Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-7 are pending in the application. Claims 1, 2, 6, and 7 are amended.
Election/Restrictions
Regarding applicant’s request for rejoinder, rejoinder is not considered at this time as the elected claims are not in condition for allowance.
Response to Arguments
Applicant’s arguments, see pg.7 of Applicant Remarks, filed 09/10/2025, with respect to the rejections of claims 1-7 under 35 U.S.C § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Funakoshi, McClusky, and Hershberger.
The applicant argues that McClusky fails to teach the elements of the amendments to claim 1, specifically, the addition of first and second DBC substrates and first and second TFTEC on the top and bottom sides of the semiconductor die. In response, the examiner introduces the disclosure of Funakoshi which teaches a multi-sided cooling arrangement that includes DBC layers for a power semiconductor module. As with the previous office action, McClusky is brought in to teach the use of active cooling elements such as TFTEC with DBC layers, while Hershberger is brought in to teach the use of a controller that controls the TFTEC operation parameters.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Funakoshi et al. (US 7671465 B2), hereinafter referred to as Funakoshi, and in further view of McClusky et al. (US 20120293962 A1), hereinafter referred to as McClusky, in further view of Hershberger et al. (US 8649179 B2), hereinafter referred to as Hershberger.
Re: the independent Claim 1:
Funakoshi teaches the power module comprising: a first direct bond copper (DBC) substrate comprising a top copper layer, a bottom copper layer, and a dielectric layer between the top copper layer and the bottom copper layer (Funakoshi Col. 2 Line 28, Fig. 1, first direct bond copper substrate comprising of top copper 7, bottom copper 9, and a dielectric layer 8);
a second DBC substrate comprising a top copper layer, a bottom copper layer, and a dielectric layer between the top copper layer and the second bottom copper layer (Funakoshi Col. 2 Line 64, Fig. 1, second direct bond copper substrate comprising of top copper 24, bottom copper 21, and a dielectric layer 23)
Funakoshi fails to teach a first thin-film thermoelectric cooler (TFTEC) comprising a thermoelectric film positioned between a top insulator and a bottom insulator; a second TFTEC comprising a thermoelectric film positioned between a top insulator and a bottom insulator one or more dies positioned over directly between the first DBC substrate and the TFTEC second DBC substrate; and a controller configured to adjust a thermoelectric device current of the first TFTEC and a thermoelectric device current of the second TFTEC responsive to a temperature of a first surface and a second surface, respectively, of the one or more dies.
However, in a related field of endeavor, McClusky teaches power module comprising a DBC substrate coupled to a thin-film thermoelectric cooler (TFTEC) comprising a thermoelectric film positioned between a top insulator and a bottom insulator (McClusky Fig. 2, [0032-0033] “As illustrated in FIG. 2, an array of thermoelectric coolers 35 can be embedded in the heat sink…TEC (6x6 20 µm-thick Bi2Te3 element array)” Where the AlN of Fig. 2 is the dielectric layers sandwiching 35 and the thickness of 20 µm is considered as a thin-film as it is similar to the thickness of the active array described within the applicant’s specifications.);
one or more dies positioned over the DBC substrate and the TFTEC (McClusky Fig. 2, [0031] “…the power module may include an IGBT chip 30” ;
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of McClusky to the disclosure of the Funakoshi in order couple a thin-film thermoelectric cooler (TFTEC) to the DBC substrates of Funakoshi. This is obvious to try as McClusky teaches that the combination of spot cooling and base cooling, where the spot cooling is achieved through the integration of a TFTEC, can lower the average junction temperature and isothermalize the surface junction temperature of the power electronic switching device (McClusky Col. 3 Line 63).
McClusky fails to teach a controller configured to adjust a thermoelectric device current of the TFTEC responsive to a temperature of the one or more dies.
However, in a related field of endeavor, Hershberger teaches a controller configured to adjust a thermoelectric device current of the TFTEC responsive to a temperature of the one or more dies (Hershberger Col. 8 Line 3, “an application specific integrated circuit (ASIC) controller 218b in communication therewith configured to help control operation of the TEM 210. As such, in this embodiment parts of the TEM 210 (via the temperature control circuit) can be used to sense thermal conditions of the circuit assembly 200.”).
Therefore it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Hershberger to the combined disclosure of Funakoshi and McClusky to include a controller configured to adjust a thermoelectric device current of the TFTEC responsive to a temperature of the one or more dies as this is a known way of controlling the cooling capabilities of a thermoelectric cooler as demonstrated by Hershberger.
Re: Claim 2: The combined disclosure of Funakoshi, McClusky and Hershberger teach the power module of claim 1.
Funakoshi teaches the module further comprising a cold plate coupled to one of the first DBC (Funakoshi Fig. 1, cold plate 11 coupled to first DBC (7, 8, 9)).
Funakoshi fails to teach the module further comprising a cold plate coupled to one of the first TFTEC
However, in a related field of endeavor, McClusky teaches the module further comprising a cold plate coupled to one of the DBC substrate and the TFTEC (McClusky Fig. 2 cold plate 15.)
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of McClusky to the disclosure of the Funakoshi in order couple a thin-film thermoelectric cooler (TFTEC) to the DBC substrates of Funakoshi where the TFTEC is further coupled to a cold plate. This is obvious to try as McClusky teaches that this is a known arrangement for a combination of spot cooling and base cooling, where the spot cooling is achieved through the integration of a TFTEC, which has the obvious result of being able to lower the average junction temperature and isothermalize the surface junction temperature of the power electronic switching device (McClusky Col. 3 Line 63).
Re: Claim 3: The combined disclosure of Funakoshi, McClusky and Hershberger teach the power module of claim 1.
Funakoshi further teaches the module wherein the one or more dies each comprise one of an Insulated Gate Bipolar Transistor (IGBT), an anti-parallel diode, a Silicon Carbide (SiC) MOSFET die, a Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) die, or a vertical GaN Junction Field Effect Transistor (JFET) die. (Funakoshi Col. 2 Line 21 “a power semiconductor element such as an IGBT or a power MOS FET, and numeral 2 denotes a power semiconductor element such as a free-wheeling diode”).
Re: Claim 4: The combined disclosure of Funakoshi, McClusky and Hershberger teach the power module of claim 1.
Funakoshi further teaches the power module wherein the dielectric layer comprises at least one of a ceramic material, silicon nitride (Si3N4), aluminum-oxide (Al2O3), and aluminum-nitride (AIN) (Funakoshi Col. 2 Lin 36 “A lower-side insulating substrate 8 is made of a material such as, e.g., aluminum nitride (AlN), alumina (Al2O3), silicon nitride (Si3N4) or boron nitride (BN)”)
Re: Claim 5: The combined disclosure of Funakoshi, McClusky and Hershberger teach the power module of claim 1.
Funakoshi fails to teach the power module wherein the thermoelectric film comprises a nano-composite thermoelectric film comprising Bi2Te3.
However, in a related field of endeavor, McClusky further teaches the power module wherein the thermoelectric film comprises a nano-composite thermoelectric film comprising Bi2Te3 (McClusky [0031]” TEC (6x6 20 µm-thick Bi2Te3 element array)”.
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of McClusky to the disclosure of the Funakoshi in order couple a thin-film thermoelectric cooler (TFTEC) to the DBC substrates of Funakoshi where the TFTEC comprises a nano-composite thermoelectric film comprising Bi2Te3. This is obvious to try as McClusky teaches that this is a known material for a TFTEC that can be implemented in a dual cooling system which has the obvious result of being able to lower the average junction temperature and isothermalize the surface junction temperature of the power electronic switching device (McClusky Col. 3 Line 63).
Re: Claim 6: The combined disclosure of Funakoshi, McClusky and Hershberger teach the power module of claim 1.
Funakoshi further teaches the power module, wherein a bottom surface of the one or more dies is secured to the top copper layer of the first DBC substrate (Funakoshi Fig. 3, bottom of IGBT die 1 secured on top copper layer 2 first DBC substrate).
Re: Claim 7: The combined disclosure of Funakoshi, McClusky and Hershberger teach the power module of claim 1.
Funakoshi and McClusky fail to teach the power module wherein a bottom surface of the one or more dies is secured to the top insulator of the first TFTEC.
However, the examiner notes that swapping the order of the cooling elements such that the bottom surface of the one or more dies would be secured to the top of the insulator of the TFTEC would be an obvious variation in the art.
Hershberger, for example, uses thermoelectric modules to directly cool electrical components in a circuit board (Hershberger Fig. 5 TFTEC 306, die 326, separated by insulator 324a).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to, apply the teaching of Hershberger to the combined disclosure of Funakoshi and McClusky in order to understand that the heat producing die could be directly coupled to the TFTEC as this is a known thermal management method as taught by Hershberger (Col 12 Line 28 “the TEM 310 functions to help control a temperature of electrical component 326 positioned on the electrical pathway 316a' of circuit board 302 by transferring heat from the electrical component 326 to circuit board 304”).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ARDEO whose telephone number is (703)756-1235. The examiner can normally be reached Mon-Fri EST.
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/EMILIO ARDEO/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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