DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 25 November 2025, with respect to claims 2, 7, 9, 14, and 16 have been fully considered and are persuasive. The 35 U.S.C. § 112 rejections of claims 2, 7, 9, 14, and 16 have been withdrawn.
Applicant’s amendments and arguments, see Remarks, filed 25 November 2025, with respect to the rejection(s) of claim(s) 1, 3-4, 6-7, 15, 17-18, and 20 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Tolentino in view of Zipprich. Please see 35 U.S.C. § 103 rejection below
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 6-7, 15, 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tolentino (US 2016/0225693 A1) and further in view of Zipprich (US 2024/0194576 A1).
Regarding claim 1 Tolentino teaches a 1.5 sided cooled power module (Figs. 12-13: 60; see ¶ 0083 and ¶ 0085; 60 is a 1.5 sided cooled power module since the bottom surface of die 18 is completely covered by downside DBC 2 and only a portion of the upper surface of the die 18 is covered by upside DBC 28, see Fig. 13) comprising:
an upside direct bond copper (DBC) (28) comprising a first top copper layer (34, see Fig. 2 and ¶0050), a first bottom copper layer (42), and a first dielectric layer (38; made of ceramic, which is known in the art to be a dielectric) between the first top copper layer and the first bottom copper layer (see Fig. 2 and ¶ 0050);
a downside DBC (2) comprising a second top copper layer (8, see Fig. 1 and ¶0049), a second bottom copper layer (16), and a second dielectric layer (12; made of ceramic) between the second top copper layer and the second bottom copper layer (see Fig. 1 and ¶ 0049);
one or more dies (18) positioned between the upside DBC and the downside DBC (Fig. 13 shows 18 between 28 and 2), wherein the downside DBC is sized to completely cover a bottommost surface (bottom surface of 18) of the one or more dies (Fig. 13 shows 2 completely covering bottom surfaces of both 18s) and the upside DBC is sized such that a portion (portions of the top surface of 18s that are not covered by 28) of an uppermost surface (top surface of 18) of the one or more dies remains an exposed portion (Fig. 13 shows 28 not completely covering the top surfaces of both 18s); and
exposed sidewalls (Fig. 2: sidewalls of 38 and 42 comprising upside DBC 28 ) of the first dielectric layer and the first bottom copper layer which are positioned over the one or more dies (Fig. 13 shows the exposed sidewalls of DBC 28 positioned over the one or more dies 18).
However, Tolentino does not teach the 1.5 sided cooled power module comprising one or more bond wires placed on the exposed portion of the one or more dies, the one or more bond wires terminating on the first top copper layer of the upside DBC, the one or more bond wires bypassing exposed sidewalls of the first dielectric layer and the first bottom copper layer.
Zipprich, in the same field of invention, teaches a 1.5 sided cooled power module (Fig. 4 shows the bottom surface of die 30 being completely covered by 16&12&14 and a portion of the top surface of 30 being covered by upside DBC 20) comprising one or more bond wires (44A, see ¶ 0025) placed on the exposed portion (38A) of the one or more dies (30, ¶ 0024: 30 is a field-effect transistor), the one or more bond wires terminating on the first top copper layer (26) of the upside DBC (20, see ¶ 0024), the one or more bond wires bypassing exposed sidewalls of the first dielectric layer (22) and the first bottom copper layer (24).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zipprich into the device of Tolentino to connect the one or more dies to the first top copper layer of the upside DBC with one or more bond wires, wherein the one or more bond wires bypassing exposed sidewalls of the first dielectric layer and the first bottom copper layer. The ordinary artisan would have been motivated to modify Tolentino in the manner set forth above for at least the purpose of connecting a control terminal (38, see Zipprich ¶ 0023) of the one or more dies (30) to a corresponding contact region (28C) of the first top copper layer for the further purpose of arranging the device structure with a free space (48) that overlaps portions of the device stack (50, see ¶ 0023, ¶ 0025) for the further purpose of adding a spacer element (40) to improve the heat dissipation of the power semiconductor device (¶ 0003-¶ 0005, ¶ 0009), which creates more space that could potentially be used for adding more cooling structures below and reducing the amount of sintering pastes (¶ 0013-¶ 0016).
Regarding claim 3, the cooled power module of claim 1, wherein the first bottom copper layer comprises a width (Tolentino Figs. 2 and 13: width of 28/42) less than a width (Figs. 1 and 13: width of 2/8) of the second top copper layer.
Regarding claim 4, the cooled power module of claim 1, wherein the one or more dies each comprise one of a central processing unit, a graphics processing unit, an application-specific integrated circuit, a metal-oxide-semiconductor field-effect transistor (MOSFET), a field-effect transistor (FET), a bipolar junction transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), and a diode (Tolentino ¶ 0048: IGBT, MOSFET).
Regarding claim 6, the cooled power module of claim 1, wherein the first top copper layer and the first bottom copper layer are directly bonded to respective surfaces (Tolentino Fig. 2: top and bottom surfaces of 38) of the first dielectric layer ( ¶ 0050: 28 is a direct bonded copper substrate, with 34 and 42 directly bonded to top and bottom surfaces of 38, respectively, without intervening adhesives), and wherein the second top copper layer and the second bottom copper layer are directly bonded to respective surfaces (Tolentino Fig. 1: top and bottom surfaces of 12 ) of the second dielectric layer (¶ 0049: 2 is a direct bonded copper substrate, with 8 and 16 directly bonded to top and bottom surfaces of 12, respectively, without intervening adhesives).
Regarding claim 7, the cooled power module of claim 1, wherein at least one of the one or more bond wires comprise a gate or kelvin source connection (Zipprich ¶ 0006: gate terminal or kelvin source terminal) that bypasses trace etching on the first top copper layer (Zipprich teaches adding a spacer 40 in between die 30 and upside DBC 20; hence Zipprich teaches bypassing trace etching on the first top copper layer 26, which would have otherwise been used to connect 26 to 30, and replace it with bond wire 44A).
Regarding claim 15, Tolentino teaches a method (Figs.1-2 and 12-13: method making a cooled power module; see ¶ 0083 and ¶ 0085) for forming a 1.5 sided cooled power module (Figs. 12-13: 60; see ¶ 0083 and ¶ 0085; 60 is a 1.5 sided cooled power module since the bottom surface of die 18 is completely covered by downside DBC 2 and only a portion of the upper surface of the die 18 is covered by upside DBC 28, see Fig. 13) comprising:
forming an upside direct bond copper (DBC) (28) comprising a first top copper layer (34, see Fig. 2 and ¶ 0050), a first bottom copper layer (42), and a first dielectric layer (38) between the first top copper layer and the first bottom copper layer (see Fig. 2 and ¶ 0050);
forming a downside DBC (2) comprising a second top copper layer (8, see Fig. 1 and ¶ 0049), a second bottom copper layer (16), and a second dielectric layer (12) between the second top copper layer and the second bottom copper layer (see Fig. 1 and ¶ 0049);
positioning one or more dies (18) between the upside DBC and the downside DBC (Fig. 13 shows 18 between 28 and 2), wherein the downside DBC is sized to completely cover a bottommost surface (bottom surface of 18) of the one or more dies (Fig. 13 shows 2 completely covering bottom surface of both 18s) and the upside DBC is sized such that a portion (portions of the top surface of 18s not covered by 28) of an uppermost surface (top surface of 18) of the one or more dies remains an exposed portion (Fig. 13 shows 28 not completely covering the top surface of both 18s); and
having exposed sidewalls (Fig. 2: sidewalls of 38 and 42 comprising upside DBC 28 ) of the first dielectric layer and the first bottom copper layer which are positioned over the one or more dies (Fig. 13 shows the exposed sidewalls of DBC 28 positioned over the one or more dies 18).
However, Tolentino does not teach the method for forming the 1.5 sided cooled power module comprising of placing one or more bond wires on the exposed portion of the one or more dies, the one or more bond wires terminating on the first top copper layer of the upside DBC, the one or more bond wires bypassing exposed sidewalls of the first dielectric layer and the first bottom copper layer.
Zipprich, in the same field of invention, teaches a method for forming a 1.5 sided cooled power module (Fig. 4 shows the bottom surface of die 30 being completely covered by 16&12&14 and a portion of the top surface of 30 being covered by upside DBC 20) comprising placing one or more bond wires (44A, see ¶ 0025) placed on the exposed portion (38A) of the one or more dies (30, ¶ 0024: 30 is a field-effect transistor), the one or more bond wires terminating on the first top copper layer (26) of the upside DBC (20, see ¶ 0024), the one or more bond wires bypassing exposed sidewalls of the first dielectric layer (22) and the first bottom copper layer (24).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zipprich into the device of Tolentino to connect the one or more dies to the first top copper layer of the upside DBC with one or more bond wires, wherein the one or more bond wires bypassing exposed sidewalls of the first dielectric layer and the first bottom copper layer. The ordinary artisan would have been motivated to modify Tolentino in the manner set forth above for at least the purpose of connecting a control terminal (38, see Zipprich ¶ 0023) of the one or more dies (30) to a corresponding contact region (28C) of the first top copper layer for the further purpose of arranging the device structure with a free space (48) that overlaps portions of the device stack (50, see ¶ 0023, ¶ 0025) for the further purpose of adding a spacer element (40) to improve the heat dissipation of the power semiconductor device (¶ 0003-¶ 0005, ¶ 0009), which creates more space that could potentially be used for adding more cooling structures below and reducing the amount of sintering pastes (¶ 0013-¶ 0016).
Regarding claim 17, the method of claim 15, wherein the first bottom copper layer comprises a width (Tolentino Figs. 2 and 13: width of 28/42) less than a width (Tolentino Figs. 2 and 13: width of 28/42) of the second top copper layer.
Regarding claim 18, the method of claim 15, wherein the one or more dies each comprise one of a central processing unit, a graphics processing unit, an application-specific integrated circuit, a metal-oxide-semiconductor field-effect transistor (MOSFET), a field-effect transistor (FET), a bipolar junction transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), and a diode (Tolentino ¶ 0048: IGBT, MOSFET).
Regarding claim 20, the method of claim 15, wherein the first top copper layer and the first bottom copper layer are directly bonded to respective surfaces (Tolentino Fig. 2: top and bottom surfaces of 38) of the first dielectric layer ( ¶ 0050: 28 is a direct bonded copper substrate, with 34 and 42 directly bonded to top and bottom surfaces of 38, respectively, without intervening adhesives ), and wherein the second top copper layer and the second bottom copper layer are directly bonded to respective surfaces (Tolentino Fig. 1: top and bottom surfaces of 12 ) of the second dielectric layer (¶0049: 2 is a direct bonded copper substrate, with 8 and 16 directly bonded to top and bottom surfaces of 12, respectively, without intervening adhesives).
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tolentino (US 2016/0225693 A1) in view of Zipprich (US 2024/0194576 A1) as applied to claim 1 and/or 15 above, and further in view of Nuotio (WO 2022/207202 A1).
Regarding claim 2, Tolentino in view of Zipprich teaches the cooled power module of claim 1, wherein the one or more bond wires comprise gate and source connections (Zipprich ¶ 0006: gate terminal or kelvin source terminal) from the one or more dies to the first top copper layer, and wherein a majority of the first top copper layer is used for cooling (Tolentino ¶ 0083: “The ability to cool the die 18 on both sides using a DBC substrate on each side”; Zipprich ¶ 0003, ¶ 0009; Furthermore, the manner of operating a device does not differentiate apparatus claim from the prior art. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). See MPEP § 2114 (I)).
However, Tolentino in view of Zipprich does not teach: wherein gate and kelvin source traces comprise an etched surface on outer boundaries of the first top copper layer of the upside DBC that is isolated from the majority of the first top copper layer.
Nuotio, in the same field of invention, teaches a power module (150, Fig. 1; see FOR mailed 02 September 2025) wherein gate (308; gate 101g connected to pad 132a of copper trace 308, see Figs. 1 and 3A and Page 14, Lines 15-20) and kelvin source traces (309; this is a Kelvin source trace, see Page 14, Lines 21-32) are etched on outer boundaries (bottom left edge of 201) of the first top copper layer of the upside DBC (201; Fig. 3A shows 308 and 309 are etched on the bottom left edge of 201) and isolated from a majority (306&307) of the first top copper layer (Fig. 3A shows 308 and 309 isolated from 306&307 ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Nuotio into the device of Tolentino in view of Zipprich to provide gate and source traces on the first top copper layer, wherein the gate and kelvin source traces are etched on outer boundaries of the first top copper layer of the upside DBC and are isolated from a majority of the first top copper layer used for cooling. The ordinary artisan would have been motivated to modify Tolentino in view of Zipprich in the manner set forth above for at least the purpose of using the Kelvin source trace as a pad to add limiting resistors (303), with the limiting resistors used for preventing excessive recirculating currents that causes high di/dt switching transients between parallel power semiconductor transistors Kelvin source bond wires (Nuotio Page 14, Lns 30-31 to Page 15, Lns 1-5), thereby improving the performance of half-bridge circuits (Nuotio Page 1).
Regarding claim 16, Tolentino in view of Zipprich teaches the method of claim 15, wherein the one or more bond wires comprise gate and source connections (Zipprich ¶ 0006: gate terminal or kelvin source terminal) from the one or more dies to the first top copper layer, and wherein a majority of the first top copper layer is used for cooling (Tolentino ¶ 0083: “The ability to cool the die 18 on both sides using a DBC substrate on each side”; Zipprich ¶ 0003, ¶ 0009).
However, Tolentino in view of Zipprich does not teach: wherein gate and kelvin source traces comprise an etched surface on outer boundaries of the first top copper layer of the upside DBC that is isolated from a majority of the first top copper layer.
Nuotio, in the same field of invention, teaches a method of forming a power module (150, Fig. 1) wherein gate (308; gate 101g connected to pad 132a of copper trace 308, see Figs. 1 and 3A and Page 14, Lines 15-20) and kelvin source traces (309; this is a Kelvin source trace, see Page 14, Lines 21-32) are etched on outer boundaries (bottom left edge of 201) of the first top copper layer of the upside DBC (201; Fig. 3A shows 308 and 309 are etched on the bottom left edge of 201) and isolated from a majority (306&307) of the first top copper layer (Fig. 3A shows 308 and 309 isolated from 306&307).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Nuotio into the device of Tolentino in view of Zipprich to provide gate and source traces on the first top copper layer, wherein the gate and kelvin source traces are etched on outer boundaries of the first top copper layer of the upside DBC and are isolated from a majority of the first top copper layer used for cooling. The ordinary artisan would have been motivated to modify Tolentino in view of Zipprich in the manner set forth above for at least the purpose of using the Kelvin source trace as a pad to add limiting resistors (303), with the limiting resistors used for preventing excessive recirculating currents that causes high di/dt switching transients between parallel power semiconductor transistors Kelvin source bond wires (Nuotio Page 14, Lns 30-31 to Page 15, Lns 1-5), thereby improving the performance of half-bridge circuits (Nuotio Page 1).
Claims 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tolentino (US 2016/0225693 A1) in view of Zipprich (US 2024/0194576 A1) as applied to claim 1 and/or claim 15 above and further in view of Choi (US 2025/0174521 A9).
Regarding claim 5, Tolentino in view of Zipprich teaches the cooled power module of claim 1, but does not teach: wherein both sides of the cooled power module are liquid cooled.
Choi, in the same field of invention, teaches a cooled power module (Fig. 6b) wherein both sides (top and bottom sides of the device between the two 150 in Fig. 6b) of the cooled power module are liquid cooled (¶ 0072; ¶ 0058: “the coolant circulating an inlet and outlet of the cooling system 150 may be a coolant fluid”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Choi into the device of Tolentino in view of Zipprich to have both sides of a power module be liquid cooled in a power module at least comprising of an upside DBC, a downside DBC, and one or more dies positioned between the upside DBC and the downside DBC. The ordinary artisan would have been motivated to modify Tolentino in view of Zipprich in the manner set forth above for at least the purpose of improving the cooling efficiency by increasing the contact area of the liquid coolant with the heat source, with the heat source being the component dies in the power module (Choi ¶ 0072, Abstract).
Regarding claim 19, Tolentino in view of Zipprich teaches the method of claim 15, but does not teach: wherein the upside DBC, downside DBC, and one or more bond wires define a cooled power module, and wherein both sides of the cooled power module are liquid cooled.
Choi, in the same field of invention, teaches a method of making a cooled power module (Fig. 6b) wherein both sides (top and bottom sides of the device between the two 150 in Fig. 6b) of the cooled power module are liquid cooled (¶ 0072; ¶ 0058: “the coolant circulating an inlet and outlet of the cooling system 150 may be a coolant fluid”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Choi into the method of Tolentino in view of Zipprich to have both sides of a power module be liquid cooled in method of making a power module at least comprising providing an upside DBC, providing a downside DBC, and positioning one or more dies between the upside DBC and the downside DBC. The ordinary artisan would have been motivated to modify Tolentino in view of Zipprich in the manner set forth above for at least the purpose of improving the cooling efficiency by increasing the contact area of the liquid coolant with the heat source, with the heat source being the component dies in the power module (Choi ¶ 0072, Abstract).
Claims 8, 10-11, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tolentino (US 2016/0225693 A1) and further in view of Zipprich (US 2024/0194576 A1) and Xu (US 10141254 B1).
Regarding claim 8, Tolentino teaches a device comprising:
a 1.5 sided cooled power module (Figs. 12-13: 60; also see ¶ 0083: “The ability to cool the die 18 on both sides using a DBC substrate on each side” and ¶ 0085 “Conventional power integrated modules (PIMs) are not double-sided cooled but instead have only a single thermal dissipation path, the path being on only one side of the package”, emphasis added; hence 60 is a cooled power module; 60 is a 1.5 sided cooled power module since the bottom surface of die 18 is completely covered by downside DBC 2 and a portion of the upper surface of the die 18 is covered by upside DBC 28, see Fig. 13), the 1.5 sided cooled power module comprising:
an upside direct bond copper (DBC) (28) comprising a first top copper layer (34, see Fig. 2 and ¶0050), a first bottom copper layer (42), and a first dielectric layer (38, made of ceramic, which is known in the art to be a dielectric) between the first top copper layer and the first bottom copper layer (see Fig. 2 and ¶ 0050);
a downside DBC (2) comprising a second top copper layer (8, see Fig. 1 and ¶ 0049), a second bottom copper layer (16), and a second dielectric layer (12, made of ceramic) between the second top copper layer and the second bottom copper layer (see Fig. 1 and ¶ 0049);
one or more dies (18) positioned between the upside DBC and the downside DBC (Fig. 13 shows 18 between 28 and 2), wherein the downside DBC is sized to completely cover a bottommost surface (bottom surface of 18) of the one or more dies (Fig. 13 shows 2 completely covering the bottom surfaces of both 18s) and the upside DBC is sized such that a portion (portions of the top surface of 18s that are not covered by 28) of an uppermost surface (top surface of 18) of the one or more dies remains an exposed portion (Fig. 13 shows 28 not completely covering the top surfaces of both 18s); and
exposed sidewalls (Fig. 2: sidewalls of 38 and 42 comprising upside DBC 28 ) of the first dielectric layer and the first bottom copper layer which are positioned over the one or more dies (Fig. 13 shows the sidewalls of DBC 28 positioned over the one or more dies 18).
However, Tolentino does not teach the 1.5 sided cooled power module comprising one or more bond wires placed on the exposed portion of the one or more dies, the one or more bond wires terminating on the first top copper layer of the upside DBC, the one or more bond wires bypassing exposed sidewalls of the first dielectric layer and the first bottom copper layer.
Zipprich, in the same field of invention, teaches a 1.5 sided cooled power module (Fig. 4 shows the bottom surface of die 30 being completely covered by 16&12&14 and a portion of the top surface of 30 being covered by upside DBC 20) comprising one or more bond wires (44A, see ¶ 0025) placed on the exposed portion (38A) of the one or more dies (30, ¶ 0024: 30 is a field-effect transistor), the one or more bond wires terminating on the first top copper layer (26) of the upside DBC (20, see ¶ 0024), the one or more bond wires bypassing exposed sidewalls of the first dielectric layer (22) and the first bottom copper layer (24).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Zipprich into the device of Tolentino to connect the one or more dies to the first top copper layer of the upside DBC with one or more bond wires, wherein the one or more bond wires bypassing exposed sidewalls of the first dielectric layer and the first bottom copper layer. The ordinary artisan would have been motivated to modify Tolentino in the manner set forth above for at least the purpose of connecting a control terminal (38, see Zipprich ¶ 0023) of the one or more dies (30) to a corresponding contact region (28C) of the first top copper layer for the further purpose of arranging the device structure with a free space (48) that overlaps portions of the device stack (50, see ¶ 0023, ¶ 0025) for the further purpose of adding a spacer element (40) to improve the heat dissipation of the power semiconductor device (¶ 0003-¶ 0005, ¶ 0009), which creates more space that could potentially be used for adding more cooling structures below and reducing the amount of sintering pastes (¶ 0013-¶ 0016).
However, Tolentino in view of Zipprich does not teach a vehicle comprising: an electric motor; and a power module coupled to the electric motor.
Xu, in the same field of invention, teaches a vehicle (Col. 1, Ln. 23-25: electric vehicles such as hybrids) comprising: an electric motor (Col. 1, Ln. 31: traction motor); and a power module (Col. 1, Ln: 30: inverter) coupled to the electric motor.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings Xu of into the device of Tolentino in view of Zipprich to couple the 1.5 sided cooled power module to an electric motor in a vehicle be comprised of the electric motor and the 1.5 sided cooled power module. The ordinary artisan would have been motivated to modify Tolentino in view of Zipprich in the manner set forth above for at least the purpose of designing an electric vehicle comprising of a half-bridge inverter having enhanced common source inductance to obtain high switching efficiency (Xu: abstract; Col. 1, Ln 16-21 and Ln 39-49), with the half-bridge inverter being a cooled power module, thereby gaining the benefits of cooling and preventing overheating while the electric motor of the vehicle is in use.
Regarding claim 10, the vehicle of claim 8, wherein the first bottom copper layer comprises a width (Tolentino Figs. 2 and 13: width of 28/42) less than a width (Figs. 1 and 13: width of 2/8) of the second top copper layer.
Regarding claim 11, the vehicle of claim 8, wherein the one or more dies each comprise one of a central processing unit, a graphics processing unit, an application-specific integrated circuit, a metal-oxide-semiconductor field-effect transistor (MOSFET), a field-effect transistor (FET), a bipolar junction transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), and a diode (Tolentino ¶ 0048: IGBT, MOSFET).
Regarding claim 13, the vehicle of claim 8, wherein the first top copper layer and the first bottom copper layer are directly bonded to respective surfaces (Tolentino Fig. 2: top and bottom surfaces of 38) of the first dielectric layer( ¶0050: 28 is a direct bonded copper substrate, with 34 and 42 directly bonded to top and bottom surfaces of 38, respectively, without intervening adhesives), and wherein the second top copper layer and the second bottom copper layer are directly bonded to respective surfaces (Tolentino Fig. 1: top and bottom surfaces of 12 ) of the second dielectric layer (¶0049: 2 is a direct bonded copper substrate, with 8 and 16 directly bonded to top and bottom surfaces of 12, respectively, without intervening adhesives).
Regarding claim 14, the vehicle of claim 8, wherein at least one of the one or more bond wires comprises a gate or kelvin source connection (Zipprich ¶ 0006: gate terminal or kelvin source terminal) that bypasses trace etching on the first top copper layer (Zipprich teaches adding a spacer 40 in between die 30 and upside DBC 20; hence Zipprich teaches replacing trace etching on the first top copper layer 26, which would have otherwise been used to connect 26 to 30, with bond wire 44A).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tolentino (US 2016/0225693 A1) in view of Zipprich (US 2024/0194576 A1) and Xu (US 10141254 B1) as applied to claim 8 above and in further view of Nuotio (WO 2022/207202 A1).
Regarding claim 9, Tolentino in view of Zipprich and Xu teaches the vehicle of claim 8, wherein the one or more bond wires comprise gate and source connections (Zipprich ¶ 0006: gate terminal or kelvin source terminal) from the one or more dies to the first top copper layer, and wherein a majority of the first top copper layer is used for cooling (Tolentino ¶ 0083: “The ability to cool the die 18 on both sides using a DBC substrate on each side”; Zipprich ¶ 0003, ¶ 0009; Furthermore, the manner of operating a device does not differentiate apparatus claim from the prior art. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). See MPEP § 2114 (I)).
However, Tolentino in view of Zipprich and Xu does not teach: wherein gate and kelvin source traces comprise an etched surface on outer boundaries of the first top copper layer of the upside DBC that is isolated from a majority of the first top copper layer.
Nuotio, in the same field of invention, teaches a power module (150, Fig. 1; see FOR mailed 02 September 2025) wherein gate (308; gate 101g is connected to pad 132a of copper trace 308, see Figs. 1 and 3A and Page 14, Lines 15-20) and kelvin source traces (309; source 101s connected to pad 131a of copper trace 309; this is a Kelvin source trace, see Page 14, Lines 21-32; Figs. 1 and 3A shows bond wires connecting gate 101g to pad 132a and bond wires connecting source 101s to pad 131a) are etched on outer boundaries (bottom left edge of 201) of the first top copper layer of the upside DBC (201; Fig. 3A shows 308 and 309 are etched on the bottom left edge of 201) and isolated from a majority (306&307) of the first top copper layer (Fig. 3A shows 308 and 309 isolated from 306&307 ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Nuotio into the device of Tolentino in view of Zipprich and Xu to provide gate and source traces on the first top copper layer, wherein the gate and kelvin source traces are etched on outer boundaries of the first top copper layer of the upside DBC and are isolated from a majority of the first top copper layer used for cooling. The ordinary artisan would have been motivated to modify Tolentino in view of Zipprich and Xu in the manner set forth above for at least the purpose of using the Kelvin source trace as a pad to add limiting resistors (303), with the limiting resistors used for preventing excessive recirculating currents that causes high di/dt switching transients between parallel power semiconductor transistors Kelvin source bond wires (Nuotio Page 14, Lns 30-31 to Page 15, Lns 1-5), thereby improving the performance of half-bridge circuits (Nuotio Page 1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tolentino (US 2016/0225693 A1) in view of Zipprich (US 2024/0194576 A1) and Xu (US 10141254 B1) as applied to claim 8 above and in further view of Choi (US 2025/0174521 A9).
Regarding claim 12, Tolentino in view of Zipprich and Xu teaches the vehicle of claim 8, but does not teach: wherein both sides of the cooled power module are liquid cooled.
Choi, in the same field of invention, teaches a cooled power module (Fig. 6b) wherein both sides (top and bottom sides of the device between the two 150 in Fig. 6b) of the cooled power module are liquid cooled (¶ 0072; ¶ 0058: “the coolant circulating an inlet and outlet of the cooling system 150 may be a coolant fluid”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Choi into the device of Tolentino in view of Zipprich and Xu to have both sides of a cooled power module be liquid cooled in vehicle comprising of an electric motor and the cooled power module, with the cooled power module at least comprising of an upside DBC, a downside DBC, and one or more dies positioned between the upside DBC and the downside DBC. The ordinary artisan would have been motivated to modify Tolentino in view of Zipprich and Xu in the manner set forth above for at least the purpose of improving the cooling efficiency by increasing the contact area of the liquid coolant with the heat source, with the heat source being the component dies in the power module (Choi ¶ 0072, Abstract).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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