DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 30 April 2026 has been entered.
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1, 13 and 26 in the Applicant’s response dated 30 April 2026. The claim amendments have been addressed below.
The Examiner acknowledges the addition of new claims 28-29 in the Applicant’s response dated 30 April 2026. The new claims have been addressed below.
The Examiner acknowledges the cancellation of claims 4-5 in the Applicant’s response dated 30 April 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-14, 17-18 and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Meng-Han Lin et al. (US 2022/0036931 A1; hereinafter “Lin”) in view of Meng-Han Lin et al. (US 2021/0398568 A1; hereinafter “Lin II”).
Regarding Claim 13, Lin teaches a semiconductor device comprising:
a first semiconductor structure including a lower interconnection structure (320, Fig. 2, para [0023] describes an interconnect structure 320 of a first semiconductor structure depicted in Fig. 2); and
a second semiconductor structure on the first semiconductor structure (58, Fig. 26C, para 0024] describes a multi-layer stack 58 formed over the substrate 50),
wherein the second semiconductor structure includes
gate electrodes stacked on the first semiconductor structure, the gate electrodes spaced apart from each other in a first direction (72, Fig. 26C, para [0026] describes conductive lines 72 of the multi-layer stack which can be seen spaced apart from each other in a first direction in Fig. 26C),
interlayer insulating layers alternately stacked with the gate electrodes (52, Fig. 26C, para [0026] describes dielectric layers 52 alternately stacked with the gate electrodes 72),
a capping insulating layer in contact with and covering the gate electrodes and the interlayer insulating layers (70, Fig. 11C, para [0072] describes a capping dielectric layer 70 in contact with and covering the gate electrodes 72 and interlayer insulating layers 52),
a first contact plug extending into the capping insulating layer, the first contact plug extending in the first direction and connected to the gate electrodes (122, Fig. 26C, para [0074] describes conductive contacts 122 extending into the capping insulating layer 70 wherein each of the first contact plugs 122 extends in a first direction and connects to a gate electrode 72A),
a second contact plug extending in the first direction, the second contact plug spaced apart from the gate electrodes and connected to the lower interconnection structure (124, Fig. 26C, para [0074] describes conductive contacts 124 extending in the first direction and connected to the circuits formed on the substrate 50 through interconnect lines 320 wherein second contact plugs 124 are spaced apart from the gate electrodes 72 by a through insulating region 102),
a connection portion connecting the first contact plug and the second contact plug, and the connection portion on the capping insulating layer (128, Fig. 26C, para [0074] describes conductive lines 128 connecting first contact plugs 122 and second contact plugs 124 wherein connection portion 128 can be seen covering on capping layer 70 above first contact plugs 122 in Fig. 26C), and
a barrier metal layer including (para [0078] describes wherein a barrier layer comprised of a metal such as titanium may be formed as a liner surrounding conductive layers 122, 124, 126, 128 and 130):
a first portion disposed on at least a portion of a side surface of the first contact plug (122, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as titanium may be formed as a liner surrounding first contact plug 122 wherein a resulting liner barrier layer would be disposed on at least a portion of a side surface of the first contact plugs 122),
a second portion disposed on at least a portion of a side surface of the second contact plug (124, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as titanium may be formed as a liner surrounding second contact plug 124 wherein a resulting liner barrier layer would be disposed on at least a portion of a side surface of the second contact plugs 124),
a third portion disposed on at least a portion of a side surface of the connection portion (128, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as titanium may be formed as a liner surrounding connecting portion 128 wherein a resulting liner barrier layer would be disposed on at least a portion of a side surface of the connection portions 128), and
a fourth portion disposed on a lower surface of the connection portion and connecting the first portion and the second portion (128, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as titanium may be formed as a liner surrounding connecting portion 128 wherein a resulting liner barrier layer would be disposed on a lower surface of connection portions connecting first portions of first contact plugs and second portions of second contact plugs),
wherein the lower surface of the connection portion is disposed between the first contact plug and the second contact plug (128, Fig. 26C depicts wherein a lower surface of connection portions 128 is disposed between the first contact plugs 122 and second contact plugs 124),
wherein the connection portion is extended to the first contact plug and the second contact plug (128, Fig. 26C depicts wherein connection portion 128 extends to the first contact plug 122 and second contact plug 124).
Lin fails to explicitly disclose wherein the lower surface of the fourth portion of the barrier metal layer is at a same level as an upper surface of the capping insulating layer.
However, Lin II teaches a similar semiconductor device, wherein the lower surface of the fourth portion of the barrier metal layer (116 and FP, annotated Fig. 27D, para [0061] describes a conductive line 116 which comprises a barrier metal layer that may be made of titanium nitride that may be deposited in the trenches comprising a lower surface as shown by fourth portion FP) is at a same level as an upper surface of the capping insulating layer (FP and 70, annotated Fig. 27D depicts wherein the fourth portion FP of the barrier metal layer formed along a lower surface of the connection portion 116 is at a same level as an upper surface of a capping insulating layer 70 deposited on and in contact with gate electrodes 72 and interlayer insulating layers 52).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lin with Lin II to further disclose a semiconductor device wherein a lower surface of a fourth portion of a barrier metal layer is at a same level as an upper surface of a capping insulating layer in order to provide the advantage of providing an adhesion layer which may promote adhesion of a conductive connection portion deposited onto an insulating capping layer further preventing separation between layers during subsequent manufacturing processes (Lin II, para [0061]).
Regarding Claim 14, the combination of Lin and Lin II teach the semiconductor device of claim 13, wherein the first portion, the second portion, the third portion, and the fourth portion of the barrier metal layer are extended to each other (Lin, 122, 124 and 126, Fig. 26C, para [0078] describes wherein the first contact plugs 122, second contact plugs 124 and connection portions 128 may be formed by forming barrier metal layers and forming conductive materials over the liners in a simultaneous process wherein a resulting barrier metal layer would extend to each other as the first contact plugs 122, second contact plugs 124 and connection portions are in contact).
Regarding Claim 17, the combination of Lin and Lin II teach the semiconductor device of claim 13, further comprising:
channel structures extending into the gate electrodes, the channel structures extending in the first direction (Lin, 92 and 98, Fig. 26C, para [0050] describes an OS layer 92, dielectric layers 98A and 98B, and a memory film 90 suitable for providing a channel region which extends into gate electrodes 72 in the first direction) and each of the channel structures including a channel layer (Lin, 92, Fig. 26C, para [0050] describes a channel OS layer 92 of the channel structure); and
bit lines connected to the channel structures (Lin, 130, Fig. 26C, para [0074] describes conductive lines 130 connected to at least one upper contact plugs 126 wherein each of the upper contact plugs are connected to at least one of the channel structures 92 through a direct connection or through electrical connection between conductive lines 130, 106/108 and 90), the bit lines on the channel structures (Lin, 130, Fig. 26C depicts wherein bit lines 130 are on channel structures 90, 92 and 98).
Regarding Claim 18, the combination of Lin and Lin II teach teaches the semiconductor device of claim 17, further comprising:
an upper insulating layer on the capping insulating layer (Lin, 121, Fig. 26C, para [0073] describes forming an upper dielectric layer 121 which can be seen as being on capping insulating layer 70), and
wherein an upper surface of the connection portion and an upper surface of the upper insulating layer are located on a same level (Lin, 121 and 128, Fig. 26C depicts wherein an upper surface of the upper insulating layer 121 and an upper surface of the connection portion 128 are located on a same level).
Regarding Claim 24, the combination of Lin and Lin II teach teaches the semiconductor device of claim 13, wherein an upper surface of the connection portion and an upper surface of the third portion of the barrier metal layer are on a same level (Lin, 128, Fig. 25C and Fig. 26C, para [0078] describe wherein a liner layer is deposited before depositing connection portion 128 wherein upon depositing a liner layer in the trench 116 of Fig. 25C prior to depositing the connection portion 128, a sidewall of the barrier metal layer liner comprising the third portion would be at a same level as the connection portion 128 in Fig. 26C).
Regarding Claim 25, the combination of Lin and Lin II teach teaches the semiconductor device of claim 13, wherein a lower surface of the fourth portion of the barrier metal layer and a side surface of the first portion of the barrier metal layer are in contact with the capping insulating layer (Lin, 128, Fig. 25C and Fig. 26C, para [0078] describe wherein a liner layer is deposited before depositing connection portion 128 and first contact plug 122 wherein upon depositing a liner layer in the trench 116 of Fig. 25C prior to depositing the connection portion 128 and first contact plug 122, a sidewall of the first contact plug barrier metal layer comprising the first portion would be at a same level as a lower surface of the fourth portion 128 deposited at a lower surface of the connection portion 128 where a lower surface of connection portion 128 meets a side surface of first contact plug 122 as shown in Fig. 26C).
Claims 1-2, 8-10, 12, 21-23, 26-27 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Meng-Han Lin et al. (US 2022/0036931 A1; hereinafter “Lin”) in view of Meng-Han Lin et al. (US 2021/0398568 A1; hereinafter “Lin II”) and in further view of Joo Won Park et al. (US 2020/0098786 A1; hereinafter “Park”).
Regarding Claim 1, Lin teaches a semiconductor device comprising:
a first semiconductor structure including a first substrate (50, Fig. 2, para [0021] describes a substrate 50 of a semiconductor structure), circuit elements on the first substrate (302, 304 and 306, Fig. 2, para [0022] describes circuit elements including gate dielectric 302, gate electrode 304 and source/drain regions 306 on the first substrate 50), and lower interconnection lines (322, Fig. 2, para [0023] describes conductive features 324 of an interconnect structure 320); and
a second semiconductor structure on the first semiconductor structure (58, Fig. 26C, para 0024] describes a multi-layer stack 58 formed over the substrate 50),
wherein the second semiconductor structure includes
a first region and a second region (FR and SR, annotated Fig. 26C depicts a first region Fr and a second region SR),
gate electrodes stacked on the second substrate the gate electrodes spaced apart from each other in a first direction (72, Fig. 26C, para [0026] describes conductive lines 72 of the multi-layer stack which can be seen spaced apart from each other in a first direction in Fig. 26C),
interlayer insulating layers alternately stacked with the gate electrodes (52, Fig. 26C, para [0026] describes dielectric layers 52 alternately stacked with the gate electrodes 72),
through-insulating regions extending into the gate electrodes in the second region, the through-insulating regions extending in a second direction (102, Fig. 26C, para [0057] describes a dielectric material 102 extending into the gate electrodes 72 and through insulating regions 52 in the second region SR and extending in a second direction and a first direction),
a capping insulating layer in contact with and covering the gate electrodes and the interlayer insulating layers, an upper insulating layer on the capping insulating layer (70 and 120, Fig. 11C and Fig. 26C, para [0041] describes a capping dielectric layer 70 in contact with and covering the gate electrodes 72 and interlayer insulating layers 52 wherein an upper insulating layer 120 can be seen on the capping insulating layer 70 in Fig. 26C),
channel structures extending into the capping insulating layer and the gate electrodes in the first region (90, 92 and 98, Fig. 26C, para [0050] describes an OS layer 92, dielectric layers 98A and 98B, and memory film 90 suitable for providing a channel region which extends into the capping insulating 70 and gate electrodes 72), each of the channel structures extending in the first direction and including a channel layer (92, Fig. 26C, para [0050] describes a channel OS layer 92 of a channel structure wherein channel OS layer 92 can be seen extending in the first direction),
upper contact plugs extending into the upper insulating layer, each of the upper contact plugs connected to at least one of the channel structures (126, Fig. 26E, para [0071] describes conductive contacts 126 extending through upper insulating layer 120 wherein Fig. 26E depicts wherein conductive contacts 126 are connected to at least one of the channel structures 92 through a direct connection or through electrical connection between conductive lines 130, 106/108 and 90),
bit lines on the upper insulating layer, each of the bit lines connected to at least one of the upper contact plugs (130, Fig. 26C, para [0074] describes conductive lines 130 connected to at least one of the upper contact plugs 126 and on upper insulating layer 120),
conductive patterns (122 and 124, Fig. 26C, para [0070] describes conductive contacts 122 and 124) including:
first contact plugs extending into the capping insulating layer in the second region, each of the first contact plugs extending in the first direction and connected to at least one of the gate electrodes (122, Fig. 26C, para [0074] describes conductive contacts 122 formed in the second region SR and extending into the capping insulating layer 70 wherein each of the first contact plugs extends in a first direction and connects to a gate electrode 72A),
second contact plugs extending into each of the through-insulating regions in the second region, the second contact plugs extending in the first direction and connected to the lower interconnection lines (124, Fig. 26C, para [0074] describes conductive contacts 124 extending into each of the through insulating regions 102 in the second region SR extending in the first direction and connected to the circuits formed on the substrate 50 through interconnect lines 320), and
connection portions extending to the first contact plugs and the second contact plugs, the connection portions extending to cover at least one of the first contact plugs (128, Fig. 26C, para [0074] describes conductive lines 128 connecting first contact plugs 122 and second contact plugs 124 wherein connection portion 128 can be seen covering at least one of top sides of first contact plugs 122 in Fig. 26C), and
a barrier metal layer on a surface of each of the conductive patterns (para [0078] describes wherein a barrier layer comprised of a metal such as titanium may be formed as a liner surrounding conductive layers 122, 124, 126, 128 and 130),
wherein the barrier metal layer includes a first portion disposed on at least a portion of a side surface of the first contact plugs (122, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as copper may be formed as a liner surrounding first contact plug 122 wherein a resulting liner barrier layer would be disposed on at least a portion of a side surface of the first contact plugs 122), a second portion disposed on at least a portion of a side surface of the second contact plugs (124, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as copper may be formed as a liner surrounding second contact plug 124 wherein a resulting liner barrier layer would be disposed on at least a portion of a side surface of the second contact plugs 124), a third portion disposed on at least a portion of a side surface of each of the connection portions (128, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as copper may be formed as a liner surrounding connecting portion 128 wherein a resulting liner barrier layer would be disposed on at least a portion of a side surface of the connection portions 128), and a fourth portion disposed on a lower surface of each of the connection portions and connecting the first portion and the second portion (128, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as copper may be formed as a liner surrounding connecting portion 128 wherein a resulting liner barrier layer would be disposed on a lower surface of connection portions connecting first portions of first contact plugs and second portions of second contact plugs),
wherein the lower surface of each of the connection portions is disposed between the first contact plugs and the second contact plugs (128, Fig. 26C depicts wherein a lower surface of connection portions 128 is disposed between the first contact plugs 122 and second contact plugs 124).
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Lin fails to explicitly disclose wherein the lower surface of the fourth portion of the barrier metal layer is at a same level as an upper surface of the capping insulating layer.
However, Lin II teaches a similar semiconductor device, wherein the lower surface of the fourth portion of the barrier metal layer (116 and FP, annotated Fig. 27D, para [0061] describes a conductive line 116 which comprises a barrier metal layer that may be made of titanium nitride that may be deposited in the trenches comprising a lower surface as shown by fourth portion FP) is at a same level as an upper surface of the capping insulating layer (FP and 70, annotated Fig. 27D depicts wherein the fourth portion FP of the barrier metal layer formed along a lower surface of the connection portion 116 is at a same level as an upper surface of a capping insulating layer 70 deposited on and in contact with gate electrodes 72 and interlayer insulating layers 52).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lin with Lin II to further disclose a semiconductor device wherein a lower surface of a fourth portion of a barrier metal layer is at a same level as an upper surface of a capping insulating layer in order to provide the advantage of providing an adhesion layer which may promote adhesion of a conductive connection portion deposited onto an insulating capping layer further preventing separation between layers during subsequent manufacturing processes (Lin II, para [0061]).
Lin and Lin II fail to explicitly teach a second substrate including a first region and a second region.
However, Park teaches a similar semiconductor device, further comprising a second substrate (110, Fig. 4, para [0039] describes upper substrates 110) including a first region (CAR, Fig. 3, para [0049] describes cell array region CAR) and a second region (CTR, Fig. 3, para [0049] describes connection region CTR).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lin and Lin II with Park to further disclose a semiconductor device comprising a second substrate in order to provide the advantage of enabling the second semiconductor substrate and first semiconductor substrate to be comprised of different materials or crystalline structures to facilitate different uses for each of the semiconductor structures (Park, para [0046]).
Regarding Claim 2, the combination of Lin, Lin II and Park teaches the semiconductor device of claim 1, wherein the first portion, the second portion, the third portion, and the fourth portion of the barrier metal layer are extended to each other (Lin, para [0078] describes wherein the first contact plugs 122, second contact plugs 124 and connection portions 128 may be formed by forming barrier metal layers and forming conductive materials over the liners in a simultaneous process wherein a resulting barrier metal layer would extend to each other as the first contact plugs 122, second contact plugs 124 and connection portions are in contact), and
the barrier metal layer surrounds further comprising a barrier metal layer surrounding an entire surface of each of the conductive patterns except for an upper surface of each of the conductive patterns (Lin, para [0078] describes wherein the first contact plugs 122, second contact plugs 124 and connection portions 128 may be formed by forming barrier metal layers and forming conductive materials over the liners in a simultaneous process wherein a liner layer formed in the aforementioned process would result in a barrier metal layer surrounding an entire surface of each of the conductive patters except for an upper surface).
Regarding Claim 8, the combination of Lin, Lin II and Park teaches the semiconductor device of claim 1, wherein each of the connection portions comprises a line pattern (Lin, 128, Fig. 26C, para [0076] describes wherein connection portions 128 are conductive lines which route connections between first contact plugs 122 and second contact plugs 124 effectively providing a line pattern connecting the contact plugs).
Regarding Claim 9, the combination of Lin, Lin II and Park teaches the semiconductor device of claim 8, wherein
the line pattern has a first width perpendicular to a longitudinal direction (Lin, FW, annotated Fig. 26A depicts wherein line pattern of first connection portion 128 has a first width FW).
Lin, Lin II and Park fail to explicitly disclose wherein the first width is equal to or greater than a diameter of each of the first contact plugs, and the first width is equal to or less than 1.2 times the diameter of each of the first contact plugs.
However, Lin depicts in Fig. 26A wherein the first width is equal to or greater than a diameter of each of the first contact plugs (FD and CPD, annotated Fig. 26A depicts wherein a first width of connection pattern 128 is essentially the same as the diameter CPD of each of the first contact plugs 122), and
the first width is equal to or less than 1.2 times the diameter of each of the first contact plugs (FD and CPD, annotated Fig. 26A depicts wherein a first width of connection pattern 128 is essentially the same as the diameter CPD of each of the first contact plugs 122).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try manufacturing the connecting region of Lin, Lin II and Park with different size contact plugs resulting in a first width of a line pattern that is equal to or up to 1.2 times greater than a diameter of the first contact plug in order to provide the well-known advantage of ensuring a proper electrical connection is maintained between the line pattern and contact plugs as well as preventing current leakage between contact plugs and other device components (see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B)).
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Regarding Claim 10, the combination of Lin, Lin II and Park teaches the semiconductor device of claim 8, wherein
the line pattern has a first width perpendicular to a longitudinal direction (Lin, FW, annotated Fig. 26A depicts wherein line pattern of first connection portion 128 has a first width FW).
Lin, Lin II and Park fail to explicitly disclose wherein the first width is equal to or greater than a diameter of each of the second contact plugs, and the first width is equal to or less than 1.2 times the diameter of each of the second contact plugs.
However, Lin depicts in Fig. 26A wherein the first width is equal to or greater than a diameter of each of the second contact plugs (FD and SPD, annotated Fig. 26A depicts wherein a first width of connection pattern 128 is essentially the same as the diameter SPD of each of the second contact plugs 124), and
the first width is equal to or less than 1.2 times the diameter of each of the second contact plugs (FD and SPD, annotated Fig. 26A depicts wherein a first width of connection pattern 128 is essentially the same as the diameter SPD of each of the second contact plugs 124).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try manufacturing the connecting region of Lin, Lin II and Park with different size contact plugs resulting in a first width of a line pattern that is equal to or up to 1.2 times greater than a diameter of the second contact plug in order to provide the well-known advantage of ensuring a proper electrical connection is maintained between the line pattern and contact plugs as well as preventing current leakage between contact plugs and other device components (see MPEP 2144.04 (IV)(A), and MPEP 2144.05 (II)(A)(B)).
Regarding Claim 12, the combination of Lin, Lin II and Park disclose all the limitations of claim 1.
Lin fails to explicitly disclose the semiconductor device of claim 1, wherein upper surfaces of the connection portions of the conductive patterns are on a same level as an upper surface of the upper insulating layer.
However, Park teaches a similar semiconductor device, wherein upper surfaces of the connection portions of the conductive patterns are on a same level as an upper surface of the upper insulating layer (Park, 124 and 178, Fig. 4, para [0045] describes an upper insulating layer 124 wherein Fig. 4 shows an upper surface of a connection portion 178 at a same level as an upper surface of upper insulating layer 124).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lin, Lin II and Park to further disclose a semiconductor device wherein upper surfaces of the connection portions of the conductive patterns are on a same level as an upper surface of the upper insulating layer in order to provide the well-known advantage of providing an upper insulating layer which encapsulates connection portions preventing current leakage from connection portions to adjacent electrical components which would negatively impact device performance.
Regarding Claim 21, the combination of Lin, Lin II and Park teaches the semiconductor device of claim 1, wherein an upper surface of the connection portions and an upper surface of the third portion of the barrier metal layer are on a same level (Lin, 128, Fig. 25C and Fig. 26C, para [0078] describe wherein a liner layer is deposited before depositing connection portion 128 wherein upon depositing a liner layer in the trench 116 of Fig. 25C prior to depositing the connection portion 128, a sidewall of the barrier metal layer liner comprising the third portion would be at a same level as the connection portion 128 in Fig. 26C).
Regarding Claim 22, the combination of Lin, Lin II and Park teaches the semiconductor device of claim 1, wherein a lower surface of the fourth portion of the barrier metal layer and a side surface of the first portion of the barrier metal layer are in contact with the capping insulating layer (Lin, 128, Fig. 25C and Fig. 26C, para [0078] describe wherein a liner layer is deposited before depositing connection portion 128 and first contact plug 122 wherein upon depositing a liner layer in the trench 116 of Fig. 25C prior to depositing the connection portion 128 and first contact plug 122, a sidewall of the first contact plug barrier metal layer comprising the first portion would be at a same level as a lower surface of the fourth portion 128 deposited at a lower surface of the connection portion 128 where a lower surface of connection portion 128 meets a side surface of first contact plug 122 as shown in Fig. 26C).
Regarding Claim 23, the combination of Lin, Lin II and Park teaches the semiconductor device of claim 1, wherein a lower surface of the first contact plugs, the lower surface of the connection portions, and a lower surface of the second contact plugs are on different levels from each other (Lin, 122, 124 and 128, Fig. 26C depicts wherein a lower surface of the first contact plugs 122 are on a same level as an upper surface of substrate 50, a lower surface of the connection portions 128 are on a same level as an upper surface of dielectric layer 120 and a lower surface of second contact plugs 122 are on a same level as an upper surface of gate electrode 72A all of which being on different levels from each other).
Regarding Claim 26, Lin teaches a semiconductor device comprising:
a first semiconductor structure including a first substrate (50, Fig. 2, para [0021] describes a substrate 50 of a semiconductor structure), circuit elements on the first substrate (302, 304 and 306, Fig. 2, para [0022] describes circuit elements including gate dielectric 302, gate electrode 304 and source/drain regions 306 on the first substrate 50), and lower interconnection lines (322, Fig. 2, para [0023] describes conductive features 324 of an interconnect structure 320); and
a second semiconductor structure on the first semiconductor structure (58, Fig. 26C, para 0024] describes a multi-layer stack 58 formed over the substrate 50),
wherein the second semiconductor structure includes
a first region and a second region (FR and SR, annotated Fig. 26C depicts a first region Fr and a second region SR),
gate electrodes stacked on the second substrate the gate electrodes spaced apart from each other in a first direction (72, Fig. 26C, para [0026] describes conductive lines 72 of the multi-layer stack which can be seen spaced apart from each other in a first direction in Fig. 26C),
interlayer insulating layers alternately stacked with the gate electrodes (52, Fig. 26C, para [0026] describes dielectric layers 52 alternately stacked with the gate electrodes 72),
through-insulating regions extending into the gate electrodes in the second region, the through-insulating regions extending in a second direction (102, Fig. 26C, para [0057] describes a dielectric material 102 extending into the gate electrodes 72 and through insulating regions 52 in the second region SR and extending in a second direction and a first direction),
a capping insulating layer in contact with and covering the gate electrodes and the interlayer insulating layers, an upper insulating layer on the capping insulating layer (70 and 120, Fig. 11C and Fig. 26C, para [0041] describes a capping dielectric layer 70 in contact with and covering the gate electrodes 72 and interlayer insulating layers 52 wherein an upper insulating layer 120 can be seen on the capping insulating layer 70 in Fig. 26C),
channel structures extending into the capping insulating layer and the gate electrodes in the first region (90, 92 and 98, Fig. 26C, para [0050] describes an OS layer 92, dielectric layers 98A and 98B, and memory film 90 suitable for providing a channel region which extends into the capping insulating 70 and gate electrodes 72), each of the channel structures extending in the first direction and including a channel layer (92, Fig. 26C, para [0050] describes a channel OS layer 92 of a channel structure wherein channel OS layer 92 can be seen extending in the first direction),
upper contact plugs extending into the upper insulating layer, each of the upper contact plugs connected to at least one of the channel structures (126, Fig. 26E, para [0071] describes conductive contacts 126 extending through upper insulating layer 120 wherein Fig. 26E depicts wherein conductive contacts 126 are connected to at least one of the channel structures 92 through a direct connection or through electrical connection between conductive lines 130, 106/108 and 90),
bit lines on the upper insulating layer, each of the bit lines connected to at least one of the upper contact plugs (130, Fig. 26C, para [0074] describes conductive lines 130 connected to at least one of the upper contact plugs 126 and on upper insulating layer 120),
conductive patterns (122 and 124, Fig. 26C, para [0070] describes conductive contacts 122 and 124) including:
first contact plugs extending into the capping insulating layer in the second region, each of the first contact plugs extending in the first direction and connected to at least one of the gate electrodes (122, Fig. 26C, para [0074] describes conductive contacts 122 formed in the second region SR and extending into the capping insulating layer 70 wherein each of the first contact plugs extends in a first direction and connects to a gate electrode 72A),
second contact plugs extending into each of the through-insulating regions in the second region, the second contact plugs extending in the first direction and connected to the lower interconnection lines (124, Fig. 26C, para [0074] describes conductive contacts 124 extending into each of the through insulating regions 102 in the second region SR extending in the first direction and connected to the circuits formed on the substrate 50 through interconnect lines 320), and
connection portions integral with the first contact plugs and the second contact plugs, the connection portions extending to cover an upper surface of at least one of the first contact plugs (128, Fig. 26C, para [0074] describes conductive lines 128 connecting first contact plugs 122 and second contact plugs 124 wherein connection portion 128 can be seen covering at least one of the upper surfaces of first contact plugs 122 in Fig. 26C and further wherein para [0078] describes wherein connection portions 128, first contact plugs 122 and second contact plugs 124 may be formed simultaneously resulting in the connection portions 128, first contact plugs 122 and second contact plugs 124 being integral), and
a barrier metal layer on a surface of each of the conductive patterns (para [0078] describes wherein a barrier layer comprised of a metal such as titanium may be formed as a liner surrounding conductive layers 122, 124, 126, 128 and 130),
wherein the barrier metal layer includes a first portion disposed on at least a portion of a side surface of the first contact plugs (122, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as copper may be formed as a liner surrounding first contact plug 122 wherein a resulting liner barrier layer would be disposed on at least a portion of a side surface of the first contact plugs 122), a second portion disposed on at least a portion of a side surface of the second contact plugs (124, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as copper may be formed as a liner surrounding second contact plug 124 wherein a resulting liner barrier layer would be disposed on at least a portion of a side surface of the second contact plugs 124), a third portion disposed on at least a portion of a side surface of each of the connection portions (128, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as copper may be formed as a liner surrounding connecting portion 128 wherein a resulting liner barrier layer would be disposed on at least a portion of a side surface of the connection portions 128), and a fourth portion disposed on a lower surface of each of the connection portions and connecting the first portion and the second portion (128, Fig. 26C, para [0078] describes wherein a barrier layer comprised of a metal such as copper may be formed as a liner surrounding connecting portion 128 wherein a resulting liner barrier layer would be disposed on a lower surface of connection portions connecting first portions of first contact plugs and second portions of second contact plugs),
wherein the lower surface of each of the connection portions is disposed between the first contact plugs and the second contact plugs (128, Fig. 26C depicts wherein a lower surface of connection portions 128 is disposed between the first contact plugs 122 and second contact plugs 124).
Lin fails to explicitly disclose wherein the lower surface of the fourth portion of the barrier metal layer is at a same level as an upper surface of the capping insulating layer.
However, Lin II teaches a similar semiconductor device, wherein the lower surface of the fourth portion of the barrier metal layer (116 and FP, annotated Fig. 27D, para [0061] describes a conductive line 116 which comprises a barrier metal layer that may be made of titanium nitride that may be deposited in the trenches comprising a lower surface as shown by fourth portion FP) is at a same level as an upper surface of the capping insulating layer (FP and 70, annotated Fig. 27D depicts wherein the fourth portion FP of the barrier metal layer formed along a lower surface of the connection portion 116 is at a same level as an upper surface of a capping insulating layer 70 deposited on and in contact with gate electrodes 72 and interlayer insulating layers 52).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lin with Lin II to further disclose a semiconductor device wherein a lower surface of a fourth portion of a barrier metal layer is at a same level as an upper surface of a capping insulating layer in order to provide the advantage of providing an adhesion layer which may promote adhesion of a conductive connection portion deposited onto an insulating capping layer further preventing separation between layers during subsequent manufacturing processes (Lin II, para [0061]).
Lin and Lin II fail to explicitly teach a second substrate including a first region and a second region.
However, Park teaches a similar semiconductor device, further comprising a second substrate (110, Fig. 4, para [0039] describes upper substrates 110) including a first region (CAR, Fig. 3, para [0049] describes cell array region CAR) and a second region (CTR, Fig. 3, para [0049] describes connection region CTR).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lin and Lin II with Park to further disclose a semiconductor device comprising a second substrate in order to provide the advantage of enabling the second semiconductor substrate and first semiconductor substrate to be comprised of different materials or crystalline structures to facilitate different uses for each of the semiconductor structures (Park, para [0046]).
Regarding Claim 27, the combination of Lin, Lin II and Park teaches the semiconductor device of claim 26, wherein the first portion, the second portion, the third portion, and the fourth portion of the barrier metal layer are integral with each other (Lin, 122, 124 and 128, Fig. 26C, para [0078] describes wherein connection portions 128, first contact plugs 122 and second contact plugs 124 may be formed simultaneously resulting in the metal barrier layer of connection portions 128, first contact plugs 122 and second contact plugs 124 forming the first portion, second portion, third portion, and the fourth portion being integral).
Regarding Claim 29, the combination of Lin, Lin II and Park discloses all the limitations of claim 1.
Lin and Park fail to explicitly disclose the semiconductor device of claim 1, wherein a lower surface of the upper contact plugs is at a same level as the lower surface of the fourth portion of the barrier metal layer.
However, Lin II teaches a similar semiconductor device, semiconductor device of claim 1, wherein a lower surface of the upper contact plugs (122, Fig. 28B, para [0064] describes contacts 122 contacting channel structures 106 and 92 wherein the upper contact plugs 122 have a lower surface planar with a lower surface of a dielectric layer 120) is at a same level as the lower surface of the fourth portion of the barrier metal layer (FP, 116 and 120, annotated Fig. 27D depicts wherein the lower surface of the fourth portion FP of the barrier metal layer of connecting portion 116 is planar with a lower surface of the dielectric layer 120 putting the lower surface of the upper contact plugs 122 and lower surface of the fourth portion FP of the barrier metal layer at a same level).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lin, Lin II and Park to further disclose a semiconductor device wherein a lower surface of upper contact plugs is at a same level as a lower surface of a fourth portion of a barrier metal layer in order to provide the well-known advantage of enabling a dielectric layer to surround adjacent conductive components preventing current leakage between the adjacent conductive components and further simplifying the manufacturing process.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Meng-Han Lin et al. (US 2022/0036931 A1; hereinafter “Lin”) in view of Meng-Han Lin et al. (US 2021/0398568 A1; hereinafter “Lin II”) and in view of Joo Won Park et al. (US 2020/0098786 A1; hereinafter “Park”) and in further view of Jee-Yeon Kim (US 2020/0357811 A1; hereinafter “Kim”).
Regarding Claim 11, the combination of Lin, Lin II and Park disclose all the limitations of claim 1.
The combination of Lin, Lin II and Park fail to disclose the semiconductor device of claim 1, wherein upper surfaces of the connection portions of the conductive patterns are on a same level as lower surfaces of the bit lines.
However, Kim teaches a similar semiconductor device wherein upper surfaces of the connection portions of the conductive patterns (186, Fig. 23A, para [0197] describes interconnect metal lines 186 connecting portions of a first and second contact plug) are on a same level as lower surfaces of the bit lines (318 and 302, Fig. 23B, para [0213] describes a multi-level bit line structure (318 and 302) wherein a lower surface of the bit line structure 302 can be seen on a same level as an upper surface of the interconnect metal line 186).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lin, Lin II and Park with the teachings of Kim to further disclose a semiconductor device comprising a bit line structure which has a lower surface at a same level as an upper surface of an upper surface of a connection portion in order to provide the advantage of providing a set of bit lines that can be used to provide electrical connection to a through via without reducing the density of bit lines (Kim, para [0223]).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Meng-Han Lin et al. (US 2022/0036931 A1; hereinafter “Lin”) in view of Meng-Han Lin et al. (US 2021/0398568 A1; hereinafter “Lin II”) and in view of Joo Won Park et al. (US 2020/0098786 A1; hereinafter “Park”) and in further view of Jang-Gn Yun et al. (US 2016/0225714 A1; hereinafter “Yun”).
Regarding Claim 28, the combination of Lin, Lin II and Park discloses all the limitations of claim 1.
Lin, Lin II and Park fail to explicitly disclose the semiconductor device of claim 1, wherein the second portion of the barrier metal layer is in contact with at least one of the interlayer insulating layers.
However, Yun teaches a similar semiconductor device, wherein the second portion of the barrier metal layer (181, Fig. 5B, para [0146] describes a cell contact structure 179b comprising an outer conductive layer 181 surrounding an inner conductive layer 182 wherein side surfaces of the barrier metal layer 181 comprising a metal nitride such as titanium nitride form a second portion) is in contact with at least one of the interlayer insulating layers (181 and 120, Fig. 5B, para [0129] describes insulating patterns 120 comprising an interlayer insulating layer structure wherein the second side portions of the barrier metal layer 181 are in contact with at least one of the interlayer insulating layers 120).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Lin, Lin II and Park with the teachings of Yun to further disclose a semiconductor device wherein a second portion of a barrier metal layer is in contact with at least one of a plurality of interlayer insulating layers in order to provide the well-known advantage of providing a barrier metal layer between a conductive plug structure and an interlayer insulating layer preventing diffusion of conductive materials into the surrounding dielectric layers and to promote adhesion between the contact structure and the surrounding dielectric layers.
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 8-14, 17-18 and 21-29 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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