Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 is rejected because “the cost function” lacks antecedent basis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6 and 8 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Kaufman (US 2003/0177455)
Regarding claim 1, the prior art discloses:
A method for generating placement and routing for a netlist of an IC design, comprising:
partitioning the netlist for the IC design into subsets of cells (dividing cells into groups (par 14), netlist that has its logic circuits partitioned into clusters is referred to as a "cluster-partitioned netlist", netlist partitioned into clusters,
netlist that is cluster partitioned (fig 9, par 112, 132, 136));
prioritizing (ranking cells, rank order, priority value/ table/ forward /backward, optimization according to a metric based, timing slack order/sorting (fig 9-10, 12, 14, par 17-18, 85) ) the subsets of cells;
placing (see place and route /physical design in abstract/summary, fig 1b) a first subset of cells with a first priority in an arrangement representing the IC design;
routing (see place and route / physical design in abstract/summary, fig 1b) wire connections between the cells of the first subset of cells;
placing a second subset of cells (see re-place, re-route, physical design iteration/optimization, placement and routing loop (abstract, par 9, 12, 15-16, 67, 70) cluster by cluster physical design optimization/repeating/iteration (par 112, 132)) relative to one another and the first subset of cells in the arrangement representing the IC design; and
routing cells (see re-place, re-route, physical design iteration/ optimization, placement and routing loop (abstract, par 9, 12, 15-16, 67, 70) cluster by cluster physical design optimization/repeating/iteration (par 112, 132)) wire connections between the cells of the second subset of cells and the cells of the first subset of cells.
(Claim 2) wherein placing the second subset of cells occurs after placing and routing the first subset of cells (see re-place, re-route, physical design iteration/ optimization, placement and routing loop (abstract, par 9, 12, 15-16, 67, 70) cluster by cluster physical design optimization/repeating/iteration (par 112, 132)) .
(Claim 3) repeatedly placing and routing subsets of the cells with previously placed and routed subsets of cells until the arrangement is complete (see re-place, re-route, physical design iteration/ optimization, placement and routing loop (abstract, par 9, 12, 15-16, 67, 70) cluster by cluster physical design optimization/repeating/iteration (par 112, 132)) .
(Claim 6) wherein the cost function (par 7, 10, 70) comprises at least one of: STA derived criticality based on negative slacks; topologically with k-means to cluster local interconnect together and identify native partitions; common clock domain; or input/output (IO) placement (one or more of fig 9, 20-22, 24-25, par 85, 96-97, 136).
(Claim 8) optimizing the arrangement by: repeating all the steps with new subsets of cells having a different number of subsets of cells than before, subsets of cells with different sizes than before or both (see re-place/re-route optimization in abstract and/or optimization/ iteration/ repeating/ looping process in fig 1-2, 4-8, 10, 12, 14, 19, 21-22), in order to define a second arrangement; and selecting the arrangement or the second arrangement based on a fastest frequency of the arrangement or the second arrangement (see re-place/re-route optimization in abstract and/or optimization/ iteration/ repeating/ looping process in fig 1-2, 4-8, 10, 12, 14, 19, 21-22)
Claims 1-3, 6-8 are rejected under 35 U.S.C. 102(a) (2) being anticipated by the prior art of record Lu (US 2023/0376659)
Regarding claim 1, the prior art discloses:
A method for generating placement and routing for a netlist of an IC design, comprising:
partitioning the netlist for the IC design into subsets of cells (Cell clustering in fig 1);
prioritizing the subsets of cells (PPA metrics (abstract) higher/lower probability (par 40-41), congestion score (par 50), priority level (par 67));
placing (fig 1B-C) a first subset of cells with a first priority in an arrangement representing the IC design;
routing (fig 1C ) wire connections between the cells of the first subset of cells;
placing a second subset (placement optimization (abstract/summary), repeat process (fig 1B)) of cells relative to one another and the first subset of cells in the arrangement representing the IC design; and
routing (subsequent/post route (par 22, 30)) wire connections between the cells of the second subset of cells and the cells of the first subset of cells.
(Claim 2) wherein placing the second subset of cells occurs after placing and routing the first subset of cells (fig 1).
(Claim 3) repeatedly placing and routing subsets of the cells with previously placed and routed subsets of cells until the arrangement is complete (process repeat (par 5), updating/optimizing metrics (par 38), cluster training/iteration/optimization (par 42-43, 49)).
(Claim 6) wherein the cost function comprises at least one of: static time analysis (STA) derived criticality based on negative slacks; topologically with k-means to cluster local interconnect together and identify native partitions; common clock domain; or input/output (IO) placement (see at least one of par 21, 42, 55)
(Claim 7) wherein the partitioning is based on machine learning (ML) with an ML classifier that ranked subsets of cells from a generated dataset of subsets of cells (see one or more of fig 5C, par 45-46, 55-56, 59-61)3
(Claim 8) optimizing the arrangement by:
repeating all the steps with new subsets of cells having a different number of subsets of cells than before, subsets of cells with different sizes than before, or both, in order to define a second arrangement; and selecting the arrangement or the second arrangement based on a fastest frequency of the arrangement or the second arrangement /partition (see optimization/ looping/ repeating/ iteration process of Placement/routing in one or more of fig 1-3)
Claims 1-3 6, 8, and 11-12 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Ang (US 2008/0201678)
Regarding claim 1, the prior art discloses:
A method for generating placement and routing for a netlist of an IC design, comprising:
partitioning the netlist (par 4, 36, 46, 56) for the IC design into subsets of cells (i.e., clusters/groups of cells (par 11, 35-38, 54-55, fig 7-8));
prioritizing (cluster of cells with lowest/high routing congestion; larger /lowest slack (par 10, 35-37, 53), lowest slack/congestion score, score function, (par 41, 46-47, 53)) the subsets of cells;
placing (fig 2-6) a first subset of cells with a first priority in an arrangement representing the IC design;
routing (fig 2-6) wire connections between the cells of the first subset of cells;
placing a second subset of cells relative to one another and the first subset of cells in the arrangement representing the IC design (see loop/ repeal /iteration /optimizing process in fig 2-6); and
routing wire connections between the cells of the second subset of cells and the cells of the first subset of cells design (see loop/ repeal /iteration /optimizing process in fig 2-6).
(Claim 2) wherein placing the second subset of cells occurs after placing and routing the first subset of cells design (see loop/ repeal /iteration /optimizing process in fig 2-6).
(Claim 3) repeatedly placing and routing subsets of the cells with previously placed and routed subsets of cells until the arrangement is complete (see loop/ repeal /iteration /optimizing process in fig 2-6).
(Claim 6) wherein the cost function comprises at least one of: static time analysis (STA) derived criticality based on negative slacks; topologically with k-means to cluster local interconnect together and identify native partitions; common clock domain; or input/output (IO) placement (par 40, 44, 49)
(Claim 8) optimizing the arrangement by:
repeating all the steps with new subsets of cells having a different number of subsets of cells than before, subsets of cells with different sizes than before, or both, in order to define a second arrangement; and selecting the arrangement or the second arrangement based on a fastest frequency of the arrangement or the second arrangement (see optimization/ looping/ repeating/ iteration process of Placement/routing/partition in one or more of fig 2-6)
(Claim 11) wherein partitioning the netlist is based on a cost function; evaluating the cost function after placing and routing one or more subsets of cells; changing the cost function or selecting a new cost function (par 40, 44, 49) ; re-partitioning all or some of the subsets of cells based on the changed cost function or the new cost function; and evaluating the changed cost function or the new cost function after placing and routing one or more subsets of cells complete (see loop/ repeal /iteration /optimizing process in fig 2-6).
(Claim 12) wherein the IC design comprises a FPGA and the cells comprise logic blocks and memory elements (par 4, 39, 55-56).
Claims 1-4 and 8 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Verma (US 2015/0248519)
Regarding claim 1, the prior art discloses: A method for generating placement and routing for a netlist of an IC design, comprising:
partitioning ( see one or more of par 4, 12-15 and/or fig 4-6) the netlist for the IC design into subsets of cells;
prioritizing the subsets of cells (i.e., in terms of one or more of excessive timing slack, power consumption, timing budget (par 4-6 and/or Fig 4-6);
placing (fig 4) a first subset of cells with a first priority in an arrangement representing the IC design;
routing (fig 4) wire connections between the cells of the first subset of cells;
placing a second subset of cells relative to one another and the first subset of cells in the arrangement representing the IC design (see optimization/ repeat/ iteration/ loop process in fig 4); and
routing wire connections between the cells of the second subset of cells and the cells of the first subset of cells (see optimization/ repeat/ iteration/ loop process in fig 4)
(Claim 2) wherein placing the second subset of cells occurs after placing and routing the first subset of cells (see optimization/ repeat/ iteration/ loop process in fig 4)
(Claim 3) repeatedly placing and routing subsets of the cells with previously placed and routed subsets of cells until the arrangement is complete (see optimization/ repeat/ iteration/ loop process in fig 4)
(Claim 4) calculating an initial frequency of the IC design based on the first subset of cells prior to placing and routing the second subset of cells in order to define an upper bound frequency (see clock/frequency in par 27, 34-35 and/or fig 9)
(Claim 8) optimizing the arrangement by:
repeating all the steps with new subsets of cells having a different number of subsets of cells than before, subsets of cells with different sizes than before, or both, in order to define a second arrangement; and selecting the arrangement or the second arrangement based on a fastest frequency of the arrangement or the second arrangement (see optimization/ looping/ repeating/ iteration process of Placement/routing/partition in fig 4)
Claims 1-4, 6, 8 and 11 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Boyle (US 2001/0010090)
Regarding claim 1, the prior art discloses:
A method for generating placement and routing for a netlist of an IC design, comprising:
Partitioning (see one or more of par 11, 13, 38-39, 42, 57, 59, 73-75, 87, 96-97, 116) the netlist for the IC design into subsets of cells;
prioritizing the subsets of cells (i.e., cost function, constraints, min/max congestion (par 11, 85-99. 101-102) “K” function/partitioning, highest level of partitioning, (par 54, 74));
placing a first subset of cells with a first priority in an arrangement representing the IC design (see layout/placement and routing in fig 2-3, 5-7);
routing wire connections between the cells of the first subset of cells; placing a second subset of cells relative to one another and the first subset of cells in the arrangement representing the IC design (see layout/placement and routing in fig 2-3, 5-7); and
routing wire connections between the cells of the second subset of cells and the cells of the first subset of cells (see update/ improve/optimization/ loop/ repeat/ iteration layout/placemen/partition and routing in fig 2-3, 5-7)
(Claim 2) wherein placing the second subset of cells occurs after placing and routing the first subset of cells (see update/ improve/optimization/ loop/ repeat/ iteration layout/placemen/partition and routing in fig 2-3, 5-7)
(Claim 3) repeatedly placing and routing subsets of the cells with previously placed and routed subsets of cells until the arrangement is complete (see update/ improve/optimization/ loop/ repeat/ iteration layout/placemen/partition and routing in fig 2-3, 5-7)
(Claim 4): calculating an initial frequency of the IC design based on the first subset of cells prior to placing and routing the second subset of cells in order to define an upper bound frequency (par 52, 54, 64)
(Claim 6) wherein the cost function (see one or more of abstract, par 10-12, 16, 32, 38, 68, 75, 82, 84-86, 91, 94, 97-98, 101) comprises at least one of: static time analysis (STA) derived criticality based on negative slacks; topologically with k-means to cluster local interconnect together and identify native partitions; common clock domain; or input/output (IO) placement.
(Claim 8) optimizing the arrangement by: repeating all the steps with new subsets of cells having a different number of subsets of cells than before, subsets of cells with different sizes than before, or both, in order to define a second arrangement; and selecting the arrangement or the second arrangement based on a fastest frequency of the arrangement or the second arrangement (see update/ improve/optimization/ loop/ repeat/ iteration layout/placemen/partition and routing in fig 2-3, 5-7)
(Claim 11) wherein partitioning the netlist is based on a cost function (see one or more of abstract, par 11-12, 16, 32, 38, 68, 75, 82, 84-86, 91, 94, 97-98, 101); evaluating the cost function after placing and routing one or more subsets of cells; changing the cost function or selecting a new cost function (see one or more of abstract, par 11-12, 16, 32, 38, 68, 75, 82, 84-86, 91, 94, 97-98, 101); re-partitioning all or some of the subsets of cells based on the changed cost function or the new cost function; and evaluating the changed cost function or the new cost function after placing and routing one or more subsets of cells (see update/ improve/optimization/ loop/ repeat/ iteration layout/placemen/partition and routing in fig 2-3, 5-7)
Allowable Subject Matter
Claims 5, 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-19 are allowed.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/ Primary Examiner, Art Unit 2851