DETAILED ACTION
This action is responsive to the application No. 18/150,775 filed on January 05, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 11/18/2025 responding to the Office action mailed on 08/18/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-6, 8, and 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2015/0349073) in view of Jimenez (“The influence of poly-Si/SiGe gate in CMOS transistors for RF and microwave circuit applications”, Phys. Status Solidi C 7, No. 2, 440-443 (2010)).
Regarding Claim 1, Kang (see, e.g., Figs. 2A, 10), teaches a semiconductor structure, comprising:
a base substrate 201, wherein a gate trench 205 and a source/drain region 216/217 positioned on two sides of the gate trench 205 are formed in the base substrate 201 (see, e.g., pars. 0031-0033);
a gate dielectric layer 206 covering a bottom wall and a side wall of the gate trench 205 (see, e.g., par. 0034);
a metal gate 208, a top surface of the metal gate 208 being lower than a bottom surface of the source/drain region 216/217, the metal gate 208 comprising a conductive layer 211 and a barrier layer 209 positioned between the conductive layer 211 and the gate dielectric layer 206, wherein the conductive layer 211 is filled in the gate trench 205, and the conductive layer 211 covers a surface of the barrier layer 209 (see, e.g., pars. 0035-0036);
a hybrid gate 212 stacked on the metal gate 208, a top surface of the hybrid gate 212 being lower than a surface of the base substrate 201, and the hybrid gate 212 comprising a layer 214 and a work function layer 213 (see, e.g., pars. 0035-0036, 0043); and
an isolation layer 215 stacked on the hybrid gate 212, the isolation layer 215 filling up the gate trench 205 (see, e.g., par. 0038); and
a buffer layer 519/523 positioned on a surface of the source/drain region 216/217 (see, e.g., pars. 0111, 0113).
Kang does not teach that the hybrid gate comprises a doped conductive layer, wherein a material of the doped conductive layer comprises a mixture of a germanium-silicon material and polysilicon; and the doped conductive layer is annealed for recrystallization to obtain germanium-silicon polysilicon having high penetration degree to dopant ions.
Jimenez, on the other hand, in similar CMOS devices to Kang, teaches a gate comprising a doped conductive layer, wherein a material of the doped conductive layer comprises a mixture of a germanium-silicon material and polysilicon, to reduce gate depletion and DC characteristics in CMOS transistors. The drive current turn-on in the I-V characteristics increases compared with conventional CMOS transistors with poly-Si gate and devices show low 1/f noise which make them promising devices for RF and micro-wave circuit applications (see, e.g., pg. 440).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Kang’s device, a hybrid gate comprising a doped conductive layer, wherein a material of the doped conductive layer comprises a mixture of a germanium-silicon material and polysilicon, as taught by Jimenez, to reduce gate depletion and DC characteristics in CMOS transistors. The drive current turn-on in the I-V characteristics increases compared with conventional CMOS transistors with poly-Si gate and devices show low 1/f noise which make them promising devices for RF and micro-wave circuit applications.
With respect to the claim limitation that “the doped conductive layer is annealed for recrystallization to obtain germanium-silicon polysilicon having high penetration degree to dopant ions”, note that a “product-by-process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which make it clear that it is the final product per se which must determine in a “product-by-process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product-by-process” claim or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935).
NOTE that the applicant has burden of proof in such cases as the above case law makes clear.
In reference to the claimed process step that “the doped conductive layer is annealed for recrystallization to obtain germanium-silicon polysilicon having high penetration degree to dopant ions”, this is considered an intermediate method step that does not affect the structure of the final device.
As to the grounds of rejection under section 103, see MPEP §2113 which discusses the handling of “product-by-process” claims and recommends the alternative (§ 102/§ 103) grounds of rejection.
Regarding Claim 2, Kang and Jimenez teach all aspects of claim 1. Kang (see, e.g., Figs. 2A, 10), teaches that:
the work function layer 213 positioned between the doped conductive layer 214 (i.e., doped conductive layer disclosed by Jimenez) and the gate dielectric layer 206;
wherein the doped conductive layer 214 covers a surface of the work function layer 213, and the work function layer 213 is configured to separate the doped conductive layer 214 from the metal gate 208.
Regarding Claim 3, Kang and Jimenez teach all aspects of claim 2. Kang (see, e.g., Figs. 2A, 10), teaches that a cross section of the work function layer 213 is U-shaped along an extension direction of the gate trench 205.
Regarding Claim 4, Kang and Jimenez teach all aspects of claim 2. Kang (see, e.g., Figs. 2A, 10), teaches that a top surface of the doped conductive layer 214 is flush with a top surface of the work function layer 213.
Regarding Claim 6, Kang and Jimenez teach all aspects of claim 1. Kang (see, e.g., Figs. 2A, 10), teaches, wherein a top surface of the conductive layer 211 is flush with a top surface of the barrier layer 209.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2015/0349073) in view of Jimenez (“The influence of poly-Si/SiGe gate in CMOS transistors for RF and microwave circuit applications”, Phys. Status Solidi C 7, No. 2, 440-443 (2010)) and further in view of Schröder (US 2017/0256552).
Regarding Claim 5, Kang and Jimenez teach all aspects of claim 2. Kang (see, e.g., Figs. 2A, 10), teaches that a material of the work function layer 213 comprises W, WC, TiAl, TiC, TiAlC (see, e.g., par. 0043).
Kang is silent with respect to the claim limitation that a material of the work function layer 213 comprises silicon carbide or doped silicon carbide.
Kang discloses the claimed invention except for the use of W, WC, TiAl, TiC, TiAlC as a material of the work function layer instead of silicon carbide or doped silicon carbide. Schröder (see, e.g., par. 0061), on the other hand teaches that SiC and W are equivalent materials known in the art. Therefore, because these workfunction materials were art-recognized equivalents at the time of the invention, one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, one of ordinary skill in the art would have found it obvious to substitute SiC for W since the substitution would yield predictable results. See Supreme Court decision in KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 YSPQ2d 1385 (2007).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2015/0349073) in view of Jimenez (“The influence of poly-Si/SiGe gate in CMOS transistors for RF and microwave circuit applications”, Phys. Status Solidi C 7, No. 2, 440-443 (2010)) and further in view of Takahashi (US 2012/0018740).
Regarding Claim 8, Kang and Jimenez teach all aspects of claim 1. Kang (see, e.g., Figs. 2A, 10), teaches that a material of the buffer layer comprises polysilicon, metal silicide, metal nitride, and metal (see, e.g., pars. 0111, 0113). Kang does not teach that a material of the buffer layer comprises silicon carbide; and/or the buffer layer is doped with a dopant ion therein.
Takahashi, on the other hand, teaches that a material of the buffer layer comprises silicon carbide; and/or the buffer layer is doped with a dopant ion therein to form a source contact having an ohmic junction (see, e.g., par. 0120).
It would have been obvious to one of ordinary skill in the art at the time of filing to have in Kang’s device, a material of the buffer layer comprising silicon carbide; and/or be doped with a dopant ion therein, as taught by Takahashi, to form a source contact having an ohmic junction.
Regarding Claim 9, Kang, Jimenez, and Takahashi teach all aspects of claim 8. Takahashi teaches that the dopant ion comprises a titanium ion (see, e.g., par. 0120).
Response to Arguments
Applicant’s arguments filed on 11/18/2025 with respect to the rejection of claim 1 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/Primary Examiner, Art Unit 2814
Prosecution Insights