DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on October 22,2025 is acknowledged.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/22/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-8, 11, 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sadra et al (US Publication No. 2005/0281098).
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Regarding claim 1, Sadra discloses a semiconductor structure Fig 10-16B comprising: a first row of transistor array Fig 10, 1068/1050; and a second row of transistor array Fig 10, 1064/1066, the second row of transistor array being adjacent to and parallel to the first row of transistor array Fig 10,wherein gates of the first row of transistor array are not aligned with gates of the second row of transistor array Fig 10.
Regarding claim 2, Sadra discloses comprising a third row of transistor array Fig 10, that is adjacent to and parallel to the first row of transistor array and shares the gates of the first row of transistor array Fig 10, wherein a first distance between the first row of transistor array and the second row of transistor array is different from a second distance between the first row of transistor array and the third row of transistor array Fig 10.
Regarding claim 3, Sadra discloses a fourth row of transistor array that is adjacent to and parallel to the second row of transistor array Fig 10 and shares the gates of the second row of transistor array Fig 10, wherein the first distance between the first row of transistor array and the second row of transistor array is different from a third distance between the second row of transistor array and the fourth row of transistor array Fig 10.
Regarding claim 5, Sadra discloses wherein the gates of the first row of transistor array partially overlap, in a horizontal direction Fig 10, with the gates of the second row of transistor array Fig 10.
Regarding claim 7, Sadra discloses wherein the first row of transistor array includes at least a first edge cell, and the second row of transistor array includes at least a second edge cell, the first edge cell and the second edge cell are aligned at a block level boundary Fig 10.
Regarding claim 8, Sadra discloses semiconductor structure comprising: a first row of transistor array Fig 10, 1068/1050 ¶0039-0040, a second row of transistor array Fig 10, 1064/1066 ¶0039-0040, a third row of transistor array Fig 10 ¶0039-0040, and a fourth row of transistor array Fig 10 ¶0039-0040 that are arranged to be parallel to each other Fig 10, the first row of transistor array and the third row of transistor array sharing a first set of gates and the second row of transistor array and the fourth row of transistor array sharing a second set of gates Fig 10, wherein gates in the first set of gates are not aligned with gates in the second set of gates Fig 10.
Regarding claim 11, Sadra discloses wherein an edge of the gates in the first row of transistor array is horizontally aligned with an edge of the gates in the second row of transistor array Fig 10.
Regarding claim 13, Sadra discloses, wherein the first row of transistor array includes a first edge cell and the second row of transistor array includes a second edge cell, the first edge cell and the second edge cell are vertically aligned at a block level boundary Fig 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sadra et al (US Publication No. 2005/0281098) over Tran et al (US Patent No. 5,780,883).
Regarding claim 4, Sandra discloses all the limitations but silent on the transistor’s polarity arrangement. Whereas Tran discloses wherein transistors in the first row of transistor array have a same polarity as transistors in the second row of transistor array, and have a different polarity from transistors in the third row of transistor array Fig 2. Sadra and Tran are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sadra because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Sadra and incorporate the teachings of Tran to provide efficient implementation (Column 2, line 1-24).
Regarding claim 10, Tran discloses wherein transistors in the first row of transistor array have an opposite polarity with transistors in the second row of transistor array and have an opposite polarity with transistors in the third row of transistor array Fig 2.
Claims 6, 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sadra et al (US Publication No. 2005/0281098) over Do et al (US Publication No. 2022/0059460).
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Regarding claims 6 and 12, Sadra discloses all the limitations but silent on the spacing. Whereas Do discloses wherein the gates of the first row of transistor array includes a first gate and a second gate that are separated by a first distance Fig 9, the gates of the second row of transistor array includes a third gate that has a second distance from the first gate of the first row of transistor array Fig 9. Sadra and Do are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sadra because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Sadra and incorporate the teachings of Do to provide efficient device orientation. Also, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the exact spacing, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ (CCPA 1980).
Regarding claim 9, Do discloses different spacing for the gates Fig 9. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the exact spacing, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ (CCPA 1980).
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811