DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12 in the reply filed on 09/08/2025 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/06/2023 and 03/18/2024 have been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 and 5-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US Pub. 2019/0027524) in view of Sakata et al. (US Pub. 2014/0103400) and Kobinata et al. (US Pub. 2019/0035832).
Regarding independent claim 1, Sato teaches an imaging device (Figs. 1-4; para. 0068+) comprising:
a first electrode (12a);
a second electrode (12c);
a photoelectric conversion layer (12b) located between the first electrode and the second electrode; and
a charge storage region (67n) electrically connected to the first electrode.
Sato is silent with respect to the specific sizing of the charge storage region; however, Sato does provide evidence that the sizing is a result effective variable; that is, Sato teaches that a smaller area of the charge storage region in plan view results in lower leakage current (para. 0128).
Sakata is also silent with respect to a specific sizing of the charge storage region; however, also provides evidence that a smaller charge accumulation region is desirable for the purpose of increased conversion gain (para. 0060).
Kobinata teaches “a not especially small” area of a charge conversion region in plan view to be on the order of 0.03 μm2 (para. 0064).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize the sizing of the charge storage region within the range below 0.03 μm2 to arrive at the claimed invention for the purpose of providing lower leakage current and increased conversion gain. Furthermore, when the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05).
Re claim 3, Sato teaches wherein the photoelectric conversion layer contains an organic material as a major ingredient (para. 0093).
Re claim 5, Sato teaches wherein the charge storage region contains an n-type impurity (para. 0088).
Re claim 6, Sato teaches wherein the charge storage region contains a substance other than boron as a major impurity (para. 0088 – that is, Sato teaches the charge storage region to be n-type and boron is a p-type dopant).
Re claim 7, Sato teaches wherein the charge storage region contains, as a major impurity, a substance whose atomic number is larger than atomic number of boron (para. 0088 – that is, Sato teaches the charge storage region to be n-type which means it would be doped by group V elements – all of which have a larger atomic number than boron).
Re claim 8, Sato teaches
a first transistor (26) (para. 0099); and
a second transistor (22) (para. 0100), wherein
the first transistor includes a first source (68an), a first drain (67n), and a first gate electrode (26e) (para. 0099),
the second transistor includes a second gate electrode (22e) (para. 0100),
the first drain is the charge storage region (67n) (para. 0099),
the second gate electrode is electrically connected to the charge storage region (para. 0107), and
an area of the second gate electrode in plan view is smaller than an area of the first gate electrode in plan view (Fig. 3).
Re claim 9, Sato teaches
a first transistor (26) (para. 0099);
a first contact plug (portion of 80a within h1) (Fig 4; para. 0106); and
a first contact hole (h1), wherein the first transistor includes a first source (68an), a first drain (67n), and a first gate electrode (26e) (para. 0099),
the first source or the first drain is the charge storage region (67n) (para. 0099),
the first contact plug electrically connects the first electrode to the charge storage region by being connected to the charge storage region via the first contact hole (Fig. 4).
Sato is silent with respect to the specific spacing between the first contact hole and the first gate electrode in plan view; however, Sato does provide evidence that this distance is a result effective variable; that is, Sato teaches that a smaller distance results in a reduced resistance value in the diffusion region 67n (i.e. the charge storage region) (para. 0119).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize the sizing of the spacing to arrive at the claimed invention for the purpose of providing a reduced resistance value. Furthermore, when the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05).
Re claim 10, a pixel (10A; para. 0086) including: the first electrode; the second electrode; the photoelectric conversion layer; and the charge storage region (Figs. 3, 4), wherein the pixel does not include a photodiode (Fig. 2-4).
Re claims 11 and 12, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize the sizing of the charge storage region within the range below 0.03 μm2 to arrive at the claimed invention for the purpose of providing lower leakage current and increased conversion gain. Furthermore, when the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US Pub. 2019/0027524) in view of Sakata et al. (US Pub. 2014/0103400) and Kobinata et al. (US Pub. 2019/0035832) and further in view of Official Notice.
Re claim 2, Sato teaches further comprising a pixel (10A; para. 0086) including: the first electrode; the second electrode; the photoelectric conversion layer; and the charge storage region (Figs. 3, 4).
Sato is silent with respect to a ratio of the area of the charge storage region in plan view to an area of the pixel in plan view is lower than or equal to 0.44%; however, each of the components of the ratio are obvious to optimize. That is, as explained above, the size of the charge storage region in plan view is a result effective variable. The Examiner is taking Official Notice that the pixel size is also a result effective variable because the pixel size has an effect on the image resolution. Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize both the area of the charge storage region in plan view and an area of the pixel in plan view such that the ratio of these two values arrived at the claimed invention. Furthermore, when the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US Pub. 2019/0027524) in view of Sakata et al. (US Pub. 2014/0103400) and Kobinata et al. (US Pub. 2019/0035832) and further in view of Ishii (US Pub. 2015/0146061).
Re claim 4, Sato, Sakata, and Kobinata are silent with respect to a thickness of the photoelectric conversion layer.
Ishii teaches an imaging device wherein a thickness of the photoelectric conversion layer is about 500nm (0.5µm) (para. 0036) – in other words within the claimed range of “less than or equal to 1 μm”.
Because Sato, Sakata, and Kobinata are silent with respect to a thickness of the photoelectric conversion layer, one of ordinary skill in the art at the time of filing would have been motivated to look elsewhere to find an appropriate thickness. Ishii teaches an appropriate thickness for a photoelectric conversion layer. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to form the thickness of the photoelectric conversion layer within the claimed range for the purpose of detecting light within the visible range (Ishii para. 0036).
Conclusion
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/MOLLY K REIDA/Examiner, Art Unit 2899