DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/22/2025 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-13 and 15-17, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yadzy (US 6201414).
PNG
media_image1.png
726
500
media_image1.png
Greyscale
PNG
media_image2.png
362
761
media_image2.png
Greyscale
PNG
media_image3.png
758
486
media_image3.png
Greyscale
PNG
media_image4.png
512
745
media_image4.png
Greyscale
PNG
media_image5.png
757
506
media_image5.png
Greyscale
PNG
media_image6.png
361
419
media_image6.png
Greyscale
With respect to claim 1, Yazdy figs. 3-7 and 9 disclose a circuit configured to facilitate measurement of a parameter (pulse width) of a device under test (DUT) (10 of Fig. 9), the circuit comprising: a first divider circuit (F1 of Fig. 4 with CD of Fig. 3 dividing the C1/CLKs by two) configured to divide a periodic input signal (t1) by a first predetermined number (each divider of Fig. 4 is divided by two ) so as to generate a first input signal (C2); a first delay circuit (DL1 of Fig. 3) configured to generate a delayed version of the first input signal; a second divider circuit (at least one of F2-F5 of Fig. 4, F2 divides C1 by 4, etc. since each divider is a divide by two) configured to divide the first input signal by a second predetermined number so as to generate a second input signal; and a second delay circuit (DL2) configured to generate different delayed versions of the second input signal (delays provided by each flip flop, e.g., FF5, FF6, etc. of Fig. 6) , whereby the parameter of the DUT ((10 of Fig. 9) having a parameter (pulse width)) is determined based on the delayed version of the first input signal (OUT1) and the different delayed versions of the second input signal (OUT2), and the DUT has a first input connected to an output of the first delay circuit (DL1 of Fig. 3) and a second input connected to an output of the second delay circuit (DL2) and is configured to receive the delayed version of the first input signal and the different delayed versions of the second input signal.
With respect to claim 2, Yadzy discloses the circuit of claim 1, wherein the first delay circuit (DL1) is further configured to receive a fixed digital control word (Reset) and to use the fixed digital control word received thereby so as to delay the first input signal a fixed amount of time (initial delay).
With respect to claim 3, Yadzy discloses the the circuit of claim 1, wherein the second delay line circuit (DL2 same configuration as shown in DL1 fig. 6) is further configured to receive a variable digital control word (Bits B1-B5) and to use the variable digital control word received thereby so as to delay the second input signal ( Bits B1-B5; For example, if the six bits B.sub.6, B.sub.5, B.sub.4, B.sub.3, B.sub.2, and B.sub.1 represent 100011, it means 32+2+1=35 delay is needed) different amounts of time.
With respect to claim 5, Yadzy discloses the circuit of claim 1, further comprising a first circuit (circuit generating B1-B6) configured to generate first, second, and third digital control words (V.sub.1, Vsub2-…V.sub32 ) and to use the first, second, and third digital control words generated thereby so as to delay the periodic input signal first, second, and third amounts of time, respectively, wherein the first circuit is further configured to generate a step size based on the first, second, and third digital control words (Bits B1-B5; For example, if the six bits B.sub.6, B.sub.5, B.sub.4, B.sub.3, B.sub.2, and B.sub.1 represent 100011, it means 32+2+1=35 delay is needed), whereby the parameter of the DUT is determined based further on the step size.
With respect to claim 6, Yadzy discloses the circuit of claim 5, wherein the first circuit (not shown but producing B1-B5) is further configured to determine a frequency of the periodic input signal (t1) and the first circuit generates the step size based further on the frequency of the periodic input signal determined thereby (see fig. 9).
With respect to claim 7, Yadzy discloses a circuit configured to facilitate measurement of a parameter (pulse width) a device under test (DUT) (10 of Fig. 9), the circuit comprising: a divider circuit (F1 of Fig. 4 with CD of Fig. 3 dividing the C1/CLKs by two) configured to divide a periodic input signal (t1) by a predetermined number (2) so as to generate an input signal (C2); a first delay circuit (DL1 of Fig. 2); configured to generate a delayed version of the input signal; and a second delay circuit (DL2) configured to generate different delayed versions of the input signal, wherein the delayed version of the input signal and the different delayed versions of the input signal are associated with the parameter (pulse width) of the DUT, wherein the parameter of the DUT is associated with a period of time during which a logic-level of an output of the DUT remains substantially constant between high and low .
With respect to claim 8, Yadzy discloses the circuit of claim 7, further comprising a pulse width modulator (PWM) (element 10) configured to generate a plurality of PWM signals, each of which has a distinct duty cycle, based on the delayed version of the input signal (OUT1) and the different delayed versions of the input signal (OUT2), wherein each PWM signal is associated with the parameter of the DUT.
With respect to claim 9, Yadzy discloses the circuit of claim 8, wherein the PWM includes one or more logic gates (and gate, inverter etc. ), one or more latch circuit (flip flops), or a combination thereof.
With respect to claim 10, the circuit above discloses the circuit of claim 7, wherein the first delay circuit (DL1) is further configured to receive a fixed digital control word ((reset) and to use the fixed digital control word received thereby so as to delay the input signal a fixed amount of time.
With respect to claim 11, the circuit above produces the discloses the circuit of claim 7, wherein the second delay line circuit (DL2) is further configured to receive a variable digital control word (B6-B1) and to use the variable digital control word received thereby so as to delay the input signal different amounts of time.
With respect to claim 12, the circuit above discloses the circuit of claim 7, further comprising a first circuit (circuit generating B1-B6) configured to generate first, second, and third digital control words (V.sub.1, Vsub2-…V.sub32 ) and to use the first, second, and third digital control words generated thereby so as to delay the periodic input signal first, second, and third amounts of time, respectively, wherein the first circuit is further configured to generate a step size based on the first, second, and third digital control words (Bits B1-B5; For example, if the six bits B.sub.6, B.sub.5, B.sub.4, B.sub.3, B.sub.2, and B.sub.1 represent 100011, it means 32+2+1=35 delay is needed), respectively, and to generate a step size based on the first, second, and third digital control words, wherein the step size is associated with the parameter (pulse width) of the DUT.
With respect to claim 13, the circuit above discloses the circuit of claim 12, wherein the first circuit is further configured to determine a frequency of the periodic input signal (t1) and the first circuit generates the step size based further on the frequency of the periodic input signal determined thereby.
With respect to claim 14, the circuit above produces the discloses the method for facilitating measurement of a parameter of a device under test (DUT), the method comprising: receiving a periodic input signal (t1); dividing the periodic input signal by a first predetermined number (2) to generate a first input signal (out1); dividing the first input signal by a second predetermined number (4) to generate a second input signal (out2); and delaying the second input signal (via DL2) to generate different delayed versions of the second input signal (out2), wherein the different delayed versions of the second input signal are associated with the parameter of the DUT (pulse width) , wherein the parameter of the DUT is associated with a period of time during which a logic-level of an output of the DUT remains substantially constant between high and low .
With respect to claim 15, the circuit above produces method of claim 14, further comprising delaying the first input signal to generate a delayed version of the first input signal (Out1), wherein the delayed version of the first input signal is associated with the parameter of the DUT (pulse width).
With respect to claim 16, the circuit above produces the method of claim 15, further comprising: receiving a fixed digital control word (reset); and using the fixed digital control word to delay the first input signal (c2) a fixed amount of time.
With respect to claim 17, the circuit above produces the method of claim 14, further comprising: receiving a variable digital control word (bits 1-5); and using the variable digital control word to delay the second input signal different amounts of time.
With respect to claim 19, the circuitabove produces the method of claim 14, further comprising: generating first, second, and third digital control words (V.sub.1, Vsub2-…V.sub32 ); using the first, second, and third digital control words to delay the periodic input signal first, second, and third amounts of time, respectively; and generating a step size based on the first, second, and third digital control words, wherein the step size is associated with the parameter (pulse width) of the DUT.
With respect to claim 20, the circuit above produces method of claim 19, further comprising: determining a frequency of the periodic input signal (t1); and generating the step size based further on the frequency of the periodic input signal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yadzy.
With respect to claim 4, Yadzy the circuit of claim 1, but fails to disclose wherein the first predetermined number (each divider of Fig. 4 is divided by two) is larger than the second predetermined number (at least one of F2-F5 of Fig. 4, F2 divides C1 by 4, etc. since each divider is a divide by two). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to select the first division to be larger than the second division as the selection of the size of to be larger than would be within the scope of one skilled in the art to try as to adjust the circuit to achieve a different result.
With respect to claim 18, the circuit above produces the method of claim 14, but fails to disclose wherein the first predetermined number r (each divider of Fig. 4 is divided by two) is larger than the second predetermined number (at least one of F2-F5 of Fig. 4, F2 divides C1 by 4, etc. since each divider is a divide by two). ). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to select the first division to be larger than the second division as the selection of the size of to be larger than would be within the scope of one skilled in the art to try as to adjust the circuit to achieve a different result.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached on M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849