Prosecution Insights
Last updated: August 08, 2026
Application No. 18/150,976

LIGHT EMITTING DIODES AND METHOD OF MAKING THEREOF BY SELECTIVELY GROWING ACTIVE LAYERS FROM TRENCH SEPARATED AREAS

Final Rejection §102§103§112
Filed
Jan 06, 2023
Priority
Jan 13, 2022 — provisional 63/299,245
Examiner
CHEN, YU
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shoei Chemical Inc.
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
729 granted / 1073 resolved
At TC average
Strong +30% interview lift
Without
With
+29.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
85 currently pending
Career history
1180
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
45.8%
+5.8% vs TC avg
§102
23.7%
-16.3% vs TC avg
§112
22.8%
-17.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1073 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This office action is in response to amendment filed 5/29/2026. Claims 1 and 4-20 are pending. Claims 2-3 have been canceled. Claims 10-20 have been withdrawn. Claims 1, 4, and 6 have been amended. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1 and 4-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 reciting “a third portion of the semiconductor regrowth layer” and “a third portion of the second-conductivity-type compound semiconductor layer” render the claim indefinite. Recitation to “a third portion” without prior recitation to any “first portion” or “second portion” renders the claim indefinite. It is unclear if recitation to “a third portion” implies the presence of “a first portion” and “a second portion”. Claim 8 reciting “a first portion of the semiconductor active layer” and “a second portion of the semiconductor active layer” render the claim indefinite for unclear antecedent basis. Claim 1 previously recite “a first portion and a second portion of the semiconductor active layer”. Thus, it is unclear if “a first portion of the semiconductor active layer” and “a second portion of the semiconductor active layer” in claim 8 are referring to the same “first portion” and “second portion” previously recited in claim 1 or are intended to refer to different portions of the semiconductor active layer. Other claims are rejected for depending on a rejected claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 4 and 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yan et al. US 2012/0025230 A1 (Yan). PNG media_image1.png 572 834 media_image1.png Greyscale In re claim 1, as best understood, Yan discloses (e.g. FIGs. 1-3) a method of forming light emitting diodes, comprising: forming a first-conductivity-type compound semiconductor layer 251,252 over a substrate 10 (¶ 73); etching the first-conductivity-type compound semiconductor layer 251,252 (¶ 78) to form a first pillar structure 25 (of a LED structure 2) and a second pillar structure 25 (of another LED structure 2) without exposing the substrate 10 between the first and the second pillar structures (substrate 10 covered by layer 20); selectively growing a semiconductor regrowth layer 301+302 on the first pillar structure and the second pillar structure 25 (of LED structures 2), selectively growing a semiconductor active layer 401+402 on the semiconductor regrowth layer 301+302 (¶ 78); and selectively growing a second-conductivity-type compound semiconductor layer 501+502 (¶ 78) on the semiconductor active layer 401+402, wherein “a third portion of the semiconductor regrowth layer” 301, “a third portion of the semiconductor active layer” 401 and a third portion of the second-conductivity-type compound semiconductor layer 501 are also formed in a trench located between the first pillar structure and the second pillar structure (301,401,501 between adjacent LED structures 2, see FIG. 2); and a top surface of the third portion second-conductivity-type compound semiconductor layer” 501 (of LED structures 1) is located below a first portion and a second portion of the semiconductor active layer 402 located over the first and the second pillar structures 25 (of LED structures 2), respectively. In re claim 4, Yan discloses (e.g. FIGs. 1-3) wherein the first-conductivity-type compound semiconductor layer 251,252 and the second-conductivity-type compound semiconductor layer 501+502 each comprise a Group III-nitride material (¶ 72). In re claim 6, Yan discloses (e.g. FIGs. 1-3) further comprising forming a compound semiconductor buffer layer 20 over the substrate 10 prior to forming the first-conductivity-type compound semiconductor layer 251,252 (¶ 78). In re claim 7, Yan discloses (e.g. FIGs. 1-3) wherein: the substrate 10 comprises sapphire (¶ 72); and the etching the first-conductivity-type compound semiconductor layer 251,252 comprises etching the first-conductivity-type compound semiconductor layer to expose the compound semiconductor buffer layer 20 in the trench between the first pillar structure and the second pillar structure (between LED structures 2) without exposing the sapphire substrate 10 in the trench between the first and the second pillar structures (¶ 78). In re claim 8, as best understood, Yan discloses (e.g. FIGs. 1-3) wherein: the first pillar structure 25 (of a LED structure 2), a first portion of the semiconductor regrowth layer 302 located on the first pillar structure 25 (of a LED structure 2), “a first portion of the semiconductor active layer” 402 located on the first portion of the semiconductor regrowth layer 302, and a first portion of the second-conductivity-type compound semiconductor layer 502 located on the first portion of the semiconductor active layer 402 comprise a first light emitting diode 2; and the second pillar structure 25 (of another LED structure 2), a second portion of the semiconductor regrowth layer 302 located on the second pillar structure 25 (of another LED structure 2), “a second portion of the semiconductor active layer” 402 (of another LED structure 2) located on the second portion of the semiconductor regrowth layer 302, and a second portion of the second-conductivity-type compound semiconductor layer 502 (of another LED structure 2) located on the second portion of the semiconductor active layer 402 comprise a second light emitting diode (another LED structure 2). In re claim 9, Yan discloses (e.g. FIGs. 1-2) further comprising forming first electrodes 713 over the first and the second portions second-conductivity-type compound semiconductor layer 502 in the first and the second light emitting diodes (plural LED structures 2, four shown in FIG. 2, ¶ 83,92). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yan as applied to claim 4 above, and further in view of Pinos et al. US 2023/0238421 (Pinos). In re claim 5, Yan discloses the claimed invention including (e.g. FIGs. 1-3) wherein: the first-conductivity-type compound semiconductor layer 251,252 comprises a n-type GaN (¶ 72-73) and the second-conductivity-type compound semiconductor layer 501+502 comprises a p-type GaN (¶ 72-73); the semiconductor active layer 401+402 comprises III-nitride (¶ 72-73); and the semiconductor regrowth layer 301+302 comprises a n-type GaN layer (¶ 72-73). Yan does not explicitly discloses the first-conductivity-type compound semiconductor layer 251,252 and the second-conductivity-type compound semiconductor layer 501+502 are single crystal, the semiconductor active layer 401+402 comprises at least one InGaN quantum well, each of the first pillar structure 25 and the second pillar structure 25 have a top surface that is a c-plane surface of the n-type GaN, and the semiconductor regrowth layer 310+302 is lattice matched to a crystal structure of the first pillar structure 25 and the second pillar structure 25 and has a top c-plane surface. However, Pinos discloses (e.g. FIGs. 6 & 8-9, ¶ 150-151) a method of forming LEDs having single crystal epitaxial layers, including an active layer 22 comprising at least one InGaN quantum well (¶ 118), pillar structures 14 (see FIG. 6) on which the LED layers 16,22,24 (FIG. 9) are formed have a top surface that is a c-plane surface (¶ 69, (0001) crystal plane is the c-plane of III-nitride crystal), and the semiconductor regrowth layer 16 is lattice matched to a crystal structure of pillar structures 14 and has a top c-plane surface (¶ 75). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Yan’s LED layers as single crystals lattice matched to the c-plane as taught by Pinos to reduce strain and defects, thereby improving light emitting efficiency (¶ 10,16,90 of Pinos), and form the active layer to include at least one InGaN quantum well for increasing internal quantum efficiency through quantum confinement and to obtained desired emission wavelength (¶ 118 of Pinos). Response to Arguments Applicant's arguments filed 5/29/2026 have been fully considered but they are not persuasive. Regarding Yan, Applicant appears to be arguing the processing is different in Yan due to the etching stop performed after growing the layers 301+302, 401+402, 501+502 which somehow fails to teach the claim method (Remark, page 11). This is not persuasive. Claim 1 does not preclude additional etching step from being performed subsequent to the growth of the semiconductor regrowth layer, the semiconductor active layer, and the second-conductivity-type compound semiconductor layer. Yan initially teaches forming mesa structures 25 (plural mesas associated with comb tooth pattern shown in FIG. 2) “by epitaxial growth, patterning and etching” (¶ 78). Subsequent to the steps of “epitaxial growth, patterning and etching” that forms the mesa structures 25, Yan teaches forming a semiconductor regrowth layer including a portion 302 on the mesa 25 and a portion 301 (corresponding to claimed third portion) on the template layer 20 exposed in the trench between adjacent mesas 25. Next, a semiconductor active layer is formed including a first portion 402 and a second portion 402 above 302 on respective mesas 25 and a third portion 401 above 301 in the trench between adjacent mesas 25. Finally, a second-conductivity-type compound semiconductor layer is formed including a portion 502 above 402 on respective mesas, and a third portion 501 above 401 in the trench between adjacent mesas 25. In the resulting structure, a top surface of the third portion 501 of the second-conductivity-type compound layer is located below a first portion 402 and a second portion 402 of the semiconductor active layer over the mesas 25. As such Yan teaches all of the claimed features. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896
Read full office action

Prosecution Timeline

Jan 06, 2023
Application Filed
Mar 02, 2026
Non-Final Rejection mailed — §102, §103, §112
May 29, 2026
Response Filed
Jul 29, 2026
Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
98%
With Interview (+29.7%)
2y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1073 resolved cases by this examiner. Grant probability derived from career allowance rate.

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