DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-17 and 26-28 are rejected under 35 U.S.C. 1103 as being unpatentable over YOO et al. (US PGpub: 2019/0393355 A1), hereinafter YOO, in view of CALLEGARI et al. (US PGPub: 2014/0138781 A1), hereinafter CALLEGARI.
Regarding claim 1, YOO teaches a semiconductor device (Paragraphs [0021] - [0036]; figure 1) comprising:
a substrate (101);
a gate electrode film (140) including a metal element (paragraph [0047]) on the substrate;
a gate insulating film including a ferroelectric material (120) between the substrate and the gate electrode film; and
a buffer oxide film (130) including an oxide of a semiconductor material (silicon oxide; Paragraph [0031]) between the gate insulating film and the gate electrode film, the buffer oxide film being in contact with the gate insulating film ((see Fig. 1).
YOO does not explicitly teach a buffer film including Si, between the buffer oxide film and the gate electrode film.
However it is taught in CALLEGARI that buffer film (110, FIG. 1. See annotated modified FIG. 3 ) including Si (material can be silicon, see paragraph [0031]. The layer 110 may also include a conductive, heavily doped semiconductor with high oxygen affinity, e.g., Si, SiGe, etc.), between the buffer oxide film (buffer oxide layer 112) and the gate electrode film(114, FIG. 3) (On the other hand, if layers 110 and 112 are not removed, the conductive layer 114 may be optionally deposited on the top of layer 110 as stated in Paragraph [0036]).
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Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use YOO’s semiconductor device with other teaching from CALLEGARI so that While the present principles are illustratively described in terms of a single scavenger layer, it should be understood that the process may be repeated one or more times to further reduce oxide levels in the capacitor dielectric materials. As the result of the use of a single scavenger layer, the capacitance effective thickness (CET) is reduced by 5 Angstroms or more. The stack has an oxygen scavenged passivation layer formed on the substrate and an oxygen scavenged high dielectric constant material formed over the passivation layer wherein the passivation layer and the high dielectric constant layer include reduced oxygen content sufficient to permit an improvement of at least 5 Angstroms for CET and EOT.
Regarding claim 2, YOO teaches the semiconductor device of claim 1, wherein the gate insulating film includes hafnium-based oxide having ferroelectricity (Paragraphs [0027] and [0031]).
Regarding claim 3, YOO teaches the semiconductor device of claim 1, wherein the gate electrode film includes: tungsten; titanium nitride; or tungsten and titanium nitride (Paragraph [0047]).
Regarding claim 4, YOO teaches the semiconductor device of claim 1, wherein the substrate includes silicon (Si), and the buffer oxide film includes an Si oxide film (Paragraph [0023] for the Si substrate and Paragraph [0025], [0031] for the silicon oxide buffer).
Regarding claim 6, YOO teaches the semiconductor device of claim 1, further comprising: an interface film between the substrate and the gate insulating film, wherein the interface film includes an oxide of a semiconductor material included in the substrate (Interface film 110 between the substrate 101 and the gate insulating film 120, wherein the interface film includes an oxide of a semiconductor material included in the substrate in paragraph [0025]).
Regarding claim 7, YOO teaches the semiconductor device of claim 6, wherein the substrate includes silicon (Si), and the interface film includes an Si oxide film (Paragraph [0023] for the Si substrate and Paragraph [0025], [0031] for the silicon oxide buffer).
Regarding claim 8, YOO teaches the semiconductor device of claim 1, wherein a thickness of the buffer oxide film is 5 angstroms (A) to 15 A (Paragraph [0031]).
Regarding claim 9, YOO teaches a semiconductor device comprising:
a substrate including a first semiconductor material ((Si) (101);
a gate electrode film including a metal element (140) including a metal element (paragraph [0047]), on the substrate (101);
a gate insulating film including a ferroelectric material (120) between the substrate and the gate electrode film;
an interface film (110) including an oxide of the first semiconductor material (silicon oxide; Paragraph [0025]), between the gate insulating film (120) and the substrate (101); and
a buffer oxide film (130) including an oxide of a semiconductor material (silicon oxide; Paragraph [0031]) between the gate insulating film and the gate electrode film, wherein a thickness of the interface film is smaller than a thickness of the buffer oxide film (silicon oxide; Paragraph [0025]), between the gate insulating film and the substrate has a thickness smaller (1 nm; paragraph [0025]) than a thickness of the buffer oxide film (2 nm to 10 nm; Paragraph [0031 ]).
YOO does not explicitly teach a buffer film including the second semiconductor material, between the buffer oxide film and the gate electrode film.
However it is taught in CALLEGARI that buffer film (110, FIG. 1. See annotated modified FIG. 3 ) including Si (material can be silicon, SiGe see paragraph [0031]. The layer 110 may also include a conductive, heavily doped semiconductor with high oxygen affinity, e.g., Si, SiGe, etc.), between the buffer oxide film (buffer oxide layer 112) and the gate electrode film(114, FIG. 3) (On the other hand, if layers 110 and 112 are not removed, the conductive layer 114 may be optionally deposited on the top of layer 110 as stated in Paragraph [0036]).
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Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use YOO’s semiconductor device with other teaching from CALLEGARI so that While the present principles are illustratively described in terms of a single scavenger layer, it should be understood that the process may be repeated one or more times to further reduce oxide levels in the capacitor dielectric materials. As the result of the use of a single scavenger layer, the capacitance effective thickness (CET) is reduced by 5 Angstroms or more. The stack has an oxygen scavenged passivation layer formed on the substrate and an oxygen scavenged high dielectric constant material formed over the passivation layer wherein the passivation layer and the high dielectric constant layer include reduced oxygen content sufficient to permit an improvement of at least 5 Angstroms for CET and EOT.
Regarding claim 10, YOO teaches the semiconductor device of claim 9, wherein the gate insulating film includes hafnium-based oxide having ferroelectricity (Paragraphs [0025] -[0031]).
Regarding claim 11, YOO teaches the semiconductor device of claim 9, wherein the first semiconductor material and the second semiconductor material are the same material as each other (Paragraphs [0025] -[0031]).
Regarding claim 12, YOO teaches the semiconductor device of claim 11, wherein the first semiconductor material and the second semiconductor material each include silicon (Si ) (Paragraphs [0025] -[0031]).
Regarding claim 13, YOO teaches the semiconductor device of claim 9, wherein the buffer oxide film is in contact with the gate insulating film (Fig. 1, gate electrode film 140 and buffer oxide film 130).
Regarding claim 14, YOO teaches the semiconductor device of claim 9, wherein the thickness of the buffer oxide film is 5 angstroms (A) to 15 (Paragraph [0031], also known to people skilled in the art) .
Regarding claim 15, YOO does not explicitly teach the semiconductor device of claim 9, wherein the thickness of the interface film is 5 angstroms (A) or less (an interface film (110) including an oxide of the first semiconductor material (silicon oxide; Paragraph [0025]), between the gate insulating film and the substrate has a thickness smaller (1 nm; paragraph [0025]) than a thickness of the buffer oxide film (2 nm to 10 nm; Paragraph [0031 ]).
Regarding claim 16, YOO does not explicitly teach the semiconductor device of claim 15, wherein the thickness of the interface film is 1 A or less (an interface film (110) including an oxide of the first semiconductor material (silicon oxide; Paragraph [0025]), between the gate insulating film and the substrate has a thickness smaller (1 nm; paragraph [0025]) than a thickness of the buffer oxide film (2 nm to 10 nm; Paragraph [0031 ]).
Regarding claim 17, YOO teaches the semiconductor device of claim 9, wherein the gate electrode film (140, Paragraph [0047]) is in contact with the buffer oxide film buffer oxide film 130, FIG. 1).
Regarding claim 26, YOO teaches a semiconductor device comprising:
a substrate including silicon (Si) (101);
a gate electrode film (140) including a metal element (paragraph [0047]), on the substrate (FIG. 1);
a gate insulating film including a ferroelectric material (120) between the substrate and the gate electrode film;
a buffer oxide film (130) including an Si oxide film (silicon oxide; Paragraph [0031]).
YOO does not explicitly teach a buffer film including the second semiconductor material, between the gate insulating film and the gate electrode film and a buffer oxide film including an Si oxide film, between the gate insulating film and the buffer film.
However it is taught in CALLEGARI that buffer film (110, FIG. 1. See annotated modified FIG. 3 ) including Si (material can be silicon, SiGe see paragraph [0031]. The layer 110 may also include a conductive, heavily doped semiconductor with high oxygen affinity, e.g., Si, SiGe, etc.), between the gate insulating film (108) and the gate electrode film(114, FIG. 3) (On the other hand, if layers 110 and 112 are not removed, the conductive layer 114 may be optionally deposited on the top of layer 110 as stated in Paragraph [0036]). a buffer oxide film (112) between the gate insulating film (108) and the buffer film (110).
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Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use YOO’s semiconductor device with other teaching from CALLEGARI so that While the present principles are illustratively described in terms of a single scavenger layer, it should be understood that the process may be repeated one or more times to further reduce oxide levels in the capacitor dielectric materials. As the result of the use of a single scavenger layer, the capacitance effective thickness (CET) is reduced by 5 Angstroms or more. The stack has an oxygen scavenged passivation layer formed on the substrate and an oxygen scavenged high dielectric constant material formed over the passivation layer wherein the passivation layer and the high dielectric constant layer include reduced oxygen content sufficient to permit an improvement of at least 5 Angstroms for CET and EOT.
Regarding claim 27, YOO does not explicitly teach the semiconductor device of claim 26, further comprising: an interface film including a silicon oxide film, between the substrate and the gate insulating film (an interface film (110) including an oxide of the first semiconductor material (silicon oxide; Paragraph [0025]), between the gate insulating film and the substrate has a thickness smaller (1 nm; paragraph [0025]) than a thickness of the buffer oxide film (2 nm to 10 nm; Paragraph [0031 ]).
Regarding claim 28, YOO teaches the semiconductor device of claim 27, wherein a thickness of the interface film is smaller than a thickness of the buffer oxide film (an interface film (110) including an oxide of the first semiconductor material (silicon oxide; Paragraph [0025]), between the gate insulating film and the substrate has a thickness smaller (1 nm; paragraph [0025]) than a thickness of the buffer oxide film (2 nm to 10 nm; Paragraph [0031 ]).
Conclusion
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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