DETAILED ACTION
This Office action responds to the Amendment file on August 8, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgment
The Amendment filed on August 8, 2025, responding to the Office action mailed on May 22, 2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claim 14. Accordingly, pending in the application are claims 1-13, 15, and 16.
Response to Amendment
Applicant’s arguments with respect to the claims filed on August 8, 2025 have been considered, but are moot in view of the new grounds of rejections. Jeon clearly shows an inverted wine cup where the width of the lower portion of the contact window being larger than the width of the upper portion of the contact window and the criticality of the specific ratio of these two widths has not established, see pages 12-13 of this Office action below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the dimension" of a contact surface and “the dimension” of the second hole segment in lines 9 and 10. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 1, 2, 4, and 5 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Jeon et al. (Jeon hereinafter) (US 2003/0132526).
Regarding Claims 1, 2, 4, and 5:
Jeon (see Figs. 9-12 and 15-17) teaches a method for fabricating a contact structure, comprising: forming an insulating dielectric layer (305 and 309) on a substrate 301; forming a contact hole (319 or 419) penetrating through the insulating dielectric layer, the contact hole comprising a first hole segment and a second hole segment communicating with each other, the first hole segment penetrating to the substrate, the second hole segment being positioned on a side of the first hole segment away from the substrate, the first hole segment having a first orthogonal projection on the substrate, the second hole segment having a second orthogonal projection on the substrate, the second orthographic projection being positioned in the first orthographic projection, the dimension 321’ of a contact surface between the first hole segment and the substrate is greater than the dimension of the second hole segment; and forming a conductive plug in the contact hole.
Jeon (see ¶ [0052], [0054], [0056]-[0059]) teaches “a lower dielectric layer 305 is formed on a semiconductor substrate 301”, “an upper dielectric layer 309 is formed”, “the upper dielectric layer 309 and the lower dielectric layer 305 are etched by a dry etching technique … to form a trench 391 having a width 321”, “the upper dielectric layer 209 is etched to a lesser extend in a lateral direction while, the lower dielectric layer 305 is etched to a greater extend in the lateral direction resulting in a sidewall profile having a negative slope … the final contact windows 319’ has a width 321’ in a lower region greater than a width in an upper region”, “the photoresist 311 is removed and a wiring material is formed on the upper electric layer 309 and inside the contact window 319’”, “the etch rate of the lower dielectric layer 305 gradually decreases in the direction from bottom to top, and the etch rate in the upper region of the lower dielectric layer 305 is relatively low … the etch rate in the bottommost region of the lower dielectric layer can be set relatively high”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon hereinafter) (US 2003/0132526) as applied to claim 1 above, and further in view of Watanabe (US 5,002,902).
Regarding Claims 3 and 6:
Jeon (see ¶ [0008]-[0011] and Figs. 1-4) teaches a contact window 19 is formed by etching an upper dielectric layer 9 and a lower dielectric layer 5 and severely damaged the impurity active region 3 and partially reached to a semiconductor substrate 1, which may increase contact resistance and junction leakage current and etching should be controlled with high accuracy to prevent damage.
Watanabe (see col.3/l.64 - col.4/l.42 and FIGs. 4A-4C) teaches a contact hole 24 is formed by etching a photoresist 27 and a silicon oxide layer 23 and can extends into the device region 21c by about 1000 Å in the substrate 21 having a thickness of about 5000 Å.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Jeon to further include the teaching of Watanabe to increase the depth of the impurity active regions in order to avoid over-etching during the formation of contact windows in order to prevent the increase of contact resistance and junction leakage current.
Claims 7, 8, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon hereinafter) (US 2003/0132526) as applied to claims 1 and 13 above, and in view of Yeh et al. (Yeh hereinafter) (US 4,375,643) and further in view of Chun (US 6,566,241).
Regarding Claims 7 and 8:
Jeon (see ¶ [0008]-[0011] and Figs. 1-4) teaches wiring material 24 being formed to fill the contact windows 19, but does not explicitly teach the forming the conductive plug comprises: forming a metallic compound layer on a bottom surface of the contact hole; covering a barrier layer on a hole wall of the contact hole and on a surface of the metallic compound layer; and forming a metal filling portion on a surface of the barrier layer, the metal filling portion being configured to fill up the contact hole; and the forming the metallic compound layer comprises: covering a metal layer on the hole wall and the bottom surface of the contact hole; and annealing the substrate covered with the metal layer, such that the metal layer reacts with the substrate to form the metallic compound layer.
Regarding Claims 15 and 16:
Jeon (see ¶ [0008]-[0011] and Figs. 1-4) teaches wiring material 24 being formed to fill the contact windows 19, but does not explicitly teach the conductive plug further comprises: a metallic compound layer arranged between the substrate and the first conductive segment and a barrier layer at least covering a periphery of the conductive plug.
Yeh teaches a Schottky Metal semiconductor FET (see col.3/ll.15-22 and col.6/l.65 – col.7/l.50 and Figs. 4i-4l) comprising a layer 115 of Pt or Pd being deposited on the substrate 10 where silicide alloy/compound layers 120-1 and 120-2 of PtSi or PdSi being formed after thermal annealing with enough temperature, a TiW layer 125, and an Al layer 130 and “any platinum not formed into a platinum-substrate compound … may be etched”. However, Yeh does not explicitly teach the barrier layer.
Chun (see col.4/ll.29-52 and FIG. 2) teaches contact hole filled with multi-layered metals comprising a metal barrier layer 150 formed of Ti/TiN and a conductive plug 160 formed of W in each of the contact holes 140.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Jeon to include the teaching of Yeh to form a high-speed Schottky ohmic contact in a small-structure geometries to lower the resistance and to further include the teaching of Chun to add a barrier layer surrounding the trench walls to prevent excessive interdiffusion between the filling metal and the semiconductor and a trench or via filled the trenches with conductive material to the top in order to complete the overall multilayered contact structure.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon hereinafter) (US 2003/0132526) in view of Yeh et al. (Yeh hereinafter) (US 4,375,643) and further in view of Chun (US 6,566,241) as applied to claim 7 above, and further in view of Kwon (US 2003/0025163).
Regarding Claim 9:
Jeon in the method of Yeh in view of Chun teaches the instant invention except for forming a semiconductor epitaxial layer on the bottom surface of the contact hole; forming, in the contact hole, a metal layer at least covering the semiconductor epitaxial layer; and annealing the semiconductor epitaxial layer covered with the metal layer, such that the metal layer reacts with the semiconductor epitaxial layer to form the metallic compound layer.
Kwon (see ¶ [0038], [0041], [0042] and Figs. 9-11) teaches a metal layer 228 made of Ni, Co, or Ti and formed on a silicon epitaxial layer 224 grown on the active regions and having a thickness of 300Å, “the metal layer 228 is made of a material that reacts on silicon in the silicon epitaxial layer 2242 to form silicide”, “a first annealing is formed … where the metal layer 228 is formed, diffusing metal atoms constituting the metal layer into the silicon epitaxial layer 224 … remaining metal layer 228, which is not diffused … is then removed … a second annealing process … completely siliciding the epitaxial layer 224”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of Jeon in the method of Yeh in view of Chun to include the teaching of Kwon to form a Schottky ohmic contact by forming a semiconductor epitaxial layer first, forming a metal layer second, and then annealing them to induce the formation of metallic compound through their interaction in order to lower contact resistance and higher interconnect speed.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon hereinafter) (US 2003/0132526) in view of Yeh et al. (Yeh hereinafter) (US 4,375,643) and further in view of Chun (US 6,566,241) and Kwon (US 2003/0025163) as applied to claim 9 above, and in view of Costa et al. (Costa hereinafter) (US 2019/0304977) and Pal et al. (Pal hereinafter) (US 7,932,143) and further in view of Lee et al. (Lee hereinafter) (US 2014/0206188).
Regarding Claim 10:
Jeon in the method of Yeh in view of Chun and Kwon teaches the instant invention except for a thickness of the semiconductor epitaxial layer is 10-20 nm, and a thickness of the metal layer being 5-30 nm.
Costa (see ¶ [0048]) teaches an interfacial layer formed over a silicon epitaxial layer having a thickness between 10 nm - 300 nm.
Pal (see col.5/ll.36-57) teaches the SiGe epitaxial layer having a thickness between 4 nm -15 nm and preferably about 10 nm and a silicon epitaxial layer having a thickness between 4 nm - 15 nm.
Lee (see Abstract) teaches a second metal layer having a thickness less than 10 nm and formed on a first metal layer having a thickness less than 10 nm and both metal layers react with the silicon substrate to form a metal silicide layer.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of Jeon in the method of Yeh in view of Chun and Kwon to include the teachings of Costa, Pal, and Lee to form desired thickness of both the semiconductor epitaxial layer and the metal layer so that proper thickness of the metal silicide can be generated in order to form ohmic contacts with less resistance and higher interconnect speed.
The differences in thickness values will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thickness values are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the thickness of the semiconductor epitaxial layer and the metal layer, it would have been obvious to one of ordinary skill in the art to use these range of thickness to form metal silicide layer after annealing.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934, 1936s (Fed. Cir. 1990).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon hereinafter) (US 2003/0132526) in view of Yeh et al. (Yeh hereinafter) (US 4,375,643) and further in view of Chun (US 6,566,241) as applied to claim 7 above, and further in view of Zhu et al. (US 6,402,592).
Regarding Claim 11:
Jeon in the method of Yeh in view of Chun teaches the instant invention except for covering a metal material on the surface of the barrier layer to form a seed layer; and filling the metal material in the contact hole by means of an electroplating process to form the conductive plug.
Zhu (see col.2/ll.3-23, and col.6/l.38) teaches Al interconnect being replaced by Cu for lower resistance and higher interconnect speed and 1500 Å copper seed layer formed on a TaN barrier layer before Cu being electroplated to fill the via holes and conductor trenches.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Jeon in the method of Yeh in view of Chun to include the teaching of Zhu to fill the contact windows with Cu by well-known electroplating process instead of Al for lower resistance and higher interconnect speed and better surface conditions and to form a Cu seed layer between the barrier layer and Cu filler to prevent voids in the contact windows for better performance and reliability.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon hereinafter) (US 2003/0132526) in view of Yeh et al. (Yeh hereinafter) (US 4,375,643) and Chun (US 6,566,241) and further in view of Zhu et al. (US 6,402,592) as applied to claim 11 above, and further in view of Reid et al. (US 8,168,540).
Regarding Claim 12:
Jeon in the method of Yeh in view of Chun and Zhu teaches the instant invention except for a thickness of the seed layer is 2-20 nm.
Red (see col.2/ll.54-59) teaches the Cu seed layer is generally between 1 nm - 20 nm thick.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of Jeon in the method of Yeh in view of Chun and Zhu to include the teaching of Red to form thinner Cu seed layer for void-free interconnections as the semiconductor technology develops into nano-scales of the smaller chips.
The differences in thickness values will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thickness values are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph on page 9) of the thickness of the seed layer, it would have been obvious to one of ordinary skill in the art to use these range of thickness to form a seed layer to prevent void formation in the trenches or via for the interconnect structure in the nano-scaled small chips.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon hereinafter) (US 2003/0132526).
Regarding Claim 13:
Jeon (see Figs. 9-12 and 15-17) teaches a method for fabricating a contact structure, comprising: forming an insulating dielectric layer (305 and 309) on a substrate 301; forming a contact hole (319 or 419) penetrating through the insulating dielectric layer, the contact hole comprising a first hole segment and a second hole segment communicating with each other, the first hole segment penetrating to the substrate, the second hole segment being positioned on a side of the first hole segment away from the substrate, the first hole segment having a first orthogonal projection on the substrate, the second hole segment having a second orthogonal projection on the substrate, the second orthographic projection being positioned in the first orthographic projection, the dimension 321’ of a contact surface between the first hole segment and the substrate is greater than the dimension of the second hole segment; and forming a conductive plug in the contact hole.
Jeon (see ¶ [0052], [0054], [0056]-[0059]) teaches “a lower dielectric layer 305 is formed on a semiconductor substrate 301”, “an upper dielectric layer 309 is formed”, “the upper dielectric layer 309 and the lower dielectric layer 305 are etched by a dry etching technique … to form a trench 391 having a width 321”, “the upper dielectric layer 209 is etched to a lesser extend in a lateral direction while, the lower dielectric layer 305 is etched to a greater extend in the lateral direction resulting in a sidewall profile having a negative slope … the final contact windows 319’ has a width 321’ in a lower region greater than a width in an upper region”, “the photoresist 311 is removed and a wiring material is formed on the upper electric layer 309 and inside the contact window 319’”, “the etch rate of the lower dielectric layer 305 gradually decreases in the direction from bottom to top, and the etch rate in the upper region of the lower dielectric layer 305 is relatively low … the etch rate in the bottommost region of the lower dielectric layer can be set relatively high”.
However Jeon does not explicitly teach a ratio of a maximum sectional dimension of the first conductive segment to a maximum sectional dimension of the second conductive segment is greater than or equal to 2.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to control the etching rates in different materials of the insulating/dielectric layers to form contact windows with desirable profile where the width 321’ of the lower portion being at least twice wide as the upper portion.
The differences in a ratio of two different sectional dimension values will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ratio of two different sectional dimension values are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph on page 9) of the ratio of two different sectional dimension values, it would have been obvious to one of ordinary skill in the art to form a multilayered contact structure in a trench or via with multilayered insulating structure where the width of a lower portion being at least twice larger than the width of the upper portion which may be limited by the aspect ratio of the trench or via, by the width of the upper portion, by the materials used for different insulating/dielectric layers, etc.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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