DETAILED ACTION
This Office action is in response to the election and amendment filed 19 August 2025. By this amendment, claims 8 and 12 are amended; claims 2-3, 5-6, and 17-18 are withdrawn. Claims 1-20 are currently pending; claims 2-3, 5-6, and 17-18 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 29 August 2023 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because NPL document 2 does not include an English translation. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Applicant’s election of Species I, claims 1, 4, 7-16, and 19-20, in the reply filed on 19 August 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Objections
Claim 12 is objected to because of the following informalities: line 2, delete the word “as” between “from” and “a material”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7, 8, 10, 14, 15, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 5,976,936 to Miyajima et al. (hereinafter “Miyajima”).
Regarding independent claim 1, Miyajima (Fig. 15) discloses a semiconductor device, comprising:
a substrate 1 (col. 7, l. 51-52);
a channel layer 3 (col. 7, l. 55-57), located on the substrate, wherein the channel layer has a trench 9 (col. 8, l. 3);
a gate structure 13 (col. 14, l. 10-12), disposed in the trench 9 (Fig. 15);
a first doped region 6 (left of 13, col. 14, l. 14) and a second doped region 6 (right of 13, col. 14, l. 14), disposed in the channel layer on two sides of the gate structure 13 (Fig. 15);
a third doped region (disposed in 1; col. 7, l. 51-52) located in the substrate 1 below the channel layer 3; and
a channel cap layer 11a (col. 14, l. 18-20), located between the gate structure 13 and the first doped region 6, between the gate structure 13 and the second doped region 6, and between the gate structure 13 and the channel layer 3 (Fig. 15), wherein an energy band gap of the channel cap layer 11a (col. 14, l. 18-25 - 4H-SiC) is greater than an energy band gap of the channel layer 3 (col. 14, l. 18-25 - 6H-SiC; energy band gap of 4H-SiC greater than energy band gap of 6H-SiC).
Regarding claim 4, Miyajima discloses the semiconductor device as claimed in claim 1. The limitations “wherein a difference between the energy band gap of the channel cap layer and the energy band gap of the channel layer is less than 1 eV” are considered claimed properties or functions. Miyajima discloses the structure as recited in the claim as currently drafted, thus the structure of Miyajima inherently possesses the claimed properties or functions of the claimed structure. MPEP § 2112.01(I).
Regarding claim 7, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 1, wherein the channel cap layer 11a comprises 6H—SiC, 4H—SiC, 2H—SiC, GaN, AlGaN, AlN, α-Ga.sub.2O.sub.3, diamond, SiGe, Si, or a combination thereof (col. 14, l. 18-25 - 4H-SiC).
Regarding claim 8, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 1, wherein a material of the channel cap layer 11a is the same as a material of the channel layer 3 but has a different crystal phase (col. 14, l. 18-25).
Regarding claim 10, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 8, wherein the channel layer 3 comprises 6H—SiC (col. 14, l. 18-25), and the channel cap layer 11a comprises 4H—SiC, 2H—SiC, or a combination thereof (col. 14, l. 18-25).
Regarding claim 14, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 1. The limitations “wherein a number of defects of an interface between the channel cap layer and a gate dielectric layer of the gate structure is greater than a number of defects of an interface between the channel cap layer and the channel layer” are considered claimed properties or functions. Miyajima discloses the structure as recited in the claim as currently drafted, thus the structure of Miyajima inherently possesses the claimed properties or functions of the claimed structure. MPEP § 2112.01(I).
Regarding claim 15, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 1. The limitations “wherein a lattice mismatch rate between the channel layer and a gate dielectric layer of the gate structure is greater than 10%” are considered claimed properties or functions. Miyajima discloses the structure as recited in the claim as currently drafted, thus the structure of Miyajima inherently possesses the claimed properties or functions of the claimed structure. MPEP § 2112.01(I).
Regarding claim 19, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 1, further comprising a buffer layer 2 (col. 7, l. 63-65) located below the channel layer 3 (Fig. 15).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 11, 13, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Miyajima.
Regarding claim 9, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 8, however fails to expressly disclose wherein the channel layer comprises 4H—SiC, and the channel cap layer comprises 2H—SiC. Miyajima does disclose the use of a same material (SiC) in the channel layer having a different crystal phase than the channel cap layer (col. 14, l. 18-25) and also discloses the use of other crystal phases of SiC (see col. 8, l. 19-22; col. 13, l. 10-15, col. 14, l. 18-25) in said layers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the recited materials in the channel layer and channel cap layer of Miyajima for the purpose of using art recognized, alternative high-performance materials known to be suitable for use in power semiconductor devices.
Regarding claim 11, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 8, however fails to expressly disclose wherein the channel layer comprises 3C—SiC, and the channel cap layer comprises 6H—SiC, 4H—SiC, 2H—SiC, or a combination thereof. Miyajima does disclose the use of a same material in the channel layer having a different crystal phase than the channel cap layer (col. 14, l. 18-25) and also discloses the use of other crystal phases of SiC (see col. 8, l. 19-22; col. 13, l. 10-15; col. 14, l. 18-25) in said layers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the recited materials in the channel layer and channel cap layer of Miyajima for the purpose of using art recognized, alternative high-performance materials known to be suitable for use in power semiconductor devices.
Regarding claim 13, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 1, and in a different embodiment, discloses wherein the channel cap layer 11a and the channel layer 3 are of a same conductivity type (col. 14, l. 56-60), a doped concentration of the channel cap layer (col. 10, l. 35-37 - 1015 to 1017/cm3) is greater than or equal to a doped concentration of the channel layer (col. 9, 43-45 - 1017/cm3; doped concentrations equal). Miyajima contemplates modifications and variations to the disclosed embodiments to be within the scope of the invention (col. 14, l. 60-67), thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of the embodiment of Fig. 15 to include the above recited features for the purpose of providing an alternative, art-recognized configuration of an insulated gate type semiconductor device, as exemplified by the disclosure of Miyajima.
Regarding claim 16, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 1, wherein a thickness of the channel cap layer is less than 100 nm (col. 10, l. 25-30).
Regarding claim 20, Miyajima (Fig. 15) discloses the semiconductor device as claimed in claim 1, wherein the channel cap layer 11a comprises a first portion (left portion) and a second portion (right portion) respectively located on sidewalls of the trench 9 and separated by an insulating layer 12 (col. 11, l. 31-35) disposed at a bottom part of the trench 9 (Fig. 15). In another embodiment, Miyajama (Fig. 1) discloses a thickness of the insulating layer 12 (thickness at 12b; col. 11, l. 30-38) is greater than a thickness of a gate dielectric layer 12 (thickness at vertical sides of 12) of the gate structure (Fig. 1). Miyajima contemplates modifications and variations to the disclosed embodiments to be within the scope of the invention (col. 14, l. 60-67), thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the recited insulating layer and gate dielectric layer of the embodiment of Fig. 1 in the device of Fig. 15 for the purpose of providing an alternative configuration of insulating layer and gate dielectric layer known in the art to be suitable for use in a trench gate semiconductor device, as exemplified by the disclosure of Miyajima.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2008/0048258 A1 to de Fresart et al. disclosing a semiconductor device including a trench gate; US 2022/0165866 A1 to Chang et al. disclosing an HEMT; US 2020/0083332 A1 to Lee et al. disclosing a semiconductor device including a β-Ga.sub.2O.sub.3 channel layer.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
30 September 2025
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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