Prosecution Insights
Last updated: August 17, 2026
Application No. 18/151,487

SEMICONDUCTOR DEVICE

Final Rejection §103
Filed
Jan 09, 2023
Priority
Nov 08, 2022 — TW 111142548
Examiner
CHAN, CANDICE
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Industrial Technology Research Institute
OA Round
2 (Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
402 granted / 553 resolved
+4.7% vs TC avg
Strong +19% interview lift
Without
With
+19.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
29 currently pending
Career history
614
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
53.3%
+13.3% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
17.7%
-22.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 553 resolved cases

Office Action

§103
DETAILED ACTION This Office action is in response to the amendment filed 30 December 2025. By this amendment, claims 1 and 12 are amended; claim 13 is cancelled; claim 21 is new. Claims 1-12 and 14-21 are currently pending; claims 2-3, 5-6, and 17-18 stand withdrawn. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim 1 as amended have been considered but are moot because the grounds of rejection have been modified in response to Applicant’s amendments to the claims. The amended limitations are addressed by the modified grounds of rejection below. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 4, 7-11, 14-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0264562 A1 to Cheng et al. (hereinafter “Cheng”) in view of US 5,976,936 to Miyajima et al. (hereinafter “Miyajima”). Regarding independent claim 1, Cheng (Fig. 1) discloses a semiconductor device, comprising: a substrate 14 (¶ 0035); a channel layer 16 (¶ 0036), located on the substrate, wherein the channel layer has a trench 70 (¶ 0037); a gate structure 34 (¶ 0041), disposed in the trench 70 (Fig. 1); a first doped region 24 (left of 34, ¶ 0037) and a second doped region 24 (right of 34, ¶ 0037), disposed in the channel layer 16 on two sides of the gate structure 34 (Fig. 1); a third doped region (disposed in 14; ¶ 0035) located in the substrate 14 below the channel layer 16; and a channel cap layer 30 (¶ 0037), located between the gate structure 34 and the first doped region 24, between the gate structure 34 and the second doped region 24, and between the gate structure 34 and the channel layer 16 (Fig. 1); wherein the channel cap layer 30 and the channel layer 16 are of a same conductivity type (¶¶ 0056-57 -- 50 is etched to form 30), and a doped concentration of the channel cap layer 30 (¶ 0056) is greater than a doped concentration of the channel layer 16 (¶ 0049). Cheng does not expressly disclose: an energy band gap of the channel cap layer is greater than an energy band gap of the channel layer. In the same field of endeavor, Miyajima (Fig. 15) discloses a semiconductor device including an energy band gap of the channel cap layer 11a (col. 14, l. 18-25 - 4H-SiC) is greater than an energy band gap of the channel layer 3 (col. 14, l. 18-25 - 6H-SiC; energy band gap of 4H-SiC greater than energy band gap of 6H-SiC). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cheng to include the materials of Miyajima, resulting in the above recited energy band gap relationship, for the purpose of increasing mobility of the carrier flow direction (Miyajima, col. 14, l. 20-25). Regarding claim 4, Cheng and Miyajima disclose the semiconductor device as claimed in claim 1. The limitations “wherein a difference between the energy band gap of the channel cap layer and the energy band gap of the channel layer is less than 1 eV” are considered claimed properties or functions. Cheng and Miyajima disclose the structure as recited in the claim as currently drafted, thus the structure of Cheng and Miyajima is presumed to possess the claimed properties or functions of the claimed structure. MPEP § 2112.01(I). Regarding claim 7, Cheng and Miyajima disclose the semiconductor device as claimed in claim 1, wherein the channel cap layer 11a comprises 6H—SiC, 4H—SiC, 2H—SiC, GaN, AlGaN, AlN, α-Ga.sub.2O.sub.3, diamond, SiGe, Si, or a combination thereof (Miyajima, col. 14, l. 18-25 - 4H-SiC). Regarding claim 8, Cheng and Miyajima disclose the semiconductor device as claimed in claim 1, wherein a material of the channel cap layer 11a is the same as a material of the channel layer 3 but has a different crystal phase (Miyajima, col. 14, l. 18-25). Regarding claim 9, Cheng and Miyajima disclose the semiconductor device as claimed in claim 8, however fail to expressly disclose wherein the channel layer comprises 4H—SiC, and the channel cap layer comprises 2H—SiC. Miyajima does disclose the use of a same material (SiC) in the channel layer having a different crystal phase than the channel cap layer (col. 14, l. 18-25) and also discloses the use of other crystal phases of SiC (see col. 8, l. 19-22; col. 13, l. 10-15, col. 14, l. 18-25) in said layers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the recited materials in the channel layer and channel cap layer of Cheng and Miyajima for the purpose of using art recognized, alternative high-performance materials known to be suitable for use in power semiconductor devices. Regarding claim 10, Cheng and Miyajima disclose the semiconductor device as claimed in claim 8, wherein the channel layer 3 comprises 6H—SiC (Miyajima, col. 14, l. 18-25), and the channel cap layer 11a comprises 4H—SiC, 2H—SiC, or a combination thereof (Miyajima, col. 14, l. 18-25). Regarding claim 11, Cheng and Miyajima disclose the semiconductor device as claimed in claim 8, however fail to expressly disclose wherein the channel layer comprises 3C—SiC, and the channel cap layer comprises 6H—SiC, 4H—SiC, 2H—SiC, or a combination thereof. Miyajima does disclose the use of a same material in the channel layer having a different crystal phase than the channel cap layer (col. 14, l. 18-25) and also discloses the use of other crystal phases of SiC (see col. 8, l. 19-22; col. 13, l. 10-15; col. 14, l. 18-25) in said layers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the recited materials in the channel layer and channel cap layer of Cheng and Miyajima for the purpose of using art recognized, alternative high-performance materials known to be suitable for use in power semiconductor devices. Regarding claim 14, Cheng and Miyajima disclose the semiconductor device as claimed in claim 1. The limitations “wherein a number of defects of an interface between the channel cap layer and a gate dielectric layer of the gate structure is greater than a number of defects of an interface between the channel cap layer and the channel layer” are considered claimed properties or functions. Cheng and Miyajima disclose the structure as recited in the claim as currently drafted, thus the structure of Cheng and Miyajima is presumed to possess the claimed properties or functions of the claimed structure. MPEP § 2112.01(I). Regarding claim 15, Cheng and Miyajima disclose the semiconductor device as claimed in claim 1. The limitations “wherein a lattice mismatch rate between the channel layer and a gate dielectric layer of the gate structure is greater than 10%” are considered claimed properties or functions. Chen gand Miyajima disclose the structure as recited in the claim as currently drafted, thus the structure of Cheng and Miyajima is presumed to possess the claimed properties or functions of the claimed structure. MPEP § 2112.01(I). Regarding claim 16, Cheng and Miyajima disclose the semiconductor device as claimed in claim 1, wherein a thickness of the channel cap layer 30 is less than 100 nm (Cheng, ¶ 0056). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. MPEP § 2144.05(I). Regarding claim 19, Cheng and Miyajima disclose the semiconductor device as claimed in claim 1, further comprising a buffer layer 12 (Cheng, ¶ 0035) located below the channel layer 30 (Cheng, Fig. 1). Regarding claim 20, Cheng (Fig. 1) and Miyajima disclose the semiconductor device as claimed in claim 1, wherein the channel cap layer 30 comprises a first portion (left portion) and a second portion (right portion) respectively located on sidewalls of the trench 70 and separated by an insulating layer 32 (¶ 0040) disposed at a bottom part of the trench 70 (Cheng, Fig. 1), and a thickness of the insulating layer (thickness, from left to right, at horizontal bottom portion of 32) is greater than a thickness of a gate dielectric layer 32 (thickness, from left to right, at vertical sides of 32) of the gate structure. Allowable Subject Matter Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 21 is allowed. The following is a statement of reasons for the indication of allowable subject matter: independent claim 21 incorporates the previously indicated allowable subject matter of claim 12 and includes all the limitations of original base claim 1. Independent claim 21 recites, inter alia, wherein a material of the channel cap layer is different from a material of the channel layer, wherein the channel layer comprises ß-Ga₂O₃, the channel cap layer comprises AlxGa₁-ₓO, A1GaxN1-x, or a combination thereof, and X is between 0 and 1. These limitations, in combination with the remaining limitations of the independent claim, are not anticipated or rendered obvious by the prior art. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. CANDICE Y. CHAN Examiner Art Unit 2813 16 May 2026 /STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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Prosecution Timeline

Jan 09, 2023
Application Filed
Oct 09, 2025
Non-Final Rejection mailed — §103
Dec 30, 2025
Response Filed
May 27, 2026
Final Rejection mailed — §103
Jul 14, 2026
Interview Requested
Jul 23, 2026
Examiner Interview Summary
Jul 23, 2026
Applicant Interview (Telephonic)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+19.2%)
3y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 553 resolved cases by this examiner. Grant probability derived from career allowance rate.

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