DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 03/03/2026. Claims 1-20 are pending in this application. Claims 1, 11, and 17 are amended.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2019/0333862; hereinafter ‘Wang’) in view of Soldano et al. (US 2021/0356519; hereinafter ‘Soldano’).
Regarding claim 1, Wang teaches a method (FIG. 30, [0016]) comprising:
forming a reconstructed wafer (forming 86, FIG. 27, [0054]) comprising:
placing a package component (placing 36, FIG. 5, [0024]) over a carrier (36 over 20);
forming an interconnect structure (forming 60A, FIG. 10, [0032]) over and electrically interconnecting the plurality of package components (60A over and electrically interconnecting 36s);
forming top electrical connectors (forming 60B, 70, 74, and 78 that are electrically connected to 36, the floating stack of 60B, 70, 74, and 78 on the right side, which is not connected to 36 is excluded, FIG. 16, [0032, 0045, 0051]; hereinafter ‘TEC1’) over and electrically connecting to the interconnect structure (TEC1 over and electrically interconnecting to 60A); and
forming alignment marks (forming 62, FIG. 10, [0031]), wherein the alignment marks are formed through a same plating process as forming the top electrical connectors (62 and 60B of TEC1 formed over 50 through a same plating process, [0032]); and
bonding an additional package component (bonding 88, FIG. 27, [0055]) to the reconstructed wafer through solder regions (88 to 86 through 80, [0052]), wherein the solder regions are physically joined to the top electrical connectors (80 is physically joined to TEC1).
Wang does not teach the method comprising: placing a plurality of package components over a carrier; and probing probe pads in the top electrical connectors, wherein the probing is performed using the alignment marks for aligning to the probe pads.
Soldano teaches a method (FIG. 8B, [0032]) comprising:
placing a plurality of package components (placing a plurality of die, [0058]) over a carrier (100, FIG. 1A(i)); and
probing probe pads (probing 130, which provide electrical signals during wafer-level testing, FIG. 1A(ii), [0079]) in the top electrical connectors (112),
wherein the probing is performed using the alignment marks for aligning to the probe pads (the probing is performed by using 113 for aligning to 130, FIG. 1A(iii), [0072, 0078-0079]).
As taught by Soldano, one of ordinary skill in the art would utilize and modify the above teaching into Wang to obtain and achieve the method comprising: placing a plurality of package components over a carrier; and probing probe pads in the top electrical connectors, wherein the probing is performed using the alignment marks for aligning to the probe pads as claimed, because the combination of optical and electrical probes enables simultaneous probing, which improves the accuracy, repeatability, and reliability of wafer-level probing for a plurality of package components [0032, 0078].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Soldano in combination with Wang due to above reason.
Regarding claim 2, Wang in view of Soldano teaches the method of claim 1, further comprising dispensing an underfill (Wang: dispensing 90, FIG. 27, [0055]) between, and in contact with, the reconstructed wafer and the additional package component (90 between and in contact with 86 and 88), wherein the underfill contacts the alignment marks (90 contact with 62).
Regarding claim 3, Wang in view of Soldano teaches the method of claim 2, wherein after the bonding, an entire top surface of one of the alignment marks is covered by the underfill (Wang: the entire top surface of 62 is covered by 90, FIG. 27).
Regarding claim 5, Wang in view of Soldano teaches the method of claim 1, wherein the top electrical connectors are arranged as a plurality of groups (Wang: TEC1 are arranged as a plurality of groups, FIG. 17) with corner regions (the right side area where the floating stack composed of 60B, 70, 74, and 78, together with 62, is formed; hereinafter ‘CR’) between the plurality of groups being free from the top electrical connectors (CR between the plurality of groups of TEC1 being free from TEC1), and wherein the alignment marks are formed in the corner regions (62 is formed in CR).
Regarding claim 6, Wang in view of Soldano teaches the method of claim 5, further comprising drilling a plurality of holes (Wang: 82, FIG. 17, [0053]) in the reconstructed wafer (82 in 86), each in one of the corner regions (82 in CR), wherein the plurality of holes are spaced apart from the alignment marks (82 is spaced apart from 62).
Regarding claim 7, Wang in view of Soldano teaches the method of claim 5, but Wang does not teach the method wherein the probing is performed using a sub set of the alignment marks to align to the probe pads, and wherein the sub set of the alignment marks is distributed in a plurality of corner regions that are arranged as a row.
Soldano teaches the method wherein the probing is performed using a sub set of the alignment marks (the sub set of 113 provided within each 102, FIG. 1A(iii); hereinafter ‘SS113’) to align to the probe pads (SS113 to align to 130, which provide electrical signals during wafer-level testing, FIG. 1A(ii), [0079]), and wherein the sub set of the alignment marks is distributed in a plurality of corner regions (SS113 distributed along a left side region of 102, FIG. 8A) that are arranged as a row (SS113 arranged in a row).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Soldano to obtain and achieve the method wherein the probing is performed using a sub set of the alignment marks to align to the probe pads, and wherein the sub set of the alignment marks is distributed in a plurality of corner regions that are arranged as a row as claimed, because controlling the combination of a sub set of alignment marks and probe pad alignment reduces alignment complexity and time, while still maintaining sufficient positional accuracy, and the same alignment principle can be applied regardless of die expansion, since each die inherently induces its own subset of alignment marks [0072].
Regarding claim 8, Wang in view of Soldano teaches the method of claim 1, wherein the forming the alignment marks and the forming the top electrical connectors share common formation processes (Wang: 62 and TEC1 being formed by metal deposition, [0031, 0045, 0048, 0051]).
Regarding claim 9, Wang in view of Soldano teaches the method of claim 1, but Wang does not teach the method further comprising forming a top surface dielectric layer over the interconnect structure, wherein an entirety of one of the alignment marks is over the top surface dielectric layer.
Soldano teaches the method further comprising forming a top surface dielectric layer (138, FIG. 1A(ii), [0070]) over the interconnect structure (132 in 103, FIG. 1A(ii), [0060]) wherein an entirety of one of the alignment marks (113) is over the top surface dielectric layer (113 is over 138).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Soldano to obtain and achieve the method further comprising forming a top surface dielectric layer over the interconnect structure, wherein an entirety of one of the alignment marks is over the top surface dielectric layer as claimed, because the alignment mark must be positioned on the upper dielectric layer to enable direct optical recognition for probing alignment, while the interconnects are embedded below to prevent optical interference and maintain electrical isolation [0070, 0098].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0333862) in view of Soldano (US 2021/0356519), and further in view of Huang et al. (US 2020/0091086; hereinafter ‘Huang’).
Regarding claim 4, Wang in view of Soldano teaches the method of claim 1, but does not teach the method wherein after the bonding, one of the solder regions bonds one of the alignment marks to the additional package component.
Huang teaches a method (FIG. 20, [0047]) wherein after the bonding, one of the solder regions (76, FIG. 14, [0038]) bonds one of the alignment marks (32A, [0039]) to the additional package component (200, [0038]).
As taught by Huang, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Soldano to obtain and achieve the method wherein after the bonding, one of the solder regions bonds one of the alignment marks to the additional package component as claimed, because soldering strengthens the physical bonding of the alignment marks to the upper package, which in turn improves the mechanical robustness of the stacked package structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Huang in combination with Wang in view of Soldano due to above reason.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0333862) in view of Soldano (US 2021/0356519), and further in view of Yu et al. (US 2021/0074553; hereinafter ‘Yu’).
Regarding claim 10, Wang in view of Soldano teaches the method of claim 1, further comprising:
forming a metal pad (Wang: the rightmost 60B, FIG. 10, [0032]; hereinafter ‘RM60B’) over the interconnect structure (RM60B over 60A);
forming a top surface dielectric layer (66, FIG. 21, [0059]) over the metal pad (66 over RM60B); and
forming an opening (68 and 94, FIG. 21, [0060]) in the top surface dielectric layer to reveal the metal pad (68 in 66 to reveal RM60B),
wherein one of the alignment marks comprises a via (the portion 70A within 94, FIG. 22, [0061]; hereinafter ‘V70A’) in the opening (V70A in 94), and
a line portion (the portion 70A over 66; hereinafter ‘L70A’) over the top surface dielectric layer (L70A over 66).
Wang in view of Soldano does not teach the method further comprising the metal pad electrically disconnected from the interconnect structure.
Yu teaches a method (FIG. 35, [0014]) further comprising a metal pad (the leftmost 50B positioned above the second-lowest 52, FIG. 8, [0031]; hereinafter ‘MP50B’) over and electrically disconnected from the interconnect structure (MP50B over and electrically disconnected from 50A).
As taught by Yu, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Soldano to obtain and achieve the method further comprising the metal pad electrically disconnected from the interconnect structure as claimed, because selective via connection in multi-layer redistribution structures enables higher routing density, better signal integrity, and improved efficiency of the conductive path.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yu in combination with Wang in view of Soldano due to above reason.
Claims 11-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0333862) in view of Yu (US 2021/0074553).
Regarding claim 11, Wang teaches a method (FIG. 30, [0016]) comprising:
encapsulating a device dies (encapsulating 36, FIG. 6, [0026]) in an encapsulant (48);
forming a surface dielectric layer (forming a surface of 50, FIG. 7, [0028]; hereinafter ‘50S’), the surface dielectric layer (50S) comprising a top surface (a surface of 50 facing away from 48; hereinafter ‘50T’);
forming via openings (forming 52, FIG. 7, [0028]) in the surface dielectric layer (52 in 50);
forming top electrical connectors (forming 60, 70, 74, 78, and 80, FIG. 16, [0048, 0051-0052]; hereinafter ‘TEC11’), each comprising:
a via portion (a via portion of 60, 70, and 74; hereinafter ‘VP’) extending into the surface dielectric layer (VP extending into 50);
a pad portion (a pad portion of 60, 70, 74, and 78; hereinafter ‘PP’) over and joined to the via portion (PP over and joined to VP), wherein a first bottom surface of the pad portion (the contact surface between 60 of PP and 50; hereinafter ‘PPS’) interfaces with the top surface of the surface dielectric layer (50T) to form a first interface (an interface between PPS and 50T); and
a first solder layer (solder layers of 80, [0052]; hereinafter ‘SL’) over the pad portion (SL over 78 of PP);
forming a first alignment mark (forming the first 62 from the left, FIG. 10, [0031]; hereinafter ‘62L’) over the surface dielectric layer (62 over 50), wherein a second bottom surface of the first alignment mark (the contact surface between 62L and 50; hereinafter ‘62LS’) interfaces with the top surface of the surface dielectric layer (50T) to form a second interface (an interface between 62LS and 50T);
bonding bond pads (bonding 78) of the top electrical connectors (78 of TEC11) to an additional package component (88. FIG. 27, [0055]); and
dispensing an underfill (dispensing 90, FIG. 27, [0055]), wherein the underfill contacts both of the top electrical connectors and the first alignment mark (90 contacts both of TEC11 and 62).
Wang does not teach the method comprising: encapsulating a plurality of device dies in an encapsulant; forming an interconnect structure over and electrically connecting to the plurality of device dies; forming a plurality of metal pads over and electrically connecting to the interconnect structure; forming a surface dielectric layer over the plurality of metal pads.
Yu teaches method (FIG. 35, [0014]) comprising:
encapsulating a plurality of device dies (encapsulating a plurality of 26, FIG. 2, [0022]) in an encapsulant (38);
a forming an interconnect structure (forming 50A, FIG. 7, [0030]) over and electrically connecting to the plurality of device dies (50A over and electrically connecting to 26);
forming a plurality of metal pads (forming 50B, FIG. 8, [0031]) over and electrically connecting to the interconnect structure (20 over and electrically connecting to 50A);
forming a surface dielectric layer (forming 52, FIG. 8, [0031]) over the plurality of metal pads (52 over 50B).
As taught by Yu, one of ordinary skill in the art would utilize and modify the above teaching into Wang to obtain and achieve the method comprising: encapsulating a plurality of device dies in an encapsulant; forming an interconnect structure over and electrically connecting to the plurality of device dies; forming a plurality of metal pads over and electrically connecting to the interconnect structure; forming a surface dielectric layer over the plurality of metal pads as claimed, because forming an in-wafer interconnect structure allows direct cross-wafer connections among dies without using solder or repeaters, thereby reducing resistance and improving signal integrity [0031, 0053].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yu in combination with Wang due to above reason.
Regarding claim 12, Wang in view of Yu teaches the method of claim 11, wherein at a time after the bonding, the first alignment mark is electrically floating (Wang: 62 is electrically floating, since 62 is in contact with 50 and 90 which are dielectric materials, FIG. 27, [0026, 0028]).
Regarding claim 14, Wang in view of Yu teaches the method of claim 11, wherein the first alignment mark and the top electrical connectors are formed through common plating processes (Wang: 62 and TEC11 are formed through plating processes, [0031, 0045]).
Claims 13 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0333862) in view of Yu (US 2021/0074553), and further in view of Soldano (US 2021/0356519).
Regarding claim 13, Wang in view of Yu teaches the method of claim 11, but does not teach the method further comprising probing probe pads in the top electrical connectors, wherein the probing is performed using the first alignment mark for alignment.
Soldano teaches a method (FIG. 8B, [0032]) comprising: probing probe pads (130, which provide electrical signals during wafer-level testing, FIG. 1A(ii), [0079]) in the top electrical connectors (112), wherein the probing is performed using the first alignment mark for alignment (the probing is performed using 113 for alignment, FIG. 1A(iii), [0072, 0078-0079]).
As taught by Soldano, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Yu to obtain and achieve the method further comprising probing probe pads in the top electrical connectors, wherein the probing is performed using the first alignment mark for alignment as claimed, because the combination of optical and electrical probes enables simultaneous probing, which improves the accuracy, repeatability, and reliability of wafer-level probing [0032, 0078].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Soldano in combination with Wang in view of Yu due to above reason.
Regarding claim 17, Wang teaches a method (FIG. 30, [0016]) comprising:
encapsulating a device die (encapsulating 36, FIG. 6, [0024, 0026]) in an encapsulant (48);
forming an interconnect structure (forming 42, FIG. 10, [0025]) over and electrically connecting to the plurality of device dies (42 over and electrically connecting to 36);
forming a plurality of metal pads (forming 60A, FIG. 10, [0032]) over and electrically connecting to the interconnect structure (60A over and electrically connecting to 42);
forming a surface dielectric layer (forming 66, FIG. 11, [0034]);
forming top electrical connectors (forming 60B, 70, 74, 78, and 80, FIG. 16, [0032, 0048, 0051-0052]; hereinafter ‘TEC17’) over and electrically connecting to the interconnect structure (TEC17 over and electrically connecting to 42), wherein the top electrical connectors (TEC17) comprise first bottom surfaces (the contact surface between 60B of TEC17 and 50, FIG. 16, [0028]; hereinafter ‘TEC17SB’);
forming a plurality of alignment marks (forming 62, FIG. 10, [0031]), wherein the forming the top electrical connectors and the forming the plurality of alignment marks share common processes (TEC17 and 62 are formed by metal deposition, [0031, 0045, 0048, 0051]), wherein the plurality of alignment marks (62) comprise second bottom surface (a contact surface between 62 and 50; hereinafter ‘62SB’) coplanar with the first bottom surfaces (62SB coplanar with TEC17SB, FIG. 16); and
bonding the top electrical connectors (bonding TEC17, FIG. 27) to an additional package component (88, [0055]).
Wang does not teach the method comprising: encapsulating a plurality of device dies in an encapsulant; probing probe pads in the top electrical connectors, wherein the probing is performed by using the plurality of alignment marks for aligning to the probe pads.
Yu teaches method (FIG. 35, [0014]) comprising: encapsulating a plurality of device dies (encapsulating a plurality of 26, FIG. 2, [0022]) in an encapsulant (38).
As taught by Yu, one of ordinary skill in the art would utilize and modify the above teaching into Wang to obtain and achieve the method comprising: encapsulating a plurality of device dies in an encapsulant as claimed, because the plurality of device dies in the same wafer to enable cross-wafer interconnection through RDSs for high-speed signal routing [0053].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yu in combination with Wang due to above reason.
Wang in view of Yu does not teach the method comprising: probing probe pads in the top electrical connectors, wherein the probing is performed by using the plurality of alignment marks for aligning to the probe pads.
Soldano teaches a method (FIG. 8B, [0032]) comprising: probing probe pads (130, which provide electrical signals during wafer-level testing, FIG. 1A(ii), [0079]) in the top electrical connectors (112), wherein the probing is performed by using the plurality of alignment marks for aligning to the probe pads (the probing is performed by using 113 and 114 for aligning to 130, FIG. 1A(iii), [0072, 0078-0079]).
As taught by Soldano, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Yu to obtain and achieve the method comprising: probing probe pads in the top electrical connectors, wherein the probing is performed by using the plurality of alignment marks for aligning to the probe pads as claimed, because the combination of optical and electrical probes enables simultaneous probing, which improves the accuracy, repeatability, and reliability of wafer-level probing [0032, 0078].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Soldano in combination with Wang in view of Yu due to above reason.
Regarding claim 18, Wang in view of Yu and Soldano teaches the method of claim 17, wherein after the bonding, the plurality of alignment marks are electrically floating (Wang: 62 is electrically floating, since 62 is in contact with 50 and 90 which are dielectric materials, FIG. 27, [0026, 0028]).
Regarding claim 19, Wang in view of Yu and Soldano teaches the method of claim 17, further comprising dispensing an underfill (Wang: dispensing 90, FIG. 27, [0055]), wherein the underfill contacts sidewalls of both of the top electrical connectors and the plurality of alignment marks (90 contacts sidewalls of both of TEC17 and 62).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0333862) in view of Yu (US 2021/0074553), and further in view of Mawatari (US 2013/0228916).
Regarding claim 15, Wang in view of Yu teaches the method of claim 11, but does not teach the method wherein the first alignment mark comprises a non-solder portion, and a second solder layer over the non-solder portion.
Mawatari teaches a method (FIG. 1, [0001]) wherein the first alignment mark (an alignment mark having 110 and 160, [0020, 0022]) comprises a non-solder portion (110 is made of a metal), and a second solder layer (160 is made of a solders, [0024]) over the non-solder portion (106 over 110).
As taught by Mawatari, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Yu to obtain and achieve the method wherein the first alignment mark comprises a non-solder portion, and a second solder layer over the non-solder portion as claimed, because the solder layer of the alignment mark utilizes molten surface tension to align the chip to the substrate, thereby directly fulfilling the alignment function [0009-0010, 0032, 0035].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Mawatari in combination with Wang in view of Yu due to above reason.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0333862) in view of Yu (US 2021/0074553), and further in view of Huang (US 2020/0091086).
Regarding claim 16, Wang in view of Yu teaches the method of claim 11, further comprising forming a second alignment mark (Wang: the second 62 form the left, FIG. 10, [0031]).
Wang in view of Yu does not teach the method wherein the second alignment mark extends into the surface dielectric layer to contact an underlying metal pad, and wherein the second alignment mark and the underlying metal pad are in combination electrically floating.
Huang teaches a method (FIG. 20, [0047]) wherein the second alignment mark (32A, FIG. 14, [0018]) extends into the surface dielectric layer (28, [0017]) to contact an underlying metal pad (26A, [0016]), and wherein the second alignment mark and the underlying metal pad are in combination electrically floating (32A and 26A are electrically floating, [0019, 0039])
As taught by Huang, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Yu to obtain and achieve the method wherein the second alignment mark extends into the surface dielectric layer to contact an underlying metal pad, and wherein the second alignment mark and the underlying metal pad are in combination electrically floating as claimed, because the alignment marks are electrically insulated to prevent interference or short circuits, serving solely as reliable alignment references within the package [0039].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Huang in combination with Wang in view of Yu due to above reason.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2019/0333862) in view of Yu (US 2021/0074553) and Soldano (US 2021/0356519), and further in view of Huang (US 2020/0091086).
Regarding claim 20, Wang in view of Yu and Soldano teaches the method of claim 17, but does not teach the method wherein the plurality of alignment marks are bonded to the additional package component through additional solder layers.
Huang teaches a method (FIG. 20, [0047]) wherein the plurality of alignment marks (32A, [0039]) are bonded to the additional package component (200, [0038]) through additional solder layers (76).
As taught by Huang, one of ordinary skill in the art would utilize and modify the above teaching into Wang in view of Yu and Soldano to obtain and achieve the method wherein the plurality of alignment marks are bonded to the additional package component through additional solder layers as claimed, because soldering strengthens the physical bonding of the alignment marks to the upper package, which in turn improves the mechanical robustness of the stacked package structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Huang in combination with Wang in view of Yu and Soldano due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Applicant’s amendments to independent claims 1, 11, and 17 have been fully considered but are not persuasive because the previously applied prior art of record teaches or suggests the amended claim limitations.
Regarding claim 1, Wang teaches forming alignment marks 62 and top electrical connectors 60B through the same plating process (FIG. 10, [0032]), as set forth in the rejection above.
Regarding claim 11, Wang teaches a first bottom surface of the pad portion (the contact surface between 60 of PP and 50; PPS) interfacing with the top surface of the surface dielectric layer 50T to form a first interface, and a second bottom surface of the first alignment mark (the contact surface between 62L and 50; 62LS) interfacing with the top surface of the surface dielectric layer 50T to form a second interface (FIGS. 10 and 16, [0031-0032, 0048, 0051-0052]), as set forth in the rejection above.
Regarding claim 17, Wang teaches top electrical connectors TEC17 comprising first bottom surfaces TEC17SB and alignment marks 62 comprising second bottom surfaces 62SB coplanar with the first bottom surfaces (FIGS. 10 and 16, [0025, 0031-0032, 0045, 0048, 0051]), as set forth in the rejection above.
Therefore, the claim rejections to claims 1-20 are maintained.
Conclusion
Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/4/26
Prosecution Insights