DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group A1, claims 1-7 and 9-19 in the reply filed on 10/13/2025 is acknowledged. The Examiner notes that claim 5 is drawn to non-elected species A2 and is hereby withdrawn from consideration.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/09/2023 and 01/18/2024 have been by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE INCLUDING CAPACITOR.
Claim Objections
Claim 2 is objected to because of the following informalities: a period (.) exists at the end of the first clause which should be removed. Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claims 1-4, 6-12 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “n-type impurity” in claim 1 is used by the claim to mean “an impurity element having a valence of 5 or more” while the accepted meaning is “elements added to a semiconductor to enhance its electrical conductivity by introducing extra electrons;” that is, an “n-type impurity” only makes sense in the context of a semiconductor material; however, Applicant is using the term in context to metals as well. The term is indefinite because the specification does not clearly redefine the term.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 7, 11, 12, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maeng et al. (US Pub. 2021/0359100).
Regarding independent claim 1, Maeng teaches a semiconductor device (Fig. 9A-9C, 4 and/or 8A; para. 0067+; para. 0116+) comprising:
a substrate (Fig. 9B, 9C: 501; para. 0117);
a plurality of lower electrodes (Fig. 4, 8A: 101) on the substrate (para. 0067);
a dielectric layer stack (Fig. 4: 320 or Fig. 8A: 420) covering the lower electrodes (para. 0067); and
an upper electrode (Fig. 4: 331/102) covering the dielectric layer stack (para. 0067, 0071),
wherein the dielectric layer stack includes,
a first dielectric layer (Fig. 4: 321 or Fig. 8A: 421’) being on the plurality of lower electrodes, the first dielectric layer including a material having anti-ferroelectricity (para. 0068), and
a second dielectric layer (Fig. 4: 323 or Fig. 8A: 423’) between the first dielectric layer and the upper electrode, the second dielectric layer including a material having ferroelectricity (para. 0068), and wherein the upper electrode includes a first upper electrode layer (Fig. 4: 331 or Fig. 8A: 431) including an N-type impurity (para. 0073 – where N-type impurity is currently being interpreted as elements having a valence number of 5 or more; of which includes at least Ta, Mo, Ru, Ir, Nb, and Ni).
Re claim 2, Maeng teaches wherein the upper electrode further includes a second upper electrode layer (Fig. 4: 102; para. 0067), the second upper electrode layer including titanium nitride (TiN) (para. 0033),
the first upper electrode layer includes at least one of niobium (Nb), and tantalum (Ta) (para. 0073).
Re claim 3, Maeng teaches wherein the first dielectric layer includes hafnium zirconium oxide (HfxZr1-xO2, 0<x<0.5) (para. 0069), and the second dielectric layer includes hafnium zirconium oxide (HfxZr1-xO2, 0.5≤x<1) (para. 0070).
Re claim 4, wherein the first upper electrode layer is between the second dielectric layer and the second upper electrode layer and is in contact with the second dielectric layer (Fig. 4 – note that “in contact” is generally interpreted to mean that layers may exist between and/or can be interpreted as “in electrical contact”, as opposed to “in direct contact” which is generally interpreted to mean direct physical contact without any intervening layers).
Re claim 6, Maeng teaches (Fig. 8A, 8B) wherein the dielectric layer stack (420) further includes a third dielectric layer (423), and the third dielectric layer includes a material having ferroelectricity and is between the plurality of lower electrodes and the first dielectric layer of the dielectric layer stack (Fig. 8A; para. 0100+).
Re claim 7, Maeng teaches (Fig. 8B) wherein each of the lower electrodes includes a first lower electrode layer (432) including an N-type impurity (para. 0113 – where N-type impurity is currently being interpreted as elements having a valence number of 5 or more; of which includes at least Ta, Mo, Ru, Ir, Nb, an Ni), and the first lower electrode layer is in contact with the third dielectric layer of the dielectric layer stack (Fig. 8B – note that “in contact” is generally interpreted to mean that layers may exist between and/or can be interpreted as “in electrical contact”, as opposed to “in direct contact” which is generally interpreted to mean direct physical contact without any intervening layers).
Re claim 11, Maeng teaches wherein the second dielectric layer of the dielectric layer stack includes at least one of HfxZr1-xO2(0.5≤x<1), PbZrxTi1-xO3(0<x<1) (para. 0069).
Re claim 12, Maeng teaches wherein each of the lower electrodes and the upper electrode includes at least one of ruthenium (Ru), iridium (Ir), ruthenium oxide (RuOx), iridium oxide (IrOx), titanium nitride (TiN), and molybdenum nitride (MoN) (para. 0032-0033).
Regarding independent claim 17, Maeng teaches a semiconductor device (Fig. 9A-9C, 4; para. 0067+; para. 0116+) comprising:
an isolation layer (Fig. 9B, 9C: 503) defining active regions (Fig. 9B, 9C: 504) on a substrate (Fig. 9B, 9C: 501) (para. 0119);
gate electrodes (508) crossing the active regions and extending into the isolation layer (Fig. 9A, 9C; para. 0120);
first impurity regions (511) and second impurity regions (510) in the active regions and a pair of one of the first impurity regions and one of the second impurity regions adjacent to the one of the first impurity regions being on opposite sides of a corresponding one of the gate electrodes (Figs. 9A-9C; para. 0121);
bit lines (BL) over the gate electrodes and connected to the first impurity regions (Figs. 9A-9C; para. 0125);
conductive patterns (SNC) on side surfaces of the bit lines and connected to the second impurity regions (Fig. 9C; para. 0125);
a plurality of lower electrodes (601) vertically extending on the conductive patterns and connected to the conductive patterns (Fig. 9C, 10A-10F; para. 0126-0127), respectively;
at least one supporter layer (600S) spaced apart from an upper surface of the substrate in a vertical direction, extending in a direction parallel to the upper surface of the substrate, and being in contact with a side surface of the plurality of lower electrodes adjacent thereto (Fig. 10B, 10D, 10F; para. 0130-0131);
a first dielectric layer (Fig. 10A-10F: 603) covering the lower electrodes and the supporter layer, the first dielectric layer including a material having anti-ferroelectricity (para. 0128);
a second dielectric layer covering the first dielectric layer, the second dielectric layer including a material having ferroelectricity (para. 0128); and
an upper electrode (Fig. 10A-10F: 602) covering the second dielectric layer, the upper electrode including a first upper electrode layer (Refer to Fig. 4A: 331) including an N-type impurity (para. 0073 – where N-type impurity is currently being interpreted as elements having a valence number of 5 or more; of which includes at least Ta, Mo, Ru, Ir, Nb, an Ni).
Re claims 18 and 19, Maeng teaches wherein the upper electrode further includes a second upper electrode layer (Fig. 4: 102), the second upper electrode layer includes a first metal having a first valence, wherein the first metal includes titanium (Ti) (para. 0033) and
the first upper electrode layer includes the first metal and a second metal having a second valence greater than the first valence, wherein the first metal includes titanium (Ti), and the second metal includes at least one of niobium (Nb), and tantalum (Ta) (para. 0073).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9, 10, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Maeng et al. (US Pub. 2021/0359100).
Re claim 9, while Maeng is silent with respect to “wherein the second dielectric layer of the dielectric layer stack has a thickness of about 5 Å to about 20 Å”, per se; Maeng does teach the thickness to have an effect on the properties of the layer; that is, Maeng teaches the thickness to be a result effective variable (para. 0053, 0060) and given that it is known that dielectric thickness has an effect on the overall capacitance of a capacitor, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize the dielectric thickness of the second dielectric layer to arrive at the claimed invention for the purpose of both ensuring ferroelectric characteristics of the layer as well as improving the capacitance of the capacitor.
Re claim 10, while Maeng is silent with respect to a specific concentration of the N-type impurity included in the first upper electrode layer, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize the material concentrations such that the claimed invention was arrived at for the purpose of providing sufficient leakage current protection (para. 0071).
Regarding independent claim 13, Maeng teaches semiconductor device (Fig. 9A-9C, 8A; para. 0100+; para. 0116+) comprising:
a substrate (Fig. 9B, 9C: 501; para. 0117);
a plurality of lower electrodes (Fig. 8A: 101) on the substrate (para. 0101);
a dielectric layer stack (Fig. 8A: 420) covering the plurality of lower electrodes, the dielectric layer stack including a plurality of dielectric layers (para. 0101); and
an upper electrode (Fig. 8A: 431/102) covering the dielectric layer stack (0101), the upper electrode including a first metal having a first valence (para. 0033),
wherein the dielectric layer stack includes a ferroelectric layer (423’) more adjacent to the upper electrode than to the lower electrodes (Fig. 8Al; para. 0102),
the upper electrode includes a first upper electrode layer (431) including the first metal and a second metal having a second valence greater than the first valence (para. 0106).
While Maeng is silent with respect to “the ferroelectric layer having a thickness of about 5 Å to about 20 Å”, per se; Maeng does teach the thickness to have an effect on the properties of the layer; that is, Maeng teaches the thickness to be a result effective variable (para. 0053, 0060) and given that it is known that dielectric thickness has an effect on the overall capacitance of a capacitor, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize the dielectric thickness of the second dielectric layer to arrive at the claimed invention for the purpose of both ensuring ferroelectric characteristics of the layer as well as improving the capacitance of the capacitor.
Re claim 14, Maeng teaches wherein the first metal includes titanium (Ti), and the second metal includes at least one of niobium (Nb) and tantalum (Ta) (para. 0106).
Re claim 15, Maeng teaches wherein the first upper electrode layer is in contact with the ferroelectric layer (Fig. 8A – note that “in contact” is generally interpreted to mean that layers may exist between and/or can be interpreted as “in electrical contact”, as opposed to “in direct contact” which is generally interpreted to mean direct physical contact without any intervening layers).
Re claim 16, Maeng teaches wherein the dielectric layer stack further includes an anti-ferroelectric layer (421’) between the lower electrodes and the ferroelectric layer (Fig. 8A; para. 0102).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
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/MOLLY K REIDA/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899