Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 9/3/2025 have been fully considered but they are not persuasive.
The Applicant's arguments are not persuasive and rely on a conclusory assertion that the claimed "air gaps" are not disclosed by the prior art. The rejection under 35 U.S.C. § 102 is based on a plain reading of the Harada reference, which discloses structures, specifically, holes 25a/25b, that anticipate the claimed "air gaps." The applicant's failure to provide a reasoned explanation or evidence for why these structures are different is insufficient to overcome the rejection. Their assertion that the air gaps are not the same simply with an assertion that the gaps are below "W" overlooks the reference Harada as a whole. The Harada air gaps are depicted and disclosed as being formed in contact hole 21B, which extends beneath both word lines (W layers) [Fig. 1GA-1IB]. Specifically see FIG 1IC depicting the cross sectional view of airgap 25b extending in the Y direction.
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The gaps are created by the deposition of material 22B, which can be described as coating the bottom and sides of the contact hole and pinching off at the top, creating air gap 25b. A comprehensive review of the sequential cross-sections makes it clear that the air gaps 25B extend below and between the word lines. Therefore, arguments relying merely on a single cross-sectional view of the air gap's relationship to "W" are not persuasive.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harada (US 20230276612 A1)
CLAIM 16. A semiconductor structure, comprising: a substrate; an active pillar, the active pillar being arranged at intervals on the substrate; and a word line, the word line surrounding a side of the active pillar; wherein a first part of the word line surrounding the side of the active pillar is wider than a second part of the word line (Harada figs2A-B – See Regarding claim 1 below for element to element mapping.),
an air gap, the air gap being configured between adjacent two word lines (Harada figs2A-B – See Regarding claim 1 below for element to element mapping.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada (US 20230276612 A1).
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CLAIM 1: Harada discloses a semiconductor structure, comprising:
a substrate 1; and
a plurality of active pillars 7 spaced on the substrate, each of the plurality of active pillars extending along a direction perpendicular to the substrate (Harada figs. 2A);
a plurality of word lines 15 spaced on the substrate along a second direction, each of the plurality of word lines extending along a first direction, wherein the first direction intersects with the second direction, each of the plurality of word lines being connected to a given one of the plurality of active pillars positioned in the first direction (Harada figs2A-B); and
in any adjacent two of the plurality of word lines, a groove is provided on a surface of at least one of the two adjacent word lines towards other one of the two adjacent word lines, the groove penetrating through the word line along the direction perpendicular to the substrate (Harada figs2A-B – Note: The constructed word line exhibits at least two grooves. Figure 2a illustrates a first groove, where the word line appears narrower than the pillars, creating an effective groove in the space between the pillars. As shown in Figure 2b, the word line extends down the pillar to form the gates, resulting in a vertical groove in the inter-pillar region.); and
a dielectric layer 24 arranged on the substrate and covering the plurality of active pillars and the plurality of word lines (Harada figs2B);
wherein an air gap 25 is provided in the dielectric layer positioned between adjacent two of the plurality of word lines (Harada figs2B).
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CLAIM 2. Harada discloses a semiconductor structure according to claim 1, wherein each of the plurality of word lines comprises a plurality of first segments (i.e. segments surrounding pillar/segments in between pillars) and a plurality of second segments (i.e. segments surrounding pillar/segments in between pillars) connected sequentially and arranged alternately (Harada figs2A-B); the plurality of first segments surround the plurality of active pillars (Harada figs2A-B); and the groove is provided in at least one of the plurality of second segments (Harada figs2A-B), the air gap being arranged in the dielectric layer between adjacent two of the plurality of first segments along the second direction (Harada figs2A-B).
CLAIM 3. Harada discloses a semiconductor structure according to claim 2, wherein in the second direction, each of the plurality of second segments has a first surface and a second surface arranged opposite to each other; and the groove is respectively provided in the first surface and the second surface (Harada figs2A).
CLAIM 4. Harada discloses a semiconductor structure according to claim 1, wherein a section parallel to the substrate is taken as a cross section, a shape of the cross section of the groove comprising a rectangle, a trapezoid, or a semicircle (Harada figs2A-B).
CLAIM 5. Harada discloses a semiconductor structure according to claim 4, wherein when the shape of the cross section of the groove is the trapezoid, a pitch between two side walls of the groove gradually decreases in a direction pointing from a groove opening to a groove bottom of the groove (Harada figs 1JA).
CLAIM 6. Harada discloses a semiconductor structure according to claim 1, wherein along an extension direction perpendicular to a given one of the plurality of word lines (Harada figs2A). Harada may be silent upon wherein a ratio of a depth of the groove to a width of the given word line is between 1/10 and ¼ . The figures 2A of Harada, while not to scale, suggest a depth ratio that aligns with the claimed value. None the less, It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the depth of groove through routine experimentation and optimization to obtain optimal or desired device performance because the depth of groove is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada in view of Anderson (US 9299835 B1).
CLAIM 7. Harada discloses a semiconductor structure according to claim 1, however is silent upon the capability of wherein along the direction perpendicular to the substrate, a top surface of the air gap is flush with or higher than a top surface of a given one of the plurality of word lines.
While Harada may depict the airgap at a lower height than the top surface of the wordline, it was established knowledge at the time of the invention that analogous airgaps could extend to or even beyond the claimed height. For instance, Anderson et al., in Figures 11a–12, clearly demonstrate an airgap extending to or higher than the top of a wordline structure. Therefore, it would have been obvious to one of ordinary skill in the art of making semiconductor devices, motivated to improve or optimize device performance through improved isolation or reduced parasitic capacitance, to combine the known airgap configuration of Anderson with the device structure of Harada. Applying this known technique to a known device ready for improvement to yield predictable results, as this modification would, is considered obvious to one of ordinary skill in the art, in accordance with the principles set forth in KSR International Co. v. Teleflex Inc.
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Claim(s) 8-15, 18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada in view of Anderson in view of Cheng et al. (US 9299835 B1).
CLAIM 8. Harada in view of Anderson disclose a semiconductor structure according to claim 6, however may be silent upon the wherein along the extension direction perpendicular to the given word line, a width of the air gap ranges from 5 nm to 10 nm. The claimed range for the airgap width was well within the known standard for airgaps in analogous vertical transistors at the time of the invention. For example, Cheng et al. discloses that airgaps in a similar vertical transistor structure may have dimensions of "15 to 50 nm" for height and "5 to 20 nm" for width. Given this prior art teaching, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the airgap width within this established range through routine experimentation and optimization. The airgap width is a result-effective variable, and there is no evidence to suggest that its optimization in this context would be critical or produce unexpected results. Therefore, it is not inventive to discover the optimum or workable range for this variable within the known prior art conditions through routine experimentation, as is held in MPEP § 2144.05.
CLAIM 9. Harada in view of Anderson in view of Cheng et al. disclose a semiconductor structure according to claim 7, wherein a section perpendicular to the substrate is taken as a longitudinal section, a shape of the longitudinal section of the air gap being an ellipse (Harada Fig. 2B, Anderson Fig. 11, Cheng fig 1).
CLAIM 10. Harada in view of Anderson in view of Cheng et al. disclose a semiconductor structure according to claim 1, further comprising a plurality of bit lines spaced in the substrate along the first direction, each of the plurality of bit lines extending along the second direction, and each of the plurality of bit lines being connected to the plurality of active pillars positioned in the same second direction (Harada Fig. 2A-B).
CLAIM 11. Harada in view of Anderson in view of Cheng et al. disclose a semiconductor structure according to claim 10, further comprising a plurality of capacitors, the plurality of capacitors being in one-to-one correspondence with the plurality of active pillars and being correspondingly arranged on the plurality of active pillars (Harada ¶4, 5, 82, and 83).
CLAIM 12. Harada in view of Anderson in view of Cheng et al. disclose a semiconductor structure according to claim 11, wherein each of the plurality of active pillars comprises a channel region and a source region and a drain region respectively arranged on two sides of the channel region; part of the plurality of word lines surround the channel region; and one of the source region and the drain region is connected to a given one of the plurality of capacitors, other one of the source region and the drain region being connected to a given one of the plurality of bit lines (Harada ¶4, 5, 82, and 83).
CLAIM 13. Harada in view of Anderson in view of Cheng et al. disclose a semiconductor structure according to claim 12, wherein a gate oxide 14 layer is arranged between the given word line and the channel region (Harada Fig. 2A-B).
CLAIM 14. Harada in view of Anderson in view of Cheng et al. disclose a semiconductor structure according to claim 12, however may be silent upon wherein the given capacitor is of a columnar structure, the given capacitor comprising a columnar first electrode, a fist dielectric layer and a second electrode sequentially surrounding the first electrode, and the first electrode being in electrical contact with a given one of the plurality of active pillars. The claimed DRAM capacitor structure is expected to be a conventional cylindrical design, commonly used in such devices at the time of the invention. As demonstrated in Figure 1 of Kim et al., analogous DRAM capacitors connected to similar vertical pillar transistors employ this standard cylindrical capacitor structure. It would have been obvious to one of ordinary skill in the art to modify the capacitor of Harada to incorporate this conventional cylindrical structure, as taught by Kim et al. This is because applying a known technique (the conventional cylindrical capacitor structure) to a known device (the DRAM capacitor in Harada) to achieve predictable results (e.g., standard DRAM performance) is considered obvious to one of ordinary skill in the art, as established by KSR International Co. v. Teleflex Inc.
CLAIM 15. Harada in view of Anderson in view of Cheng et al. disclose a semiconductor memory, at least comprising the semiconductor structure according to claim 1 (See Regarding claim 1).
CLAIM 20. Harada in view of Anderson in view of Cheng et al. disclose a semiconductor structure according to claim 20, wherein a top surface of the air gap is flush with or higher than a top surface of the word line (Harada in view of Anderson See regarding claim 7).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
9/9/2025
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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