Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 10, 2023 was filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: reference number 101 for a groove formed in the first substrate recited in paragraphs 32, 56, 158 and reference number 300 for a second semiconductor die stack body recited in paragraphs 32 and 115-116. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because the figures 1 and 7E-7H do not show a signal line labelled with reference number 41 and instead show a bracket labelled with reference number 41 around reference number 411 for a ground line and reference number 412 for a power line. The examiner notes that the terms signal line, power line, and ground line refer to distinct lines and that a signal line is understood to refer to a line carries data signals. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the signal line in the second substrate connected with the plurality of second conductive bumps recited in claim 2 on page 1 line 35 and page 2 line 1 must be shown or the feature canceled from the claim. Additionally, the plurality of second conductive bumps are formed in one side, along the first direction, of the second semiconductor die stack structure recited in claim 2 on page 1 lines 27-28 must be shown or the feature canceled from the claim. Further, the third conductive bump is formed on one side, close to the first substrate, of the second substrate, along the second direction recited in claim 2 on page 1 lines 1-2 must be shown or the feature canceled from the claim. Additionally, a plurality of second conductive bumps on one side, along the first direction, of the first die stack structure and the second die stack structure recited in claim 15 on page 5 lines 19-20 must be shown or the feature canceled from the claim. Further, a third conductive bump on one side, close to the first semiconductor die, of the second substrate recited in claim 15 on page 5 lines 22-23 must be shown or the feature canceled from the claim. The examiner notes that the plurality of second conductive bumps are shown in figures 1, -2, 4 7D-7H formed along a second direction and the third conductive bump is shown in 1, -2, 4 7F-7H formed along a first direction. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities: the specification abbreviates Through Silicon Via as TVS in paragraph 33. The abbreviation for Through Silicon Via is understood to be TSV.
Appropriate correction is required.
Claim Objections
Claim 14 is objected to because of the following informalities: claim 14 contains the following typographical error, claim 14 recites “ a second wireless communication portion,” on page line 26, this is understood to be the second wireless communication portion. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “ wherein the second semiconductor die stack structure comprises a first die stack structure located on the first semiconductor die and a second die stack structure located on the first die stack structure,” on page 1 lines 8-10 and the limitation “ the second semiconductor die stack structure comprises a plurality of second semiconductor dies stacked in sequence along a first direction,” on page 1 lines 10-12. These limitations render the claim indefinite because it is unclear whether the plurality of second semiconductor dies refers to semiconductor dies in the first die stack structure and the second die stack structure or whether the plurality of second semiconductor dies refers to additional semiconductor dies. The examiner notes the reading independent claim 1 together with claim 4 suggests the plurality of second semiconductor dies refers to semiconductor dies in the first die stack structure and the second die stack structure. Thus, for examination purposes, the plurality of second semiconductor dies will be interpreted as referring to semiconductor dies in the first die stack structure and the second die stack structure.
Claims 2-13 are also rejected for containing the same limitations because claims 2-13 depend from independent claim 1.
Claim 2 recites the limitation “ The semiconductor package structure of claim 1, wherein,” on page 1 line 25 and the limitation “ the semiconductor package structure further comprises,” on page 1 line 30. These limitations render claim 2 indefinite because it is unclear what structure of the semiconductor package structure is being defined through the use of two introductory phrases. For examination purposes, claim 2 will be interpretated as having the introductory phrase the semiconductor package structure of claim 1, further comprising.
Claims 8-9 and 11-13 are also rejected for containing the same limitations because claims 8-9 and 11-13 depend from claim 2.
Claim 11 recites the limitation “the signal line comprises a ground line and a power line,” on page 3 line 25. This limitation renders the claim indefinite because it is unclear how a signal line can include a ground line and a power line. The examiner notes that the terms signal line, power line, and ground line refer to distinct lines and that a signal line is understood to refer to a line carries data signals. For examination purposes, the semiconductor package structure will be interpreted as having a ground line and a power line.
Claim 14 recites the limitation “a plurality of second semiconductor dies stacked in sequence along a first direction,” on page 4 lines 18-19 and the limitation “a plurality of second semiconductor dies stacked in sequence along a first direction,” on page 4 lines 31-32. These limitations render the claim indefinite because it is unclear how many plurality of second semiconductor dies are recited. Thus, for examination purposes, claim 14 will be interpreted as including two pluralities of second semiconductor dies.
Claim 15 is also rejected for containing the same limitations because claim 15 depends from claim 14.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Okutsu et al. (US 2021/0143129) in view Pagani (US 2013/0241025).
Regarding Claim 1:
Okutsu discloses a semiconductor package structure, comprising:
a first semiconductor die (memory substrate, See fig. 8, ref. no. 10 and paragraph 34. The examiner notes that the memory substrate is a silicon substrate with circuits formed thereon.), wherein a first wireless communication portion (non-contact communication circuits, See fig. 8, ref. no. 11 and paragraph 34) is formed in the first semiconductor die; and
a second semiconductor die stack structure (memory unit, See fig. 8, ref. no. 20 and paragraph 35), wherein the second semiconductor die stack structure comprises a first die stack structure (plurality of memory chips, See fig. 8, ref. no. 21 and paragraphs 35-36) located on the first semiconductor die, the second semiconductor die stack structure comprises a plurality of second semiconductor dies (plurality of memory chips, See fig. 8, ref. no. 21 and paragraphs 35-36) stacked in sequence along a first direction (stacking direction D, See fig. 8), a second wireless communication portion (non-contact communication circuits, See fig. 8, ref. no. 121 and paragraph 36) formed in one side of the first die stack structure, along a second direction, of the first die stack structure, the first direction is a direction parallel to a plane of the first semiconductor die (the stacking direction D is parallel to a plane of the memory substrate, See fig. 8), and the second direction is a direction perpendicular to the plane of the first semiconductor die (the non-contact communications circuits in the memory substrate and the non-contact communications circuits in the memory chips communicate in the vertical direction, See fig. 8, ref. nos. 11, 121),
wherein the first wireless communication portion in the first semiconductor die is correspondingly disposed with the second wireless communication portion in the first die stack structure (the non-contact communications circuits in the memory substrate are aligned with the non-contact communications circuits in the memory chips, See fig. 8, ref. nos. 11, 121).
Okutsu does not disclose a second die stack structure located on the first die stack structure, a third wireless communication portion formed in the other side, a fourth wireless communication portion is formed in one side, opposite to the first die stack structure, of the second die stack structure, and the third wireless communication portion in the first die stack structure is correspondingly disposed with the fourth wireless communication portion in the second die stack structure.
Pagani discloses a second die stack structure located on the first die stack structure (two stacks of integrated circuits having front sides and back sides in contact, See fig. 3-25, ref. no. 302 and paragraphs 124-125), a third wireless communication portion are formed in the other side (communication pads formed on the back side of integrated circuits in the two stacks of integrated circuits, See fig. 3-25, ref. nos. 302, 350e-350h, 352s and paragraphs 124-125), a fourth wireless communication portion is formed in one side, opposite to the first die stack structure, of the second die stack structure (communication pads formed on the front side integrated circuit in the two stacks of integrated circuits, See fig. 3-25, ref. nos. 302, 350a-350d, 352s and paragraphs 124-125), and the third wireless communication portion in the first die stack structure is correspondingly disposed with the fourth wireless communication portion in the second die stack structure (the communication pads on the back side of one of the stacks of integrated circuits are aligned with the communication pads on the front side of the other of the stacks of integrated circuits, See fig. 8, ref. nos. 11, 121).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okutsu a second die stack structure located on the first die stack structure, a third wireless communication portion formed in the other side, a fourth wireless communication portion is formed in one side, opposite to the first die stack structure, of the second die stack structure, and the third wireless communication portion in the first die stack structure is correspondingly disposed with the fourth wireless communication portion in the second die stack structure as taught by Pagani in order to reduce routing to additional memory units at the PCB level. (See Pagani paragraph 121).
Regarding Claim 4:
The above stated combination of Okutsu and Pagani discloses the second wireless communication portion comprises a plurality of second sub-portions (a non-contact communication circuit for each of four memory chips, See Okutsu fig. 8, ref. no. 121 and paragraph 36), the third wireless communication portion comprises a plurality of third sub-portions (a communication pad on the back side of each of the four integrated circuits in the two stacks of integrated circuits, See Pagani fig. 3-25, ref. nos. 302, 350e-350h, 352s and paragraphs 124-125), and the fourth wireless communication portion comprises a plurality of fourth sub-portions (a communication pad on the front side of each of the four integrated circuits in the two stacks of integrated circuits, See Pagani fig. 3-25, ref. nos. 302, 350e-350h, 352s and paragraphs 124-125), at least one second sub-portion and at least one third sub-portion are comprised in each of second semiconductor dies in the first die stack structure (a communication pad on the front side and back side of each of the four integrated circuits in the two stacks of integrated circuits, See Pagani fig. 3-25, ref. nos. 302, 350e-350h, 352s, paragraphs 95, and 124-125), and at least one fourth sub-portion is comprised in each of second semiconductor dies in the second die stack structure (a communication pad on the front side of each of the four integrated circuits in the two stacks of integrated circuits, See Pagani fig. 3-25, ref. nos. 302, 350e-350h, 352s, paragraphs 95, and 124-125).
Regarding Claim 5:
Pagani discloses the second semiconductor die stack structure comprises N first die stack structures stacked along the second direction, wherein N is an integer greater than or equal to 1 (two stacks of integrated circuits having front sides and back sides in contact, See fig. 3-25, ref. no. 302 and paragraphs 124-125).
Regarding Claim 10:
The above stated combination of Okutsu and Pagani discloses above stated semiconductor package structure. Okutsu further discloses a plurality of Through Silicon Vias (TSVs) (through electrodes, See fig. 8, ref. no. 22 and paragraphs 37-38) penetrating, along the first direction, the second semiconductor dies.
The above stated combination of Okutsu and Pagani does not disclose a plurality of fourth conductive bumps located between two adjacent second semiconductor dies and connected with the TSVs correspondingly.
Pagani discloses a solder bumps located between two adjacent integrated circuits that include through silicon via (See fig. 3-27, ref. no. 353t, paragraphs 4 and 127).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package structure of Okutsu and Pagani to include a solder bumps located between two adjacent memory chip that include through silicon via as taught by Pagani in order to establish a reliable electrical and mechanical coupling. (See Pagani paragraph 4).
Regarding Claim 14:
Okutsu discloses a method for manufacturing a semiconductor package structure, comprising:
forming a first die stack structure (forming and arranging a memory unit with memory chips, See figs. 3, 6, ref. no. 20, 21, paragraphs 45-46 and 50-51), wherein the first die stack structure comprises a plurality of second semiconductor dies stacked in sequence along a first direction (memory chips are arranged over the memory substrate in the stacking direction D, See figs. 6, 8, ref. no. 20, and paragraphs 50-51);
forming a second wireless communication portion in one side of the first die stack structure (forming a memory unit with memory chips having non-contact communication circuits, See figs. 3, 6, ref. no. 20, 21 121, paragraphs 36, 45-46);
forming a first semiconductor die (a memory substrate is formed for connecting a memory unit to the memory substate, See fig. 8, ref. nos. 10, 20, and paragraphs 51-52);
forming a first wireless communication portion in the first semiconductor die (non-contact communication circuits are formed in the memory substate, See fig. 8, ref. nos. 10, 11 and paragraph 34);
placing a surface, on which a second wireless communication portion is formed, of the first die stack structure on the first semiconductor die (arranging a memory unit with memory chips on the memory substate, See figs. 3, 6, ref. nos. 10, 20, 21, paragraphs 45-46 and 50-51);
wherein the first direction is a direction parallel to a plane of the first semiconductor die (the stacking direction D is parallel to a plane of the memory substrate, See fig. 8), and the second direction is a direction perpendicular to the plane of the first semiconductor die (the non-contact communications circuits in the memory substrate and the non-contact communications circuits in the memory chips communicate in the vertical direction, See fig. 8, ref. nos. 11, 121),
wherein the first wireless communication portion in the first semiconductor die is correspondingly disposed with the second wireless communication portion in the first die stack structure (the non-contact communications circuits in the memory substrate are aligned with the non-contact communications circuits in the memory chips, See fig. 8, ref. nos. 11, 121).
Okutsu does not disclose forming a third wireless communication portion in the other side along the second direction of the first die stack structure, forming a second die stack structure, the second die stack structure comprising a plurality of second semiconductor dies stacked in sequence along the first direction, forming a fourth wireless communication portion in one side, along the second direction, of the second die stack structure, and placing a side surface, on which the fourth wireless communication portion is formed, of the second die stack structure on the first die stack structure, and the third wireless communication portion in the first die stack structure is correspondingly disposed with the fourth wireless communication portion in the second die stack structure.
Pagani discloses forming a third wireless communication portion in the other side along the second direction of the first die stack structure (combining the integrated circuits with communication mechanism, See figs. 3-15, 3-16, ref. nos. 302a, 350a, and paragraphs 114-115), forming a second die stack structure (stacking the integrated circuits, See figs. 3-18, ref. nos. 302a, 302b, fig. 3-25 and paragraph 117), the second die stack structure comprising a plurality of second semiconductor dies stacked in sequence along the first direction (stack of integrated circuits, See fig. 3-25, ref. no. 302 and paragraphs 124-125), forming a fourth wireless communication portion in one side, along the second direction, of the second die stack structure (combining the integrated circuits with communication mechanism, See figs. 3-15, 3-16, ref. nos. 302a, 350a, and paragraphs 114-115), and placing a side surface, on which the fourth wireless communication portion is formed, of the second die stack structure on the first die stack structure (two stacks of integrated circuits having front sides and back sides in contact, See fig. 3-25, ref. no. 302 and paragraphs 124-125), and the third wireless communication portion in the first die stack structure is correspondingly disposed with the fourth wireless communication portion in the second die stack structure (two stacks of integrated circuits having front sides and back sides in contact, See fig. 3-25, ref. no. 302 and paragraphs 124-125).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okutsu to include forming a third wireless communication portion in the other side along the second direction of the first die stack structure, forming a second die stack structure, the second die stack structure comprising a plurality of second semiconductor dies stacked in sequence along the first direction, forming a fourth wireless communication portion in one side, along the second direction, of the second die stack structure, and placing a side surface, on which the fourth wireless communication portion is formed, of the second die stack structure on the first die stack structure, and the third wireless communication portion in the first die stack structure is correspondingly disposed with the fourth wireless communication portion in the second die stack structure as taught by Pagani in order to reduce routing to additional memory units at the PCB level. (See Pagani paragraph 121).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Okutsu et al. (US 2021/0143129) in view Pagani (US 2013/0241025) further in view of Nakano (US 10,217,726).
Regarding Claim 6:
The above stated combination of Okutsu and Pagani discloses the above state semiconductor package structure. Okutsu further discloses the second semiconductor die stack structure comprises a Dynamic Random Access Memory (DRAM) die (the memory chips are DRAM chips, See paragraph 32).
The above stated combination of Okutsu and Pagani does not disclose the first semiconductor die comprises a logic die.
Nakano discloses a substrate including logic die (See fig. 1A, ref. no. 110 and col. 2 lines 47-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package structure of Okutsu and Pagani to include a logic die as taught by Nakano in order improve latency by processing information closer to the DRAM chips.
Regarding Claim 7:
The above stated combination of Okutsu and Pagani discloses the above stated semiconductor package structure.
The above stated combination of Okutsu and Pagani does not disclose an adhesive film located between the first semiconductor die and the second semiconductor die stack structure. The examiner notes that Okutsu discloses a mount portion located between the memory substrate and the memory unit, however, Okutsu is silent as to the materials used for the mount portion. (See fig. 8, ref. no. 60 and paragraph 33)
Nakano discloses an adhesive film for attaching a die to a substrate (See fig. 1, ref. nos. 110, 120a, 140, col. 3 lines 52-67, and col. 4 lines 1-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package structure of Okutsu and Pagani to include using an adhesive film located between the memory substrate and the memory unit as taught by Nakano since it has been held that the selection of a known material on the basis of its suitability for its intended use is a matter of obvious design choice. See In re Leshin, 125 USPQ 416 (CCPA 1960).
Allowable Subject Matter
Claims 2-3, 8-9, 11, and 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The disclosures and illustrations of Okutsu and/or Pagani as discussed above fail to teach or suggest the limitations of claims 2, 8-9, and 11 because Okutsu does not teach a plurality of second conductive bumps are formed in one side, along the first direction, of the second semiconductor die stack structure, and a second substrate, wherein a signal line in the second substrate is connected with the plurality of second conductive bumps, a third conductive bump is formed on one side, close to the first substrate, of the second substrate, along the second direction, and the second substrate is connected with the first substrate through the third conductive bump. Additionally, Pagani does not teach plurality of second conductive bumps are formed in one side, along the first direction, of the second semiconductor die stack structure, and a second substrate, wherein a signal line in the second substrate is connected with the plurality of second conductive bumps, a third conductive bump is formed on one side, close to the first substrate, of the second substrate, along the second direction, and the second substrate is connected with the first substrate through the third conductive bump. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Okutsu and/or Pagani to teach and/or suggest the limitations of claims 2, 8-9, and 11. Therefore, claims 2, 8-9, and 11include allowable subject matter.
The disclosures and illustrations of Okutsu and/or Pagani as discussed above fail to teach or suggest the limitations of claims 3 because Okutsu does not teach first sub-portions of the plurality of first sub-portions are disposed along a third direction in the first semiconductor die, wherein the third direction is a direction parallel to the plane of the first semiconductor die and forms an included angle with the first direction, and the included angle is greater than 25° and less than 65°. Additionally, Pagani does not teach first sub-portions of the plurality of first sub-portions are disposed along a third direction in the first semiconductor die, wherein the third direction is a direction parallel to the plane of the first semiconductor die and forms an included angle with the first direction, and the included angle is greater than 25° and less than 65°. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Okutsu and/or Pagani to teach and/or suggest the limitations of claim 3. Therefore, claim 3 includes allowable subject matter.
The disclosures and illustrations of Okutsu and/or Pagani as discussed above fail to teach or suggest the limitations of claims 15 because Okutsu does not teach forming a plurality of second conductive bumps on one side, along the first direction, of the first die stack structure and the second die stack structure; providing a second substrate after forming the second die stack structure, wherein a signal line in the second substrate is connected with the plurality of second conductive bumps. Additionally, Pagani does not teach forming a plurality of second conductive bumps on one side, along the first direction, of the first die stack structure and the second die stack structure; providing a second substrate after forming the second die stack structure, wherein a signal line in the second substrate is connected with the plurality of second conductive bumps. Further, the prior art also fails to provide other relevant disclosures which are properly combinable with Okutsu and/or Pagani to teach and/or suggest the limitations of claim 15. Therefore, claim 15 includes allowable subject matter.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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