DETAILED ACTION
Election/Restrictions
A restriction requirement was mailed on 12/3/25.
Applicant’s election without traverse of Group I (method claims 1-16 and newly added claims 19-20) in the reply filed on 1/17/26 is acknowledged. Claims 17-18 are withdrawn.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method of forming 3D DRAM having capacitor surrounding horizontal silicon pillars
Claim Objections
Claims 2-16 and 19-20 are objected to because certain terms lack proper antecedent basis and for minor issues such as lacking proper capitalization or inconsistent use of commas/semicolons. The following changes should be made:
1. A method … each column of silicon pillar structures comprises a plurality of silicon pillars… the plurality of silicon pillars in the plurality of columns of silicon pillar structures are distributed in a plurality of layers[[;]], and…
2. The method for manufacturing [[a]] the semiconductor structure of claim 1, wherein the forming [[a]] the plurality of columns …removing remaining first sacrificial layers and remaining second sacrificial layers located on the second area
3. The method for manufacturing [[a]] the semiconductor structure of claim 2, comprising: after the forming the stack structure on the substrate and before the forming [[a]] the plurality of columns…
4. The method for manufacturing [[a]] the semiconductor structure of claim 3…
5. The method for manufacturing [[a]] the semiconductor structure of claim 4, wherein the forming [[a]] the second sacrificial layer…
6. The method for manufacturing [[a]] the semiconductor structure of claim 5…
7. The method for manufacturing [[a]] the semiconductor structure of claim 6…
8. The method for manufacturing [[a]] the semiconductor structure of claim 7…
9. The method for manufacturing [[a]] the semiconductor structure of claim 1, wherein the forming [[a]] the capacitor structure…
10. The method for manufacturing [[a]] the semiconductor structure of claim 9…
11. The method for manufacturing [[a]] the semiconductor structure of claim 10…
12. The method for manufacturing [[a]] the semiconductor structure of claim 11…
13. The method for manufacturing [[a]] the semiconductor structure of claim 11…
14. The method for manufacturing [[a]] the semiconductor structure of claim 13, further comprising: after the forming the active pillar on the silicon layer located on the first area by [[a]] the plasma doping process…
15. The method for manufacturing [[a]] the semiconductor structure of claim 1, wherein the forming [[a]] the stack structure on the substrate comprises: forming initial silicon layers and first initial sacrificial layers stacked alternately on the substrate, wherein the first initial sacrificial layers are formed by an epitaxy
16. The method for manufacturing [[a]] the semiconductor structure of claim 10…
19. The method for manufacturing [[a]] the semiconductor structure of claim 1…
20. The method for manufacturing [[a]] the semiconductor structure of claim 1…
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-16 and 19-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claim 1 recites:
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate comprising a first area and a second area connected to the first area;
forming a stack structure on the substrate;
forming a plurality of columns of silicon pillar structures and support structures in the stack structure located on the second area,
wherein
the plurality of columns of silicon pillar structures are arranged at intervals in a first direction,
each column of silicon pillar structures comprises a plurality of silicon pillars that are arranged at intervals and are parallel to the substrate, and
the plurality of silicon pillars in the plurality of columns of silicon pillar structures are distributed in a plurality of layers; and
the support structure is configured to connect any adjacent silicon pillars; and
forming a capacitor structure surrounding each of the silicon pillars.
The metes and bounds of the claimed limitation can not be determined for the following reasons:
First, it is unclear how the claimed “silicon pillar structures” in the “columns of silicon pillar structures” differs from the claimed “silicon pillars that are arranged at intervals…” There appears to be no difference at all between them, although they are claimed with different terms and described in different figures with different element numbers 30 and 31.
Second, the number and overall structure of the “support structure” or “support structures” is unclear because the claim at times refers to a single “support structure” and at times refers to plural “support structures”. Furthermore, the limitation “the support structure is configured to connect any adjacent silicon pillars” could imply a single, interconnected support that touches all silicon pillars in the device, but it is unclear if there may be multiple supports that in aggregate touch all silicon pillar in the device, and it is unclear if there may be multiple supports that in aggregate only touch some silicon pillars.
Third, the limitation “the support structure is configured to connect any adjacent silicon pillars” together with the limitation “each column of silicon pillar structures comprises a plurality of silicon pillars that are arranged at intervals and are parallel to the substrate”, along with the first and second issues described above, makes it unclear if the “support structure” needs to only connect “any” adjacent pillars in a single column, or if it needs to connect “any” adjacent pillars in different columns.
Lastly, the limitation “forming a capacitor structure surrounding each of the silicon pillars” is unclear as to whether the capacitor structure needs to surround each of the silicon pillars only in a given column, or if it needs to surround each of the silicon pillars in the whole device. Additionally, this is unclear given the teachings of the specification, wherein in Fig. 3 all silicon layers 23 are in the stack structure 20, and said silicon layers 23 are later converted to silicon pillars 30 or 31, but in Fig. 31 when capacitor structures 31 are formed on the top and bottom of some 31s but not on the top of the top 31. Since Fig. 30 makes it clear that the capacitor structures are formed on the sidewalls of each 31, in combination, Figs. 30-31 show that the capacitor structures surround the silicon pillars 31 in the bottom two layers but do not fully surround the silicon pillars 31 in the top layer. Because the claim requires “each” silicon pillar to be surrounded, is unclear if this refers to all silicon pillars in the whole device, or if it refers only to silicon pillars in certain levels (e.g. only in all levels except the topmost level; or if it could be e.g. only in a single level). It is further unclear if it could refer to only a subset of all pillars in a single level, e.g. a subset of pillars that is on the right side of a device in top view, but that is not on the left side.
Claims 1-16 and 19-20 depend from claim 1 and inherit its deficiencies.
Claim 2 recites:
2. The method for manufacturing a semiconductor structure of claim 1, wherein the forming a plurality of columns of silicon pillar structures and support structures in the stack structure located on the second area comprises:
etching part of the stack structure to form a plurality of first trenches arranged at intervals in the first direction,
wherein the stack structure is divided into a plurality of columns of strips by the plurality of first trenches, and each column of strip comprises silicon layers and first sacrificial layers stacked alternately,
wherein a length direction of the first trenches is perpendicular to the first direction;
forming a second sacrificial layer in each of the first trenches;
etching part of the second sacrificial layer to form a plurality of second trenches in the second sacrificial layer,
wherein the second trenches expose part of a top surface of the substrate; and
removing part of a first sacrificial layer to form a plurality of third trenches arranged at intervals in each of the first sacrificial layers,
wherein the third trenches are communicated with the second trenches to form a filling area;
forming the support structures in the filling area, wherein the support structure comprises a plurality of support pillars arranged in a rectangular array,
wherein each of the support pillars is configured to connect adjacent silicon pillars; and
removing remaining first sacrificial layers and remaining second sacrificial layer located on the second area to form the plurality of columns of silicon pillar structures.
The metes and bounds of the claimed limitation can not be determined for the following reasons:
First, both instances of “arranged at intervals” in claim 2 lack proper antecedent basis for “intervals”, and it is unclear if one or both of the instances of “intervals” in claim 2 needs to refers to the same “intervals” as is recited in claim 1.
Second, the limitation “wherein each of the support pillars is configured to connect adjacent silicon pillars” is unclear because it refers to plural “support pillars” needing to connect adjacent silicon pillars, whereas claim 1 already recites a similar limitation that refers to “support structure” (that comprises support pillars). It is unclear what the limitation of claim 2 requires that the limitation in claim 1 already does not require.
Finally, the limitation “removing remaining first sacrificial layers and remaining second sacrificial layer located on the second area to form the plurality of columns of silicon pillar structures” is unclear as how the result of “to form the plurality of columns of silicon pillar structures” results from the cause (“removing remaining first sacrificial layers and remaining sacrificial layers…”). The claim is not removing silicon material from a silicon layer to result in a pattern of silicon pillars, from which the cause would logically imply the result. Rather, it removes a non-silicon material, which does not actually change the silicon itself, and somehow “forms” silicon pillars in the process. Because the limitation’s cause does not directly relate to the “result”, it is unclear.
Claims 3-8 depend from claim 2 and inherit its deficiencies.
Claim 4 recites: “… wherein the plurality of first protrusions are arranged at intervals in the first direction…” The metes and bounds of the claimed limitation can not be determined for the following reasons: the instance of “arranged at intervals” in claim 4 lack proper antecedent basis for “intervals”, and it is unclear if the instance of “intervals” in claim 4 needs to refers to the same “intervals” as is recited in claim 1 and/or in claim 2.
Claims 5-8 depend from claim 4 and inherit its deficiencies.
Claim 6 recites: “… wherein the second mask pattern comprises a plurality of second protrusions arranged at intervals and … wherein the plurality of second protrusions are arranged at intervals in the second direction …” The metes and bounds of the claimed limitation can not be determined for the following reasons: the two instances of “arranged at intervals” in claim 6 lack proper antecedent basis for “intervals”, and it is unclear if one or both of the instances of “intervals” in claim 4 need to refers to the same “intervals” as is recited in claim 1, claim 2, and/or claim 4.
Claims 7-8 depend from claim 6 and inherit its deficiencies.
Claim 9 recites “… wherein there is a first gap between any adjacent second electrode layers, and the dielectric layer has a high dielectric constant.”
The metes and bounds of the claimed limitation can not be determined for the following reasons:
First, the claim equates a single “first gap” with space between plural “any adjacent second electrode layers”. It is unclear if a same spacing needs to exist between each pair of adjacent second electrode layers, or if merely a space between the various pairs of second electrode layers can exist but if its value of distance in the space could vary.
Second, the limitation “high dielectric constant” contains the term "high" that is a relative term that renders the claim indefinite. It is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “high” defines a target dielectric constant and implicitly requires a boundary below which one is not “high” any more. Neither the claims, nor the specification, defines this boundary. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and the claim is unclear.
Claims 10-16 depend from claim 9 and inherit its deficiencies.
Claim 20 recites “… both the dielectric layer and second electrode layer comprise a plurality of segmentations arranged at intervals in the second direction between the support structures.” The metes and bounds of the claimed limitation can not be determined for the following reasons: the instance of “arranged at intervals” in claim 20 lacks proper antecedent basis for “intervals”, and it is unclear if the instance of “intervals” in claim 20 needs to refers to the same “intervals” as is recited in claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 9, and 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2020/0212041 A1 (“Machkaoutsan”).
Machkaoutsan teaches, for example:
PNG
media_image1.png
417
494
media_image1.png
Greyscale
PNG
media_image2.png
358
521
media_image2.png
Greyscale
PNG
media_image3.png
515
766
media_image3.png
Greyscale
Machkaoutsan teaches:
1. A method for manufacturing a semiconductor structure (see e.g. the structure of Figs. 2-3), comprising:
providing a substrate (e.g. 404, see e.g. Fig. 4) comprising a first area (e.g. left side of device 400 as shown in Fig. 4) and a second area (e.g. right side of device 400 as shown in Fig. 4) connected to the first area;
forming a stack structure (e.g. “electrically conductive device layers 304” and “dielectric device layers 306”, or tiers 410, as shown in e.g. Figs. 3-4) on the substrate;
forming a plurality of columns of silicon pillar structures (e.g. comprising one or multiple of “transistor channels 310”; see e.g. para 28; their geometry of the “pillar” has not been claimed, and it is reasonable that some of the ring or partial-ring shapes described in para 29 read thereon) and support structures (the geometry of the “support structures”, which later in claim 1 is described as a single “structure”, has not been limited by the claim; it is reasonable to interpret it as e.g. comprising one or more of various parts of 306 in e.g. Fig. 2; in additional interpretation or in alternate interpretation, it also could be interpreted as parts of 1000 during processing, see e.g. Fig. 10) in the stack structure located on the second area,
wherein the plurality of columns of silicon pillar structures are arranged at intervals in a first direction (e.g. see 206 in Fig. 4), each column of silicon pillar structure comprises a plurality of silicon pillars that are arranged at intervals and are parallel to the substrate (see how 310 is parallel with each other in Fig. 2; and in Fig. 4 how the layers are all parallel with the top of 404), and the plurality of silicon pillars in the plurality of columns of silicon pillar structures are distributed in a plurality of layers (see Figs. 2 and 4); and the support structure is configured to connect any adjacent silicon pillars (see e.g. Fig. 2); and
forming a capacitor structure (comprising one or more of e.g. “capacitor node plate 312”, dielectric 318, and/or 304, see e.g. para 30 and Fig. 2) surrounding each of the silicon pillars (see e.g. Figs. 2-3, wherein at least 312 surrounds 310 laterally in a generally “ring” fashion, see e.g. para 29).
2. The method for manufacturing a semiconductor structure of claim 1, wherein the forming a plurality of columns of silicon pillar structures and support structures in the stack structure located on the second area comprises:
etching part of the stack structure to form a plurality of first trenches (see e.g. Figs. 7-8, wherein certain parts of 700, 702, and/or 800 could be interpreted as first trenches) arranged at intervals in the first direction,
wherein the stack structure is divided into a plurality of columns of strips by the plurality of first trenches, and each column of strip comprises silicon layers and first sacrificial layers stacked alternately (see e.g. Figs. 7-8),
wherein a length direction of the first trenches is perpendicular to the first direction (it is in the direction perpendicular to the top surface plane of the substrate, see e.g. Figs. 7-8);
forming a second sacrificial layer (e.g. 1000, see e.g. Fig. 10) in each of the first trenches;
etching part of the second sacrificial layer to form a plurality of second trenches in the second sacrificial layer, wherein the second trenches expose part of a top surface of the substrate (see e.g. Fig. 11); and
removing part of a first sacrificial layer to form a plurality of third trenches arranged at intervals in each of the first sacrificial layers (see e.g. Fig. 7, wherein certain parts of 700 or 702 could be interpreted as third trenches),
wherein the third trenches are communicated with the second trenches to form a filling area (see e.g. Figs. 7-8, wherein the certain parts that are first trenches and the other certain parts that are third trenches could connect and form overall trenches);
forming the support structures in the filling area, wherein the support structure comprises a plurality of support pillars arranged in a rectangular array (see e.g. Fig. 10, wherein 1000 is formed in the trenches),
wherein each of the support pillars is configured to connect adjacent silicon pillars (see e.g. Figs. 2 and Fig. 10); and
removing remaining first sacrificial layers and remaining second sacrificial layer (see e.g. Fig. 11) located on the second area to form the plurality of columns of silicon pillar structures.
9. The method for manufacturing a semiconductor structure of claim 1, wherein the forming a capacitor structure surrounding each of the silicon pillars comprises: forming sequentially a first electrode layer (e.g. 312, see e.g. para 30), a dielectric layer (see e.g. para 30), and a second electrode layer (e.g. 304, e.g. para 30) surrounding the silicon pillar on each of the silicon pillars exposed (see e.g. Fig. 3), wherein there is a first gap between any adjacent second electrode layers (see e.g. Fig. 3), and the dielectric layer has a high dielectric constant (“high” is a relative term; see e.g. para 73, 84, etc.).
20. The method for manufacturing a semiconductor structure of claim 1, wherein the capacitor structure further comprises a dielectric layer and a second electrode layer surrounding the silicon pillar, both the dielectric layer and second electrode layer comprise a plurality of segmentations arranged at intervals in the second direction between the support structures (see e.g. Fig. 2).
Conclusion
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Kevin Parendo/Primary Examiner, Art Unit 2896