DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on Jun. 15th 2026 has been entered.
Response to Amendment
The amendment filed on May 23rd 2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments to the Claims 17-18 and Specification (Title) have overcome each and every objection previously set forth in the Final Office Action mailed on Feb. 25th 2026. Claims 12-18 are examined in this office action. Claims 1-11 and 19-20 are withdrawn from further consideration.
Claim Objections
Claims 19-20 are objected to because of the following informalities:
In claim 19, line 1, “The semiconductor method” should read “The method of manufacturing a semiconductor structure”.
In claim 20, line 1, “The semiconductor method” should read “The method of manufacturing a semiconductor structure”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 20180158773) in view of Kadoya et al. (US 20150294934).
Regarding claim 12, Hong teaches a semiconductor structure (Abstract), comprising:
a substrate (fig. 16, 110), comprising a core region (cell array region CELL; para. 0016) and a peripheral region (peripheral circuit region C/P; para. 0016), wherein a part of the substrate (110) of the core region (CELL) is provided with a first gate (word lines structure 120; para. 0028), a first doped region (cell active region 118; para. 0022) is provided in a part of the substrate (top part of 110) at two opposite sides (fig. 1, 118 in bit lines BL level are at up and down sides of word lines WL; para. 0061) of the first gate (120 in WL) of the core region (CELL), the substrate (110) exposes a top surface of the first doped region (118), and a dielectric layer (first insulating pattern 112A or device isolation layer 116; para. 0022, 0034) is provided on the top surface of the first doped region (top surface of 118); a part of the substrate (top middle part of 110) of the peripheral region (C/P) is provided with a second gate (gate with first and second gate electrode structures 242A and 242B; para. 0067), and a second doped region (peripheral circuit active region 119; para. 0090) is provided in a part of the substrate (top part of 110) at two opposite sides of the second gate (left and right sides of 242A, 242B) of the peripheral region (C/P);
a first conductive pillar (buried contacts 170 with landing pads 180; para. 0132), wherein the first conductive pillar (170, 180) is located in the first doped region (118) and protrudes from a surface of the substrate (top surface of 110), wherein the first doping region (118) located on one side of the first gate (120) serves as the source (118 at opposite sides 120 as source/drain regions; para. 0031) corresponding to the first gate (120), and the first doping region (118) located on the other side of the first gate (120) serves as the drain corresponding to the first gate (120); and
a second conductive pillar (conductive line 280; para. 0137), wherein the second conductive pillar (280) is located in the second doped region (119) and protrudes from the surface of the substrate (top surface of 110), and a depth of the second conductive pillar (depth of 280) into the second doped region (119) is less than a depth of the first conductive pillar (depth of 170, 180) into the first doped region (118).
Hong fails to explicitly teach the second doping region located on one side of the second gate serves as the source corresponding to the second gate, and the second doping region located on the other side of the second gate serves as the drain corresponding to the second gate; wherein the top surface of the first conductive pillar is flush with the top surface of the second conductive pillar.
However, Kadoya teaches the second doping region (Kadoya: fig. 1, third diffusion layers 150 on both sides as source/drain regions; para. 0039, similar to part of 119 of Hong) located on one side of the second gate (Kadoya: silicon layer 148 as gate electrode; para. 0039, similar to 242A and 242B of Hong) serves as the source corresponding to the second gate (Kadoya: 148), and the second doping region (Kadoya: 150) located on the other side of the second gate (Kadoya: 148) serves as the drain corresponding to the second gate (Kadoya: 148); wherein the top surface of the first conductive pillar (Kadoya: storage contact 122; para. 0035, similar to 170, 180 of Hong) is flush with the top surface of the second conductive pillar (Kadoya: contact plug 152; para. 0039, similar to 280 of Hong).
Kadoya and Hong are considered to be analogous to the claimed invention because they are in the same field of contacts structures in transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the second doping region serves as the source and drain and the top surface of the first conductive pillar is flush with the top surface of the second conductive pillar as taught by Kadoya.
Doing so would realize the source/drain regions essential for the transistor structure in the peripheral region and the contact structures having a same height top surface in both areas, which will be more convenient for forming layers above.
Regarding claim 17, Hong in view of Kadoya teaches the semiconductor structure according to claim 12, wherein a material of the first conductive pillar (Hong: fig. 16, material of 180 part) is the same (Hong: 180, 280 are formed at the same time; para. 0089) as that of the second conductive pillar (Hong: 280).
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Kadoya as applied to claim 12 above, and further in view of Lin et al. (US 20160005824).
Regarding claim 13, Hong in view of Kadoya teaches the semiconductor structure according to claim 12, further comprising:
a first metal silicide layer (Hong: fig. 16 and 11C, metal silicide layer 172; para. 0133), located between (Hong: vertical or diagonal direction) the first conductive pillar (Hong: 180 as part of 170 with 180) and the first doped region (Hong: 118).
Hong in view of Kadoya fails to teach a second metal silicide layer, located between the second conductive pillar and the second doped region.
However, Lin teaches a second metal silicide layer (Lin: fig. 3, metal-silicide layer 40; para. 0033), located between the second conductive pillar (Lin: contact structures 50; para. 0036, similar to 280 of Hong) and the second doped region (Lin: source/drain regions 210; para. 0036, similar to 119 of Hong).
Lin, Kadoya and Hong are considered to be analogous to the claimed invention because they are in the same field of contacts structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the second metal silicide layer as taught by Lin.
Doing so would realize a metal silicide layer to leverage a low resistance silicide contact with improved process stability (Lin: para. 0011).
Regarding claim 14, Hong in view of Kadoya and Lin teaches the semiconductor structure according to claim 13, wherein the second metal silicide layer (Lin: fig. 3, 40) is located on a bottom surface of the second conductive pillar (Lin: bottom surface of 50).
Regarding claim 15, Hong in view of Kadoya and Lin teaches the semiconductor structure according to claim 14, wherein the second metal silicide layer (Lin: fig. 3, 40) is further located on a side surface of the second conductive pillar (Lin: side surface of 50).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Kadoya and Lin as applied to claim 13 above, and further in view of Lin et al. (US 20160005824 as LIN2).
Regarding claim 16, Hong in view of Kadoya and Lin teaches the semiconductor structure according to claim 13 including the second metal silicide layer (Lin: fig. 3, 40).
Hong in view of Kadoya and Lin fails to explicitly teach the second metal silicide layer is further provided with fluoride ions therein.
However, LIN2 teaches the second metal silicide layer (LIN2: fig. 9, metal-silicide layer 225; para. 0040, similar to 40 of Lin) is further provided with fluoride ions (LIN2: fluorine in 225; para. 0040) therein.
LIN2, Lin, Kadoya and Hong are considered to be analogous to the claimed invention because they are in the same field of contacts structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the second metal silicide layer with fluoride ions therein as taught by LIN2.
Doing so would realize a contact interface with fluorine to increase in both the width and depth of the silicide to lower resistance (LIN2: para. 0011).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Kadoya and Lin as applied to claim 13 above, and further in view of Lee et al. (FR 2674373).
Regarding claim 18, Hong in view of Kadoya and Lin teaches the semiconductor structure according to claim 13, wherein the part of the second doping region (Hong: fig. 16 and 11C, top part of 119 and Kadoya: 150) in contact with the second conducting pillar (Hong: 280) and the second metal silicide layer (Lin: fig. 3, 40) and the part of the first doping region (Hong: top part of 118) in contact with the first conducting pillar (Hong: 170, 180) and the first metal silicide layer (Hong: 172).
Hong in view of Kadoya and Lin as applied to claim 13 above fails to explicitly teach the concentration of dopant ions in the part of the second doping region is greater than that in the part of the first doping region.
However, Lee teaches the concentration of dopant ions (Lee: fig. 5, concentration of impurities; Abstract) in the part of the second doping region (Lee: source and drain regions in the peripheral circuit; Abstract, similar to 150 of Kadoya) is greater than that in the part of the first doping region (Lee: source and drain regions in cells; para. Abstract, similar to 118 of Hong).
Lee Lin, Kadoya and Hong are considered to be analogous to the claimed invention because they are in the same field of contacts structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the concentration of dopant ions in the part of the second doping region is greater than that in the part of the first doping region as taught by Lee.
Doing so would realize the breakdown voltage characteristic of the junction of the transistor in the region with a set of cells is enhanced and the data inversion phenomenon and the problem of degradation in the refreshing characteristics due to the leakage current of the transistor in the peripheral circuit region are both prevented (Lee: Abstract).
Response to Arguments
Applicant’s arguments with respect to claims 12-18 of prior art rejections (35 USC 102/103) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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