Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, Figures 1-8 and 41 in the reply filed on 10/10/25 is acknowledged.
No claims are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/10/25.Claims 6, 8, 19-20 and 25-30 have been cancelled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) s 1-2, 4-5, 10-12 and 22 are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Choi et al. (US PGPub 2022/032025).
Claim 1: Choi teaches (Fig. 15A-15B) a semiconductor memory device comprising: a peripheral circuit structure (PS); and a cell structure (CS) on the peripheral circuit structure, wherein the cell structure comprises: a cell substrate (70,103) including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface, the cell substrate having a first conductivity type [0113]; a plurality of gate electrodes stacked on the first surface of the cell substrate; a channel structure (VS1/VS2) that intersects the plurality of gate electrodes (Ela,Elb) and is electrically connected to the cell substrate; a first impurity region (73, 75) in the cell substrate adjacent to the second surface, the first impurity region having a second conductivity type different from the first conductivity type [0089]; and a second impurity region (SCP1) that is in the cell substrate and is spaced apart from the first impurity region, the second impurity region having the first conductivity type with a higher impurity concentration than that of the cell substrate [0089, 0125].
Claim 2: Choi teaches (Fig. 15A-15B) the semiconductor memory device comprises a cell array region in which the channel structure is provided and an extension region (EXR) in which the plurality of gate electrodes are stacked in a stair shape, the first impurity region (73) is in a first portion of the cell substrate in the cell array region, and the second impurity region (SCP1) is around at least a portion of the first impurity region in a plan view.
Claim 4: Choi teaches (Fig. 15A-15B) the second impurity region is adjacent to the second surface of the cell substrate.
Claim 5: Choi teaches (Fig. 15A-15B) a source plate (CSL) [0089] extending on the first impurity region and the second surface of the cell substrate; and a source contact electrically connected to the source plate.
Claim 10: Choi teaches (Fig. 15A-15B) [0089, 0113] wherein the first conductivity type is a P-type and the second conductivity type is an N-type.
Claim 11: Choi teaches (Fig. 15A-15B) [0081] the channel structure comprises a semiconductor pattern that comprises a portion in the plurality of gate electrodes and is electrically connected to the cell substrate, and a data storage film interposed between the semiconductor pattern and the plurality of gate electrodes.
Claim 12: Choi teaches (Fig. 15A-15B) the semiconductor pattern protrudes into the first surface of the cell substrate and comprises an end portion in the cell substrate, and the data storage film is on the first surface of the cell substrate.
Claim 22: Choi teaches An electronic system comprising: a main substrate; a semiconductor memory device that is on the main substrate and comprises a peripheral circuit structure (PS) and a cell structure (CS) on the peripheral circuit structure; and a controller [0008] that is electrically connected to the semiconductor memory device and is on the main substrate, wherein the cell structure comprises: a cell substrate (70) including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface, the cell substrate having a first conductivity type (SCP1); a plurality of gate electrodes (El) stacked on the first surface of the cell substrate; a channel structure (VS1, VS2) that intersects the plurality of gate electrodes and is electrically connected to the cell substrate; a first impurity region (73, 75) in the cell substrate adjacent to the second surface of the cell substrate, the first impurity region having a second conductivity type different from the first conductivity type; and a second impurity region (SCP2) that is in the cell substrate and is spaced apart from the first impurity region, the second impurity region having the first conductivity type with a higher impurity concentration than that of the cell substrate [0089].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13, 15, 18, 21 and 24 are rejected under 35 U.S.C. 103 as being unpatentable Choi et al. (US PGPub 2022/032025).
Claim 13: Choi teaches (Fig. 15A-15B) a semiconductor memory device comprising (Fig. 15A-B) a peripheral circuit structure (PS) and a cell structure (CS) on the peripheral circuit structure, wherein the peripheral circuit structure comprises: a peripheral circuit board (10); a peripheral circuit element (PTR) on the peripheral circuit board; and a peripheral circuit interconnection structure (PS) electrically connected to the peripheral circuit element, and the cell structure comprises: a cell substrate having a first conductivity (SPC1) and including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface; a mold structure (60) comprising a plurality of gate electrodes stacked on the first surface of the cell substrate; a plurality of channel structures (VS1/VS2), each of which extends in a vertical direction that is not parallel to the first surface of the cell substrate, extends through the mold structure, and is electrically connected to the cell substrate; a bit line (BL) that is electrically connected to the channel structure and is between the peripheral circuit structure and the mold structure; a plurality of gate contacts (CCP/CL1) that are electrically connected to the plurality of gate electrodes, respectively and are on the mold structure; a cell interconnection structure that is electrically connected to the bit line and the plurality of gate contacts and contacts (41,43) the peripheral circuit interconnection structure; a first impurity region that has an second conductivity (SCP2), overlaps the plurality of channel structures in the vertical direction and is in the cell substrate adjacent to the second surface; and a second impurity region that has a first conductivity (75), is around at least a portion of the first impurity region in a plan view and is in the cell substrate, the second impurity region having a higher impurity concentration than that of the cell substrate. The conductivity types of the claim are the opposite of that taught by Choi but one of ordinary skill would be able to switch the conductivity types as is known in the art as long as the regions with the same type conductivity type regions are maintained.
Claim 15: Choi teaches (Fig. 15A-15B) the second impurity region comprises a line-shaped impurity region extending along a side surface of the first impurity region.
Claim 18: Choi teaches (Fig. 15A-15B) a source plate extending on the first impurity region and on the second surface of the cell substrate; and a source contact extending in the vertical direction and electrically connecting the input/output line structure to the source plate.
Claim 21: Choi teaches (Fig. 15A-15B) a contact plug that extends in the vertical direction and electrically connects the cell interconnection structure to the input/output line structure.
Claim 24: Choi teaches (Fig. 15A-15B) the first conductivity type is a P-type, and the second conductivity type is an N-type. The conductivity types of the claim are the opposite of that taught by Choi but one of ordinary skill would be able to switch the conductivity types as is known in the art as long as the regions with the same type conductivity type regions are maintained.
Allowable Subject Matter
Claims 3, 7, 9, 14, 16, 17 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. These dependent claims are not taught by the prior art of record as the read/erase functions do not align with the conductivity types and location of the impurity regions of the independent claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814