Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 9 is objected to because of the following informalities:
Claim 9 recites the limitation “the p-type well" in line 21. There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the p-type well” relates back to “a deep p-type well” in line 3.
For purpose of compact prosecution, “the p-type well” will be treated as if it were “the deep p-type well.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over HAN et al. (U.S. 2018/0082994 A1, hereinafter refer to HAN) in view of Chiu et a. (U.S. 2022/0157982 A1, hereinafter refer to Chiu).
Regarding Claim 1: HAN discloses a structure (see HAN, Fig.4 as shown below and ¶ [0002]) comprising:
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an n-type deep well (115 and 160) on a substrate (105 and portion of 110) (see HAN, Fig.4 as shown above);
a p-type deep well (110) over a lower portion of the n-type deep well (115 and 160) and horizontally between upper portions of the n-type deep well (115 and 160) (see HAN, Fig.4 as shown above);
a first n-type well (125) over the p-type deep well (110) (see HAN, Fig.4 as shown above);
a pair of p-type wells (135) over the p-type deep well (110) and adjacent opposite horizontal ends of the first n-type well (125), wherein the pair of p-type wells (135) have a higher doping concentration than the p-type deep well (110) (note: second well 135 formed by implanting p-type impurity into the collector region of the epitaxial layer 110, which means the impurity concentration of 135 is greater than the impurity concentration of 110) (see HAN, Fig.4 as shown above and ¶ [0047]);
a pair of third n-type wells (150) each within a respective one of the upper portions of the n- type deep well (115 and 160) and horizontally adjacent the p-type deep well (110), wherein the third n-type well (150) is horizontally distal to and decoupled from the p-type deep well (110) (see HAN, Fig.4 as shown above); and
a second pair of p-type wells (165) within a portion of the substrate (105 and portion of 110) horizontally adjacent the n- type deep well (115 and 160), wherein the second pair of p-type wells (165) are horizontally distal to the n-type deep well (115 and 160) (see HAN, Fig.4 as shown above).
HAN is silent upon explicitly disclosing wherein a pair of second n-type wells over the p-type deep well and each adjacent one of the pair of p-type wells, such that each p-type well is immediately horizontally between the first n-type well and one of the second n-type wells, wherein each p-type well includes a first sidewall contacting one of a pair of sidewalls of the first n-type well and a second sidewall contacting one of the second n-type wells, each second n-type well includes a first sidewall contacting the second sidewall of a respective one of each of the pair of p-type wells and the first n-type well, the pair of p-type wells and the pair of second n-type wells have a same height over the p-type deep well and each include a lower surface coplanar along an upper surface of the p-type deep well.
For support see Chiu, which teaches wherein a pair of second n-type wells (322/ first conductivity type is N-type) over the p-type deep well (332/ second conductivity type is P-type) and each adjacent one of the pair of p-type wells (325/ second conductivity type is P-type), such that each p-type well (325/ second conductivity type is P-type) is immediately horizontally between the first n-type well (322/ first conductivity type is N-type) and one of the second n-type wells (322/ first conductivity type is N-type), wherein each p-type well (325/ second conductivity type is P-type) includes a first sidewall contacting one of a pair of sidewalls of the first n-type well (322/ first conductivity type is N-type) and a second sidewall contacting one of the second n-type wells (322/ first conductivity type is N-type), each second n-type well (322/ first conductivity type is N-type) includes a first sidewall contacting the second sidewall of a respective one of each of the pair of p-type wells (325/ second conductivity type is P-type) and the first n-type well (322/ first conductivity type is N-type), the pair of p-type wells (325/ second conductivity type is P-type) and the pair of second n-type wells (322/ first conductivity type is N-type) have a same height over the p-type deep well (332/ second conductivity type is P-type) and each include a lower surface coplanar along an upper surface of the p-type deep well (332/ second conductivity type is P-type) (see Chiu, Fig.3 as shown below, ¶ [0002], ¶ [0042], ¶ [0045], and ¶ [0050]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of HAN and Chiu to enable a pair of second n-type wells over the p-type deep well and each adjacent one of the pair of p-type wells, such that each p-type well to be immediately horizontally between the first n-type well and one of the second n-type wells, wherein each p-type well to include a first sidewall contacting one of a pair of sidewalls of the first n-type well and a second sidewall contacting one of the second n-type wells, each second n-type well to include a first sidewall contacting the second sidewall of a respective one of each of the pair of p-type wells and the first n-type well, the pair of p-type wells and the pair of second n-type wells to have a same height over the p-type deep well and each to include a lower surface coplanar along an upper surface of the p-type deep well as taught by Chiu in order to obtain a high voltage device which can eliminate leakage current.
Regarding Claim 2: HAN as modified teaches a structure as set forth in claim 1 as above. The combination of HAN and Chiu further teaches wherein a P+ terminal (130) on the first n-type well (125), the P+ terminal (130) being coupled to an input/output (I/O) terminal, wherein the first n-type well (125) defines a floating well beneath the P+ terminal (130) (see HAN, Fig.4 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 4: HAN as modified teaches a structure as set forth in claim 2 as above. The combination of HAN and Chiu further teaches wherein a first N+ terminal (329/ first conductivity type is N-type) coupled to ground and on one of the pair of second n-type wells (322/ first conductivity type is N-type) and a second N+ terminal (329/ first conductivity type is N-type) coupled to a voltage supply and on the other of the pair of second n-type wells (322/ first conductivity type is N-type) (see Chiu, Fig.3 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 5: HAN as modified teaches a structure as set forth in claim 4 as above. The combination of HAN and Chiu further teaches wherein a current pathway between the I/O terminal and the first N+ terminal (329/ first conductivity type is N-type) defines a first semiconductor controlled rectifier (SCR), and a current pathway between the I/O terminal and the second N+ terminal (329/ first conductivity type is N-type) defines a second SCR, and the first n-type well (322/ first conductivity type is N-type) is shared between the first SCR and the second SCR (see Chiu, Fig.3 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 6: HAN as modified teaches a structure as set forth in claim 1 as above. The combination of HAN and Chiu further teaches wherein the first n-type well (125) and pair of p- type wells (135) define floating semiconductor regions within the structure (see HAN, Fig.4 as shown above).
Regarding Claim 7: HAN as modified teaches a structure as set forth in claim 1 as above. The combination of HAN and Chiu further teaches wherein a deep n-type well (333/ first conductivity type is N-type) below the deep p- type well (332/ second conductivity type is P-type), wherein the deep p-type (332/ second conductivity type is P-type) well vertically separates the deep n-type well (115 and 160) from the first n- type well (322/ first conductivity type is N-type), the pair of p-type wells (325/ second conductivity type is P-type), and the pair of second n-type wells (322/ first conductivity type is N-type) (see Chiu, Fig.3 as shown above, ¶ [0045], and ¶ [0050]).
Regarding Claim 8: HAN as modified teaches a structure as set forth in claim 7 as above. The combination of HAN and Chiu further teaches wherein the deep p-type well (332/ second conductivity type is P-type) and the deep n-type well (333/ first conductivity type is N-type) each define floating semiconductor regions within the structure (see Chiu, Fig.3 as shown above).
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over HAN et al. (U.S. 2018/0082994 A1, hereinafter refer to HAN) and Chiu et a. (U.S. 2022/0157982 A1, hereinafter refer to Chiu) as applied to claim 2 above, and further in view of Zeng et al. (U.S. 2021/0082905 A1, hereinafter refer to Zeng).
Regarding Claim 3: HAN as modified teaches a structure as applied to claim 2 above. The combination of HAN and Chiu is silent upon explicitly disclosing wherein a pair of trench isolation (TI) regions each partially recessed over a corresponding one of the pair of p-type wells, the first n-type well and one of the second n-type wells, wherein the P+ terminal is horizontally between the pair of isolation regions.
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For support see Zeng, which teaches wherein a pair of trench isolation (TI) regions (230-244) each partially recessed over a corresponding one of the pair of p-type wells (814b/814c), the first n-type well (224) and one of the second n-type wells (222 or 822), wherein the P+ terminal (818 or 820) is horizontally between the pair of isolation regions (230-244) (see Zeng, Fig.8A as shown below and ¶ [0006]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of HAN, Chiu, and Zeng to enable a pair of trench isolation (TI) regions each partially recessed over a corresponding one of the pair of p-type wells, the first n-type well and one of the second n-type wells, wherein the P+ terminal is horizontally between the pair of isolation regions as taught by Zeng in order to obtain a smaller ESD protection device with better clamping ability and lower on-resistance that can support bi-directional high voltage bias.
Claim(s) 9-10, 12-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et a. (U.S. 2022/0157982 A1, hereinafter refer to Chiu) in view of HAN et al. (U.S. 2018/0082994 A1, hereinafter refer to HAN).
Regarding Claim 9: Chiu discloses a structure (see Chiu, Fig.3 as shown above and ¶ [0002]) including:
an n-type deep well (333/ first conductivity type is N-type) on a substrate (321 and 334) (see Chiu, Fig.3 as shown above);
a deep p-type well (332/ second conductivity type is P-type) over a lower portion of the n-type deep well (333/ first conductivity type is N-type) and horizontally between upper portions of the n-type deep well (333/ first conductivity type is N-type) (see Chiu, Fig.3 as shown above);
a first semiconductor-controlled rectifier (SCR) over the deep p-type well (332/ second conductivity type is P-type) and the substrate (321 and 334), the first SCR including a first set of alternatingly doped wells to define a first N-P-N junction over the substrate (321 and 334), wherein the first set of alternatingly doped wells includes a first n- type well (322/ first conductivity type is N-type) within a floating well region, a second n-type well (322/ first conductivity type is N-type) coupled to ground, and a first p-type well (325/ second conductivity type is P-type) therebetween and the first p-type well (325/ second conductivity type is P-type) includes a first sidewall contacting one of a pair of sidewalls of the first n-type well (322/ first conductivity type is N-type) and a second sidewall (322/ first conductivity type is N-type) contacting one of the second n-type wells (see Chiu, Fig.3 as shown above);
a second SCR over the substrate (321 and 334), the second SCR including a second set of alternatingly doped wells to define a second N-P-N junction over the substrate (321 and 334), wherein the second set of alternatingly doped wells includes the first n-type well (322/ first conductivity type is N-type) within the floating well region, a third n- type well (322/ first conductivity type is N-type) coupled to a voltage supply, and a second p-type well (325/ second conductivity type is P-type) therebetween, such that the first n-type well (322/ first conductivity type is N-type) is shared between the first SCR and the second SCR and the second p-type well (325/ second conductivity type is P-type) includes a first sidewall contacting one of the pair of sidewalls of the first n-type well (322/ first conductivity type is N-type) and a second sidewall contacting one of the third n-type wells (322/ first conductivity type is N-type) (see Chiu, Fig.3 as shown above),
wherein the first p-type well (325/ second conductivity type is P-type) and the second p-type well (325/ second conductivity type is P-type) each have a higher doping concentration than the p-type deep well (332/ second conductivity type is P-type), and the first SCR and the second SCR have a same height over the p-type well (332/ second conductivity type is P-type) and each include a lower surface are coplanar along an upper surface of the p-type deep well (332/ second conductivity type is P-type) (see Chiu, Fig.3 as shown above).
Chiu is silent upon explicitly disclosing wherein a pair of third n-type wells each within a respective one of the upper portions of the n- type deep well and horizontally adjacent the p-type deep well, wherein the third n-type well is horizontally distal to and decoupled from the p-type deep well; and
a second pair of p-type wells within a portion of the substrate horizontally adjacent the n- type deep well, wherein the second pair of p-type wells are horizontally distal to the n-type deep well.
For support see HAN, which teaches wherein a pair of third n-type wells (150) each within a respective one of the upper portions of the n- type deep well (115 and 160) and horizontally adjacent the p-type deep well (110), wherein the third n-type well (150) is horizontally distal to and decoupled from the p-type deep well (110) (see HAN, Fig.4 as shown above and ¶ [0011]); and
a second pair of p-type wells (165) within a portion of the substrate (105 and portion of 110) horizontally adjacent the n- type deep well (115 and 160), wherein the second pair of p-type wells (165) are horizontally distal to the n-type deep well (115 and 160) (see HAN, Fig.4 as shown above and ¶ [0011]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chiu and HAN to enable Chiu high voltage device of a switching regulator/protection device to include a pair of third n-type wells each within a respective one of the upper portions of the n- type deep well and horizontally adjacent the p-type deep well, wherein the third n-type well is horizontally distal to and decoupled from the p-type deep well; and a second pair of p-type wells within a portion of the substrate horizontally adjacent the n- type deep well, wherein the second pair of p-type wells are horizontally distal to the n-type deep well as taught by HAN in order to obtain an ESD protection devices having relatively a low on resistance and a high second trigger current.
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 10: Chiu as modified teaches a structure as set forth in claim 9 as above. The combination of Chiu and HAN further teaches wherein a P+ terminal on the first n-type well, the P+ terminal (326/ second conductivity type is P-type) being coupled to an input/output (I/O) terminal (see Chiu, Fig.3 as shown above, ¶ [0042], and ¶ [0045]).
Regarding Claim 12: Chiu as modified teaches a structure as set forth in claim 10 as above. The combination of Chiu and HAN further teaches wherein the second n-type well (322/ first conductivity type is N-type) is coupled to ground through a first N+ terminal (329/ first conductivity type is N-type) over the second n-type well (322/ first conductivity type is N-type) (see Chiu, Fig.3 as shown above), and
wherein the third n-type well (150) is coupled to the voltage supply through a second N+ terminal (155) over the third n-type well (150) (see HAN, Fig.4 as shown above).
Regarding Claim 13: Chiu as modified teaches a structure as set forth in claim 9 as above. The combination of Chiu and HAN further teaches wherein the first p-type well (325/ second conductivity type is P-type) and the second p-type well (325/ second conductivity type is P-type) define floating semiconductor regions within the structure (see Chiu, Fig.3 as shown above).
Regarding Claim 14: Chiu as modified teaches a structure as set forth in claim 9 as above. The combination of Chiu and HAN further teaches wherein the deep p-type well (332) below the first SCR and the second SCR (see Chiu, Fig.3 as shown above); and
the deep n-type well (333) below the deep p-type well (332), wherein the deep p-type (332) well vertically separates the deep n-type well (333) from the first SCR and the second SCR (see Chiu, Fig.3 as shown above).
Regarding Claim 15: Chiu as modified teaches a structure as set forth in claim 14 as above. The combination of Chiu and HAN further teaches wherein the deep p-type well (332) and the deep n-type well (333) each define floating semiconductor regions within the structure (see Chiu, Fig.3 as shown above).
Regarding Claim 16: Chiu discloses a structure (see Chiu, Fig.3 as shown above and ¶ [0002]) comprising:
an n-type deep well (333/ first conductivity type is N-type) over a substrate (321 and 334) and having a scyphoidal geometry (see Chiu, Fig.3 as shown above);
a p-type deep well (332/ second conductivity type is P-type) over a lower portion of the n-type deep well (333/ first conductivity type is N-type) and horizontally between upper portions of the n-type deep well (333/ first conductivity type is N-type) (see Chiu, Fig.3 as shown above);
a first n-type well (322/ first conductivity type is N-type) over the p-type deep well (332/ second conductivity type is P-type) (see Chiu, Fig.3 as shown above);
a P+ terminal on the first n-type well (322/ first conductivity type is N-type) and coupled to an input/output (I/O) node (see Chiu, Fig.3 as shown above),
a pair of p-type wells (325/ second conductivity type is P-type) over the p-type deep well and adjacent opposite horizontal ends of the first n-type well (322/ first conductivity type is N-type), wherein the pair of p-type wells (325/ second conductivity type is P-type) have a higher doping concentration than the p-type deep well (332/ second conductivity type is P-type) (see Chiu, Fig.3 as shown above);
a pair of second n-type wells (322/ first conductivity type is N-type) over the p-type deep well (332/ second conductivity type is P-type) and each adjacent one of the pair of p-type wells (325/ second conductivity type is P-type), such that each p-type well (325/ second conductivity type is P-type) is immediately-horizontally between the first n-type well (322/ first conductivity type is N-type) and one of the second n-type wells (322/ first conductivity type is N-type), wherein each p-type well (325/ second conductivity type is P-type) includes a first sidewall contacting one of a pair of sidewalls of the first n-type well (322/ first conductivity type is N-type) and a second sidewall contacting one of the second n-type wells (322/ first conductivity type is N-type), each second n-type well (322/ first conductivity type is N-type) includes a first sidewall contacting the second sidewall of a respective one of each of the pair of p-type wells (325/ second conductivity type is P-type) and the first n-type well (322/ first conductivity type is N-type), the pair of p-type wells (325/ second conductivity type is P-type) and the pair of second n-type wells (322/ first conductivity type is N-type) have a same height over the p-type deep well (332/ second conductivity type is P-type) and each include a lower surface coplanar along an upper surface of the p-type deep well (332/ second conductivity type is P-type) (see Chiu, Fig.3 as shown above);
a first N+ terminal (329/ first conductivity type is N-type) on one of the pair of second n-type wells (322/ first conductivity type is N-type) and coupled to ground (see Chiu, Fig.3 as shown above); and
a second N+ terminal (329/ first conductivity type is N-type) on the other of the pair of second n-type wells (322/ first conductivity type is N-type) and coupled to a voltage supply (see Chiu, Fig.3 as shown above),
wherein the deep p-type well (332/ second conductivity type is P-type), the deep n-type well (333/ first conductivity type is N-type), the first n-type well (322/ first conductivity type is N-type), and the pair of p- type wells (325/ second conductivity type is P-type) each define floating semiconductor regions within the structure (see Chiu, Fig.3 as shown above).
Chiu is silent upon explicitly disclosing wherein a pair of third n-type well within a respective one of the upper portions of the n-type deep well and horizontally adjacent the p-type deep well, wherein the second pair of third n-type well is horizontally distal to and decoupled from the p-type deep well;
a second pair of p-type wells within a portion of the substrate horizontally adjacent the n- type deep well, wherein the second pair of p-type wells are horizontally distal to the n-type deep well.
For support see HAN which teaches wherein a pair of third n-type well (150) within a respective one of the upper portions of the n-type deep well (115 and 160) and horizontally adjacent the p-type deep well (110), wherein the second pair of third n-type well (150) is horizontally distal to and decoupled from the p-type deep well (110) (see HAN, Fig.4 as shown above and ¶ [0011]);
a second pair of p-type wells (165) within a portion of the substrate (105 and portion of 110) horizontally adjacent the n- type deep well (115 and 160), wherein the second pair of p-type wells are horizontally distal to the n-type deep well (115 and 160) (see HAN, Fig.4 as shown above and ¶ [0011]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chiu and HAN to enable Chiu high voltage device of a switching regulator/protection device to include pair of third n-type well within a respective one of the upper portions of the n-type deep well and horizontally adjacent the p-type deep well, wherein the second pair of third n-type well is horizontally distal to and decoupled from the p-type deep well and a second pair of p-type wells within a portion of the substrate horizontally adjacent the n- type deep well, wherein the second pair of p-type wells are horizontally distal to the n-type deep well as taught by HAN in order to obtain an ESD protection devices having relatively a low on resistance and a high second trigger current.
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 18: Chiu as modified teaches a structure as set forth in claim 16 as above. The combination of Chiu and HAN further teaches wherein a current pathway between the I/O terminal and the first N+ terminal (329/ first conductivity type is N-type) defines a first semiconductor controlled rectifier (SCR), and a current pathway between the I/O terminal and the second N+ terminal defines (329/ first conductivity type is N-type) a second SCR, and the first n-type well (322/ first conductivity type is N-type) is shared between the first SCR and the second SCR (see Chiu, Fig.3 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 19: Chiu as modified teaches a structure as set forth in claim 18 as above. The combination of Chiu and HAN further teaches wherein the first SCR and the second SCR are of opposite polarity during operation (see Chiu, Fig.3 as shown above).
Note: a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Regarding Claim 20: Chiu as modified teaches a structure as set forth in claim 16 as above. The combination of Chiu and HAN further teaches wherein the deep p-type well (332) vertically separates the deep n-type well (333) from the first n-type well (322), the pair of p-type wells (325), and the pair of second n-type wells (322) (see Chiu, Fig.3 as shown above).
Claim(s) 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et a. (U.S. 2022/0157982 A1, hereinafter refer to Chiu) and HAN et al. (U.S. 2018/0082994 A1, hereinafter refer to HAN) as applied to claims 10 and 16 above, and further in view of Zeng et al. (U.S. 2021/0082905 A1, hereinafter refer to Zeng).
Regarding Claim 11: Chiu as modified teaches a structure as applied to claim 10 above. The combination of Chiu and HAN is silent upon explicitly disclosing wherein a pair of trench isolation (TI) regions each partially recessed over a corresponding one of the first p-type well or the second p-type well, the first n-type well and one of the second n-type wells, wherein the P+ terminal is horizontally between the pair of isolation regions.
For support see Zeng, which teaches wherein a pair of trench isolation (TI) regions (230-244) each partially recessed over a corresponding one of the first p-type well (814b) or the second p-type well (814c), the first n-type well (224) and one of the second n-type wells (222 or 822), wherein the P+ terminal (818 or 820) is horizontally between the pair of isolation regions (230-244) (see Zeng, Fig.8A as shown above and ¶ [0006]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chiu, HAN, and Zeng to enable a pair of trench isolation (TI) regions each partially recessed over a corresponding one of the first p-type well or the second p-type well, the first n-type well and one of the second n-type wells, wherein the P+ terminal is horizontally between the pair of isolation regions as taught by Zeng in order to obtain a smaller ESD protection device with better clamping ability and lower on-resistance that can support bi-directional high voltage bias.
Regarding Claim 17: Chiu as modified teaches a structure as applied to claim 16 above. The combination of Chiu and HAN is silent upon explicitly disclosing wherein a pair of trench isolation (TI) regions each partially recessed over a corresponding one of the pair of p-type wells, the first n-type well and one of the second n-type wells, wherein the P+ terminal is horizontally between the pair of isolation regions.
For support see Zeng, which teaches wherein a pair of trench isolation (TI) regions (230-244) each partially recessed over a corresponding one of the pair of p-type wells (814b/814c), the first n-type well (224) and one of the second n-type wells (222 or 822), wherein the P+ terminal (818 or 820) is horizontally between the pair of isolation regions (230-244) (see Zeng, Fig.8A as shown above and ¶ [0006]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chiu, HAN, and Zeng to enable a pair of trench isolation (TI) regions each partially recessed over a corresponding one of the pair of p-type wells, the first n-type well and one of the second n-type wells, wherein the P+ terminal is horizontally between the pair of isolation regions as taught by Zeng in order to obtain a smaller ESD protection device with better clamping ability and lower on-resistance that can support bi-directional high voltage bias.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812