DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 05/18/2026, in which claims 1, 9, 16, 23 were amended, claims 7-8, 13-14, 20, 24 were cancelled, claims 25-26 were added, has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US Pub. 20210376155) in view of Huang et al. (US Pub. 20220028752).
Regarding claims 1 and 21, Chang et al. discloses in Fig. 17C, Fig. 21C, Fig. 23C, Fig. 26B-26C, Fig. 27B-27C, Fig. 28B-28C, Fig. 29B-29C a method comprising:
forming a transistor structure on a front side of the semiconductor substrate [50], wherein the transistor structure comprises a gate structure [100 and 102] and a source/drain region [92][Fig. 17C];
forming a front-side interconnect structure [120] over the transistor structure [Fig. 21C];
performing a thinning process on a back side of the semiconductor substrate [50] to reduce a thickness of the semiconductor substrate [50][Fig. 23C, paragraph [0084]];
forming a recess [128] that extends through the semiconductor substrate [50] to expose a back side of the source/drain region [92][Fig. 26C, paragraph [0093]];
forming a metal contact plug [130] in the recess [128], wherein the metal contact plug [130] extends through the semiconductor substrate [50] to contact the back side of the source/drain region [92][Fig. 27C, paragraph [0096]-[0097]]; and
forming a back-side interconnect structure [136] over the back side of the semiconductor substrate [50] and on the metal contact plug [130][Fig. 29C].
Chang et al. fails to disclose
implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate;
wherein the gate structure and the source/drain region are physically separated from the etch stop region;
performing the thinning process on the back side of the semiconductor substrate to reduce a thickness of the etch stop region, wherein the thinning process is slowed by the etch stop region, wherein a portion of the etch stop region remains after performing the thinning process;
the recess that extends through the portion of the etch stop region; and
the metal contact plug extends through the portion of the etch stop region;
forming the back-side interconnect structure over a back side of the portion of the etch stop region;
wherein a thickness of the etch stop region after performing the thinning process is smaller than a thickness of the semiconductor substrate after performing the thinning process.
Huang et al. discloses in Fig. 1, Fig. 2, Fig. 16A-C, Fig. 21A-21C, Fig. 23A-23C, Fig. 24A-24C, Fig. 27A-27C
implanting impurities in a semiconductor substrate [50] to form an etch stop region [50B] within the semiconductor substrate [50][Fig. 2, paragraph [0020] “a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX)”];
wherein the gate structure [102 and 100] and the source/drain region [92] are physically separated from the etch stop region [50B][Fig. 1, Fig. 16A-16C];
wherein the thinning process is slowed by the etch stop region [50B], wherein a portion of the etch stop region [50B] remains after performing the thinning process [Fig. 23A-23C, paragraph [0064]]; and
forming the back-side interconnect structure [136] over the back side of the semiconductor substrate [50] and over a back side of the portion of the etch stop region [50B][Fig. 24A-24C, Fig. 27A-27C, paragraph [0065]-[0070]];
wherein a thickness of the etch stop region [50B] after performing the thinning process is smaller than a thickness of the semiconductor substrate [50] after performing the thinning process [Fig. 23A-23C];
Huang et al. further suggests in Fig. 24C
the recess that extends through the portion of the etch stop region [50B][Fig. 24C][Fig. 24C]; and
a contact plug [145 and 91] extends through the portion of the etch stop region [50B][Fig. 2C];
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Thus, incorporating a portion of the etch stop region [50B] remains after performing the thinning process disclosed by Huang et al. into the method of Chang et al., and forming recess 128 and metal contact plug 130 as taught by Chang et al. would result to “the recess that extends through the portion of the etch stop region”; and “the metal contact plug extends through the portion of the etch stop region.”
Notes, “etch stop” and “wherein the thinning process is slowed by the etch stop region” are intended purposes of an implanted region. An implanted region 50B is capable of performing the intended function of an etch stop region and slow the thinning process. “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”. MPEP2112.01. Further, per MPEP 2131, “[t]he elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Huang et al. into the method of Chang et al. to include implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; wherein the gate structure and the source/drain region are physically separated from the etch stop region; wherein the thinning process is slowed by the etch stop region, wherein a portion of the etch stop region remains after performing the thinning process; the recess that extends through the portion of the etch stop region; and the metal contact plug extends through the portion of the etch stop region; forming the back-side interconnect structure over a back side of the portion of the etch stop region; wherein a thickness of the etch stop region after performing the thinning process is smaller than a thickness of the semiconductor substrate after performing the thinning process.
The ordinary artisan would have been motivated to modify Chang et al. in the above manner for the purpose of providing semiconductor-on-insulator (SOI) substrate including a buried oxide (BOX) layer for better controlling thinning process to remove the bulk silicon layer [paragraphs [0020], [0064] of Huang et al.].
Chang et al. and Huang et al. fails to explicitly disclose
performing the thinning process on the back side of the semiconductor substrate to reduce a thickness of the etch stop region.
However, Chang et al. discloses in Fig. 23C, paragraph [0084] that a thickness T1 of the substrate 50 over the gate structure after the thinning process is adjustable. Huang discloses a thickness of the substrate 50 over the gate structure after the thinning process including a thickness of the etch stop region. Thus, it would be obvious that a thickness of the etch stop region remaining after the thinning process can be reduced.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chang et al. and Huang et al. to include performing the thinning process on the back side of the semiconductor substrate to reduce a thickness of the etch stop region. The ordinary artisan would have been motivated to modify Chang et al. and Huang et al. in the above manner for the purpose of ensuring bulk silicon layer being removed completely and obtaining desired thickness of the substrate over the gate structure after the thinning process.
Regarding claim 5, Huang et al. discloses the claimed etch stop region. Thus, the etch stop region disclosed by Huang et al. would have the claimed property of “a removal rate of the thinning process within the etch stop region is between 55% and 90% of a removal rate for the semiconductor substrate outside of the etch stop region.” “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).” MPEP 2112.01
In addition, Applicant has not provided any criticality of the claimed range. Thus, it would have been obvious to modify Chang et al. and Huang et al. to provide the claimed range for at least the purpose of optimization and routine experimentation to obtain desired etch selectivity. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claim 6, Huang et al. discloses in Fig. 1, Fig. 2 wherein the etch stop region [50B] is separated from a front surface of the semiconductor substrate [50] by a distance.
Chang et al. and Huang al. fails to disclose
the distance is in a range of 40 nm to 60 nm.
However, Applicant has not provided any criticality of the claimed range. Thus, it would have been obvious to modify Chang et al. and Huang et al. to provide the claimed range for at least the purpose of optimization and routine experimentation to obtain optimal distance of a doped region for its intended purpose. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US Pub. 20210376155) in view of Huang et al. (US Pub. 20220028752) as applied to claim 1 above and in view of Mouli (US Pub. 20070012970).
Regarding claim 2, Chang et al. and Huang et al. fails to disclose
wherein the impurities comprise boron, aluminum, gallium, indium, or titanium
Mouli discloses in Fig. 4, paragraph [0039] wherein the impurities [114 and 116] comprise boron, aluminum, gallium, indium, or titanium [boron].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Mouli into the method of Chang et al. and Huang et al. to include wherein the impurities comprise boron. The ordinary artisan would have been motivated to modify Chang et al. and Huang et al. in the above manner for the purpose of providing a boron-rich BOX to achieve certain characteristics of the devices [paragraph [0039] of Mouli].
Regarding claim 3, Chang et al. and Huang et al. fails to disclose
wherein the impurities are implanted using a dose in a range of 5×1014 cm−2 to 2×1015 cm−2.
Mouli discloses in Fig. 4, paragraph [0039] wherein the impurities are implanted using a dose in a range of 5×1014 cm−2 to 2×1015 cm−2 [“Oxygen (or nitrogen) is implanted 114 into the substrate 110 (typically about 1015 to about 1018 ions cm-2)”] “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Mouli into the method of Chang et al. and Huang et al. to include wherein the impurities are implanted using a dose in a range of 5×1014 cm−2 to 2×1015 cm−2. The ordinary artisan would have been motivated to modify Chang et al. and Huang et al. in the above manner for the purpose of providing suitable concentration of the impurities of BOX layer [paragraph [0039] of Mouli].
In addition, Applicant has not provided any criticality of the claimed range. Thus, it would have been obvious to modify Chang et al. and Huang et al. and Mouli to provide the claimed range for at least the purpose of optimization and routine experimentation to obtain a doped region having desired characteristic. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US Pub. 20210376155) in view of Huang et al. (US Pub. 20220028752) as applied to claim 1 above and further in view of Nishiguchi (US Pat. 4908693).
Regarding claim 4, Chang et al. and Huang et al. fails to disclose
wherein the etch stop region has a concentration of impurities in a range of 5×1018 cm−3 to 1020 cm−3.
Nishiguchi discloses in column 2, lines 34-38 wherein the etch stop region has a concentration of impurities in a range of 5×1018 cm−3 to 1020 cm−3 [7x1019 ions/cm3]. “In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Nishiguchi into the method of Chang et al. and Huang et al. to include wherein the etch stop region has a concentration of impurities in a range of 5×1018 cm−3 to 1020 cm−3. The ordinary artisan would have been motivated to modify Chang et al. and Huang et al. in the above manner for the purpose of providing suitable concentration of the impurities of an etch stop layer.
In addition, Applicant has not provided any criticality of the claimed range. Thus, it would have been obvious to modify Chang et al. and Huang et al. and Nishiguchi to provide the claimed range for at least the purpose of optimization and routine experimentation to obtain a doped region having desired characteristic. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claims 9-12, 22-23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. (US Pat. 9082698) in view of Chang et al. (US Pub. 20210376155) and Huang et al. (US Pub. 20220028752).
Regarding claims 9, 22-23, 25, Joshi et al. discloses in Fig. 2C-2F a method comprising:
performing an implantation process to form an implanted region [110A and 112A] of a substrate [102], wherein the implanted region [110A and 112A] is separated from a top surface [top surface of 102] of the substrate [102] by a first distance [Fig. 2C-2D];
forming an isolation region [108] over the implanted region [110A and 112A] of the substrate [102], wherein the implanted region [110A and 112A] is separated from a top surface of the isolation region [108] by a second distance, wherein a first portion [112A] of the implanted region [110A and 112A] is closer to the top surface of the substrate [102] than a bottom surface of the isolation region [108];
forming a first transistor over the isolation region [108] and the implanted region [110A and 112A] of the substrate, wherein the first transistor comprises a source/drain region [126] that is separated from the implanted region [112A and 110A];
wherein the first distance is different than the second distance [Fig. 2D];
wherein the implanted region [110A and 112A] is vertically separated from a top side of the source/drain region of the first transistor by a third distance [Fig. 2F];
wherein a second portion [portion of 110A under the STI 108] of the implanted region [110A and 112A] is farther from the top surface [top surface of fin 106] of the substrate [102] than the bottom surface of the isolation region [108].
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Joshi et al. fails to disclose
forming a first interconnect structure over a first side of the first transistor, wherein the first interconnect structure is electrically coupled to the first transistor;
thinning the substrate, wherein the implanted region is exposed after the thinning of the substrate; and
forming a second interconnect structure over a second side of the first transistor, wherein the second interconnect structure is electrically coupled to the first transistor.
Chang et al. discloses in Fig. 21C, Fig. 23C
forming a first interconnect structure [120] over a first side of the first transistor, wherein the first interconnect structure [120] is electrically coupled to the first transistor [Fig. 21C];
thinning the substrate [50][Fig. 23C]; and
forming a second interconnect structure [136] over a second side of the first transistor, wherein the second interconnect structure [136] is electrically coupled to the first transistor [Fig. 29C].
Chang et al. discloses in Fig. 23C, paragraph [0084] that a thickness T1 of the substrate 50 over the gate structure after the thinning process is adjustable. Thus, it would be obvious that the implanted region can be exposed after the thinning of the substrate to obtain desired thickness T1 of the substrate 50 over the gate structure after the thinning process.
For further providing support that an implanted region can be exposed after the thinning of the substrate, Huang et al. is cited.
Huang discloses in Fig. 21A-21C, Fig. 23A-23C, Fig. 24A-24C, Fig. 27A-27C
forming a first interconnect structure [114, 112 and 120] over a first side of the first transistor, wherein the first interconnect structure [114, 112 and 120] is electrically coupled to the first transistor [Fig. 21A-21C, paragraph [0049]-[0055]];
thinning the substrate [50], wherein the implanted region [50B] is exposed after the thinning of the substrate [50][Fig. 23A-23C, paragraph [0064]]; and
forming a second interconnect structure [136] over a second side of the first transistor, wherein the second interconnect structure [136] is electrically coupled to the first transistor [Fig. 24A-24C, Fig. 27A-27C, paragraph [0065]-[0070]].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chang et al. and Huang et al. into the method of Joshi et al. to include forming a first interconnect structure over a first side of the first transistor, wherein the first interconnect structure is electrically coupled to the first transistor; thinning the substrate, wherein the implanted region is exposed after the thinning of the substrate; and forming a second interconnect structure over a second side of the first transistor, wherein the second interconnect structure is electrically coupled to the first transistor. The ordinary artisan would have been motivated to modify Joshi et al. in the above manner for the purpose of providing suitable subsequent manufacturing processes to form a semiconductor die having front-side interconnect structure and backside power rails so that a gate density of the transistor and/or interconnect density of the front-side interconnect structure may be increased, wider power rails can be implemented to reduce resistance and increase efficiency of power delivery to the device [paragraph [0100] of Chuang et al.; paragraph [0050], [0064], [0067] of Huang et al.].
Regarding claim 10, Joshi et al. discloses in columns 6-7
wherein the implantation process comprises an energy in a range of 20 keV to 40 keV [1-100 keV].
Additionally, Applicant has not provided any criticality of the claimed range.
Thus, it would have been obvious to modify Chang et al., Joshi et al. and Huang et al. to provide wherein the implantation process comprises an energy in a range of 20 keV to 40 keV for at least the purpose of optimization and routine experimentation to obtain a doped region at desired location. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Regarding claims 11-12, Joshi et al. discloses in Fig. 2D, column 7, lines 1-27
wherein the implanted region [110A and 112A] has a height;
wherein the height of the implanted region [110A and 112A] corresponds to an impurity concentration in a range of 5×1018 cm−3 to 1020cm-3 [1e17-1e19 ion/cm3].
Joshi et al. and Chang et al. and Huang et al. fails to disclose
wherein the height is in a range of 100 nm to 300 nm.
However, Applicant has not provided any criticality of the claimed range. Thus, it would have been obvious to modify Joshi et al., Chang et al. and Huang et al. to provide the claimed ranges for at least the purpose of optimization and routine experimentation to obtain optimal height of a doped region for its intended purpose. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. (US Pat. 9082698) in view of Chang et al. (US Pub. 20210376155) and Huang et al. (US Pub. 20220028752) as applied to claim 9 above and in view of Mouli (US Pub. 20070012970).
Regarding claim 15, Joshi et al. fails to disclose
wherein the implantation process comprises implanting oxygen ions.
Huang discloses in paragraph [0020]
wherein the implantation process comprises implanting oxygen ions [“a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX)”];
Mouli discloses in Fig. 4, paragraph [0039]
wherein the implantation process comprises implanting oxygen ions.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of HUang et al. and Mouli into the method of Joshi et al. to include wherein the implantation process comprises implanting oxygen ions. The ordinary artisan would have been motivated to modify Joshi et al. in the above manner for the purpose of providing a boron-rich BOX to achieve certain characteristics of the devices [paragraph [0039] of Mouli].
Claims 16-19 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. (US Pat. 9082698) in view of Chang et al. (US Pub. 20210376155).
Regarding claims 16-18 and 26, Joshi et al. discloses in Fig. 2B-2F a device comprising:
a semiconductor fin [106] comprising an implanted region [110A and 112A], wherein the implanted region [110A and 112A] of the semiconductor fin [106] is within the semiconductor fin [106] and at a first side [bottom side] of the semiconductor fin [106], wherein the implanted region [110A and 112A] has a first concentration of implanted impurities, wherein a height of the implanted region [110A and 112A] of the semiconductor fin [106] is less than a height of the semiconductor fin [106], wherein a second side [top side] of the semiconductor fin [106] has a second concentration of the implanted impurities that is less than the first concentration;
an isolation region [108] surrounding the semiconductor fin [108], wherein surfaces of the isolation region [108] and the implanted region [110A and 112A] of the semiconductor fin [106] are level;
a source/drain region [126] on the second side [top side] of the semiconductor fin [106];
wherein surfaces of the isolation region [108] and the implanted region [110A and 112A] are level to within 5 nm [surfaces of 110A and 108 are coplanar][Fig. 2D];
wherein at the first side [top side] of the semiconductor fin [106], a width of the implanted region [110A and 112A] is a width of the semiconductor fin [106][Fig. 2D].
Joshi et al. fails to disclose
a via penetrating the semiconductor fin to electrically contact the source/drain region, wherein the via penetrates the implanted region;
a first interconnect structure over the first side of the semiconductor fin, wherein the first interconnect structure is electrically connected to the via; and
a second interconnect structure over the second side of the semiconductor fin.
Chang et al. discloses in Fig. 30B-30C
a via [130] penetrating the semiconductor fin [50/66] to electrically contact the source/drain region [92];
a first interconnect structure [120] over the first side [top side] of the semiconductor fin [66], wherein the first interconnect structure [120] is electrically connected to the via [130]; and
a second interconnect structure [136] over the second side [bottom side] of the semiconductor fin [66].
Joshi et al. discloses a semiconductor fin [106] comprising the implanted region [110A and 112A] at a bottom of the semiconductor fin. Chang et al. discloses the via [130] penetrating the bottom of the semiconductor fin to the top of the semiconductor fin [50/66]. Thus, incorporating the via disclosed by Chang et al. into the device of Joshi et al. would result to the via penetrates the implanted region.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chang et al. into the method of Joshi et al. to include a via penetrating the semiconductor fin to electrically contact the source/drain region, wherein the via penetrates the implanted region; a first interconnect structure over the first side of the semiconductor fin, wherein the first interconnect structure is electrically connected to the via; and a second interconnect structure over the second side of the semiconductor fin. The ordinary artisan would have been motivated to modify Joshi et al. in the above manner for the purpose of providing a semiconductor die having front-side interconnect structure and backside power rails so that a gate density of the transistor and/or interconnect density of the front-side interconnect structure may be increased, wider power rails can be implemented to reduce resistance and increase efficiency of power delivery to the device [paragraph [0100] of Chuang et al.].
Regarding claim 19, Joshi et al. discloses in column 7, lines 1-27
wherein the first concentration is greater than 5×1018 cm−2 and less than 1020 cm−2 [1e17-1e19 ion/cm3].
In addition, Applicant has not provided any criticality of the claimed range. Thus, it would have been obvious to modify Joshi et al. to provide the claimed range for at least the purpose of optimization and routine experimentation to obtain a doped region having desired characteristic. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Response to Arguments
Applicant’s arguments with respect to claims 1-6, 9-12, 15-19, 22-23, 25-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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