DETAILED ACTION
This Office action responds to Applicant’s election filed on 07/20/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Election/Restriction
The Applicant’s response on 07/20/2025 in reply to the restriction/election requirements mailed on 06/18/2025 has been entered. Applicant’s election without traverse of Invention I/Group I (claims 1-19), drawn to a semiconductor device package, is acknowledged. Claims 20, drawn to a method for manufacturing of a semiconductor device package, is withdrawn, by corresponding to a non-elected invention. Applicant’s election without traverse of Species 5, corresponding to figs. 2A and 4A and drawn to claims 1-2, 5-9, 11-14, and 17-19, is acknowledged. Examiner disagrees. Claims 9, and its dependent claim 11 are withdrawn, as being drawn to a nonelected species (for example, Species 1, corresponding to fig. 2B, and 3A, where the conductive pole 207 is between the redistribution layer 106 and the interconnection layer 202).
Claims 3-4, 9-11, and 15-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/20/2025.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDSes have been considered.
Specification
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the dies and the multiple stacked dies recited in the claim must be shown the drawings or the feature(s) canceled from the claim(s).
Also, the drawings do not show that “each of the dies is electrically connected to the substrate through a lead on a respective one of the third pads in the package structure” (a limitation from claim 13). Therefore, the element of this limitation recited in the claim 13 must be shown the drawings or the feature(s) canceled from the claim(s).
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Duplicate Claims Warning
Applicant is advised that should claim 12 be found allowable, claim 13 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. Claims 12, 14, 17, and 19, respectively are substantial duplicates of claims 1, 2, 5, and 7. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of copending Application No. 18/163802 (US2023/0395441).
Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the co-pending application, and is a broader statement of the invention as currently claimed in the co-pending application. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 1 of co-pending application patent 18/163802 anticipates claim 1 of the instant invention
Claims 1-2 of co-pending application patent 8/163802 anticipate claim 2 of the instant invention.
Claims 1-3 of co-pending application patent 18/163802 anticipate claim 3 of the instant invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 13 is rejected under 35 U.S.C. 112(b) as being indefinite.
The claim is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint regard as the invention.
Claim 13 (and any dependents) recites the limitation "multiple stacked dies”. The claim does not define what the multiple stacked dies is. It is not clear from this claim how these dies are stacked. The dies can be stacked on a substrate in a single layer or the dies can be stacked on each other in multiple layers. For the purposes of examination to apply prior art, this was treated as the dies are stacked on a substrate in a single layer.
Claim 13 (and any dependents) also recites the limitation "each of the dies comprises a semiconductor functional structure and a package structure located on the semiconductor functional structure”. It is not clear from this claim what is the meaning of the word die. A die can be a semiconductor chip or a portion cut from a semiconductor wafer. From the limitation of "multiple stacked dies”, it looks that the die is a semiconductor chip. However, from the limitation "each of the dies comprises a semiconductor functional structure and a package structure located on the semiconductor functional structure”, it looks that the die is a portion cut from a semiconductor wafer containing a semiconductor functional structure and a package structure. Examiner requests a change in the wording of these limitations. For the purposes of examination to apply prior art, this was treated as the die equivalent to a semiconductor chip.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Initially, and with respect to claims 1 and 12 note that a limitation in a claim with respect to the manner in which a claimed device is intended to be used does not differentiate the claimed device from a prior-art device, if the prior-art device teaches all structural limitations in the claim and the limitations are found to be inherent in the prior-art device. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See Hewlett-Packard Co. v. Bausch & Lomb Inc. and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a device claim, and not the patentability of its functions (909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)). As stated in Best,
Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Note that the applicant has burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Claims 1, 12, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by or, in alternative, under 35 U.S.C. 103 as obvious over by Jo (US 2017/0062367).
Regarding claims 1 and 12, Jo shows (see, e.g., Jo: figs. 2-4) all aspects of the instant invention including a semiconductor functional structure 20 and package structure, comprising:
An isolation layer 120 with multiple vias 125
wherein:
The isolation layer 120 covers a surface of on interconnection layer 110
Each of the vias 125 exposes a respective part of the interconnection layer 110
The interconnection layer 110 is arranged on a surface of the semiconductor functional structure 20
N first pads 110, wherein each of the N first pads 110 is formed by a respective part of the interconnection layer 110 exposed by a corresponding one of the vias 125, where N is a positive integer greater than 1 (see, e.g., Jo: fig. 2)
N Redistribution Layers (RDLs) 130, wherein each of the RDLs 130 covers the isolation layer 120 and is electrically connected to a respective one of the N first pads 110
A first insulating layer 140, which is formed on the RDLs 130, and exposes a part area of each of the RLDs 130
wherein:
The exposed part areas of at least some of the RDLs 130 comprises second pads 135c1 and third pads 135c2
A center point of each of the second pads 135c1 has a same offset direction and same offset distance with respect to a center point of a corresponding one of the first pads 110 (this is the case for two corresponding RDLs (that is, N = 2), having one second pad 135c1 in the PA1 area, and the other second pad 135c1 in the PA2 area)
The first pads 110 and the second pads 135c1 are used for testing when the semiconductor functional structure 20 is at different running speeds respectively (MPEP 2114.II: Apparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim)
The third pads 135c2 are used for performing function interaction corresponding to content tested by the second pads 135c1 (MPEP 2114.II: Apparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim)
Regarding claim 13, Jo shows (see, e.g., Jo: figs. 2-4) that the semiconductor device of claim 12 comprises:
A substrate 10
A multiple stacked dies 20 (see, e.g., Jo: par. [0005])
wherein:
Each of the dies 20 comprises a semiconductor functional structure 20 and a package structure located on the semiconductor functional structure 20
Each of the dies 20 is electrically connected to the substrate 10 through a lead on a respective one of the third pads 135c2 in the package structure (see, e.g., Jo: fig. 1)
Claims 2, 5-6, and 14, 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jo in view of Shin (US 2019/0221535).
Regarding claims 2 and 14, Jo shows (see, e.g., Jo: figs. 2-4) most aspects of the instant invention including a package structure, comprising N first pads 110, second pads 135c1, and third pads 135c2. Jo also shows that:
The N first pads 110 are arranged in parallel along a first direction
At least some of the second pads 135c1 and corresponding ones of the third pads 135c2 arranged in parallel along a second direction
wherein:
The second direction is perpendicular to the first direction.
Jo, however, fails (see, e.g., Jo: figs. 2-4) to show that the N first pads 110 are arranged near a first edge of the semiconductor functional structure 20. Moreover, Jo shows that the N first pads 110 are arranged near the center of the semiconductor functional structure 20.
Shin, in a similar device to Jo, shows (see, e.g., Shin: figs. 6E and 7, and also par. [0028]) that the N first pads 143v are arranged near a first edge of the semiconductor functional structure 10b. Shin also teaches (see, e.g., Shin: figs. 6E and 7, and also par. [0028]) that, after the process of forming of the redistribution pads 143, the test process is performed before the process of forming of the protective layer 151 and the passivation layer 153. (see, e.g., Shin: par. [0065]). Shin also shows (see, e.g., Shin: figs. 6E and 7, and also par. [0028]) that the probe pins of a probe card can be placed in contact with the redistribution pads 143, and test signals can be applied to the redistribution pads 143 through the probe pins to perform the test process (see, e.g., Shin: par. [0066]). According to these examples, Shin further shows (see, e.g., Shin: figs. 6E and 7, and also par. [0028]) that it is possible to secure integrity or consistency of values measured in the test process performed on the test structures 103 because the connection structure 113a or 113b and the redistribution pad 143 connected to the test structure 103 on the edge region 23a or 23b constitute an integrated structure (see, e.g., Shin: par. [0066]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the N pads arranged near a first edge of the semiconductor functional structure of Shin in device of Jo, to secure integrity or consistency of values measured in the test process performed on the test structures, because the redistribution pads connected to the test structure on the edge region constitute an integrated structure.
Regarding claims 5 and 17, Jo shows (see, e.g., Jo: figs. 2-4) most aspects of the instant invention including a package structure, comprising N first pads 110, second pads 135c1, and third pads 135c2. Jo also shows that:
Some of the first pads 110 are arranged in parallel along a first direction
Some of the second pads 135c1 and corresponding ones of the third pads 135c2 arranged in parallel along a second direction
wherein:
The second direction is perpendicular to the first direction.
Jo, however, fails (see, e.g., Jo: figs. 2-4) to show that the N first pads 110 are arranged near a first edge of the semiconductor functional structure 20. Moreover, Jo shows that the N first pads 110 are arranged near the center of the semiconductor functional structure 20.
Shin, in a similar device to Jo, shows (see, e.g., Shin: figs. 5, 6E and 7-8, and also par. [0028]) that the N first pads 143v are arranged near a first edge of the semiconductor functional structure 10b. Shin also teaches (see, e.g., Shin: figs. 5, 6E and 7-8, and also par. [0028]) that, after the process of forming of the redistribution pads 143, the test process is performed before the process of forming of the protective layer 151 and the passivation layer 153. (see, e.g., Shin: par. [0065]). Shin also shows (see, e.g., Shin: figs. 5, 6E and 7-8, and also par. [0028]) that the probe pins of a probe card can be placed in contact with the redistribution pads 143, and test signals can be applied to the redistribution pads 143 through the probe pins to perform the test process (see, e.g., Shin: par. [0066]). According to these examples, Shin further shows (see, e.g., Shin: figs. 5, 6E and 7-8, and also par. [0028]) that it is possible to secure integrity or consistency of values measured in the test process performed on the test structures 103 because the connection structure 113a or 113b and the redistribution pad 143 connected to the test structure 103 on the edge region 23a or 23b constitute an integrated structure (see, e.g., Shin: par. [0066]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the N pads arranged near a first edge of the semiconductor functional structure of Shin in device of Jo, to secure integrity or consistency of values measured in the test process performed on the test structure, because the redistribution pads connected to the test structure on the edge region constitute an integrated structure.
Jo in view of Shin further shows (see, e.g., Shin: figs. 5, 6E and 7-8) that a rest of the first pads 141 are arranged near a second edge of the semiconductor functional structure along the second direction, where the first edge and the second edge are two opposite edges of the semiconductor functional structure 10a/10b.
Jo in view of Shin shows (see, e.g., Jo: figs. 2-4) that the second pads and the third pards corresponding to the rest of the first pads 110 are arranged in parallel along the first direction.
Regarding claims 6 and 18, Jo in view of Shin shows (see, e.g., Jo: figs. 2-4) that:
An orthographic projection of the center point of each of the second pads 135c1 on a plane where the interconnection layer 110 is located is offset by a second distance in a third direction with respect to the center point of the corresponding first pad 110
An included angle between the third direction and the first direction is 45 degrees or 135 degrees
Claims 7 and 19 is rejected under 35 U.S.C. 103 as being unpatentable over Jo in view of Shin in further view of Huang (US 2021/0343632).
Regarding claims 7 and 19, Jo in view of Shin shows (see, e.g., Jo: figs. 2-4) that:
Shapes of the first pads 110 comprises a long-strip shape
Shapes of orthographic projections of some of the RDLs 130 on the plane where the interconnection layer 110 is located comprise a Z-shape
Jo in view of Shin fails (see, e.g., Jo: figs. 2-4) to shows that shapes of orthographic projections of some of the RDLs 130 on the plane where the interconnection layer 110 is located comprise a L-shape. However, it is noted that the specification fails to provide teachings about the criticality of having the first isolation structure with shapes of orthographic projections of some of the RDLs 130 on the plane where the interconnection layer 110 is located comprise a L-shape or a Z-shape, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the shape of orthographic projections of some of the RDLs 130 on the plane where the interconnection layer 110 is located, disclosed by Jo in view of Shin as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular L-shape or Z-shape claimed by applicant is nothing more than one of numerous contour shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Furthermore, the claimed L-shape of a redistribution layer on the plane where the interconnection layer is located is known in the art: Huang, in the same field of endeavor, teaches (see, e.g., Huang: fig. 2C) that the shape of a redistribution layer 30 on the plane where the interconnection layer 304 is located is a L-shape (see, e.g., Huang: par. [0037]).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the L-shape of Huang, because redistribution layer is known in the semiconductor art to have a L-shape for its use as a RDL similarly used for in instant invention and Jo in view of Shin, as suggested by Huang, and implementing a known structure shape for its conventional use/purpose would have been a common-sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jo in view of Hubacher (US 5554940).
Regarding claim 2, Jo shows (see, e.g., Jo: figs. 2-4) most aspects of the instant invention including a package structure, comprising N first pads 110, second pads 135c1, and third pads 135c2, and a RDL 130. Jo also shows (see, e.g., Jo: figs. 2-4) that the third pads 135c2 are located at one end of the RDLs 130 away from the first pad 110.
Jo, however, fails (see, e.g., Jo: figs. 2-4) to show that the second pads 135c1 are located at another end of the RDLs 130 close to the first pads 110. Moreover, Jo shows that second pads 135c1 are located at the same end with the third pads 135c2.
Hubacher, in a similar device to Jo, shows (see, e.g., Hubacher: fig. 8, and also col.1/II.48-50) that the second pads 24 are located at another end of the RDLs 32/36 close to the first pads 42. Hubacher also shows (see, e.g., Hubacher: fig. 8, and also col.1/II.48-50) that the redistribution metallization layer is used to redistribute the peripheral bond pad configuration into a C4 array or partial array pad configuration (see, e.g., Hubacher: col.1/II.48-50).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the second pads are located at one end of the RDLs close to the first pads of Hubacher in device of Jo, to allow the redistribution metallization layer being used to redistribute the peripheral bond pad configuration into a C4 array or partial array pad configuration.
In reference to the language in claim 1 referring to the structure of the device, it is noted that Jo shows all structural aspects of the package structure according to the instant invention (see paragraph 22 above), and that providing testing when the semiconductor functional structure is at different running speeds does not affect the function of the final device. Furthermore, Jo’s device is configured of performing the claimed functions since the performing function interaction corresponding to content tested would involve a mere manipulation of the structure of the package structure.
As to the grounds of rejection of claims 1 and 12 under section 103, see MPEP § 2112, which discusses the handling of functional language in the claims and recommends the alternative (§ 102/ § 103) grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814