DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (claims 1, 2, 5-10, 19, and 21) in the reply filed on 7/22/2026 is acknowledged.
Claims 3, 4, 11-18, and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 9, 10, and 19 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kayama (US 5153696).
With regard to claim 1, Kayama teaches, in Figs 2-5, a semiconductor assembly, comprising: a semiconductor switching device comprising a drain structure (109) and a plurality of array units (MN2), wherein each array unit of the plurality of array units comprises a respective load pad (106) of a plurality of load pads and a respective plurality of transistor cells (column 2, lines 55-60) electrically connected in parallel between the respective load pad of the array unit and the drain structure; a conductive load base structure (105); and a current sense circuit (119) electrically connected between a first load pad of the plurality of load pads and the conductive load base structure.
With regard to claim 2, Kayama teaches, in Figs 2-5, that in each array unit of the plurality of array units, the respective plurality of transistor cells are formed directly between the respective load pad of the array unit and the drain structure (see Figures 3-4).
With regard to claim 9, Kayama teaches, in Figs 2-6, that a first terminal of the current sense circuit is directly connected to the first load pad and a second terminal of the current sense circuit is directly connected to a second load pad of the plurality of load pads (See figures 5 and 6; column 3, lines 55-68).
With regard to claim 10, in reference to the claim language referring to "wherein the current sense circuit comprises an overcurrent detection circuit configured to evaluate a current flowing through the current sense circuit between the first load pad and the conductive load base structure or a current flowing between the first load pad and a second load pad of the plurality of load pads," intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963); Ex parte Masham, 2USPQ2d 1647 (Bd. Pat. App. &Inter. 1987). In the instant case, as explained above with regard to claim 1, Kayama shows all structural limitations specifically recited in the claim and it appears that the recited functional limitation does not affect the structure of Kayama's device.
With regard to claim 19, Kayama teaches, in Figs 2-5, a semiconductor assembly, comprising: a semiconductor switching device comprising a drain structure (109) and an array unit (MN2), wherein the array unit comprises a load pad (106) and a plurality of transistor cells (column 2, lines 55-60) electrically connected in parallel between the load pad and the drain structure; a conductive load base structure (105); and a current sense circuit (119) electrically connected between the load pad and the conductive load base structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kayama (US 5153696) in view of Amada (US 2014/0118056).
With regard to claim 5, Kayama teaches most of the limitations of the claim, as set forth above with regard to claim 1.
Koyama does not explicitly teach a first load connection structure, wherein the first load connection structure electrically connects the conductive load base structure and a second load pad of the plurality of load pads.
Amada teaches, in Fig 6, a first load connection structure (not labeled, but shown between 2 and various Tr1-Tr5), wherein the first load connection structure electrically connects the conductive load base structure (2) and a second load pad of the plurality of load pads (Tr1-Tr5), “to materialize a configuration of protecting a semiconductor device to control the forward or reverse flow of electric current against reverse connection of a power source by a simple structure,” ([0009]).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the assembly of Koyama with the connection structures of Amada to materialize a configuration of protecting a semiconductor device to control the forward or reverse flow of electric current against reverse connection of a power source by a simple structure.
With regard to claim 6, Amada teaches, in Fig 6, that the first load connection structure electrically connects the conductive load base structure, the second load pad, and a third load pad of the plurality of load pads (see figure, some connections made through other elements).
Allowable Subject Matter
Claim 21 is allowed.
Claims 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to anticipate or render obvious claimed limitations of wherein the gate connection lines are formed in pad gaps between neighboring load pads of the plurality of load pads, as set forth in claim 7, or of wherein a first terminal of the current sense circuit is directly connected to the first load pad and a second terminal of the current sense circuit is directly connected to the conductive load base structure, as set forth in claim 8, each when taken in concert with all the other limitations of the claim, the base claim, and any intervening claims. The prior art of record further fails to anticipate or render obvious claimed limitations of wherein each array unit of the plurality of array units comprises a load pad of a plurality of load pads and a plurality of transistor cells electrically connected in parallel between the load pad of the array unit and the drain structure, and wherein the backside metallization of the semiconductor switching device and the collector plate of the module substrate are electrically connected; and a current sense unit electrically connected between a first load pad of the plurality of load pads and the conductive load base structure, as set forth in independent claim 21, when taken in concert with all the other limitations of the claim.
Conclusion
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/RAJ R GUPTA/Primary Examiner, Art Unit 2893
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