DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed November 18th, 2025 are noted. Applicant’s amendments to the Specification to overcome the objections set forth in the Non-Final Office Action mailed 08/26/2025 are noted. Applicant’s amendment(s) to the Specification have not overcome the objection(s) to the Title previously set forth in the Non-Final Office Action mailed 08/26/2025, as the new-title is not considered more descriptive than the original, so the objection(s) to the Title has been maintained.
Applicant’s amendments to the claims are noted.
3. Claims 2-4 are now canceled; Claims 21-25 are newly-added; Claims 1 and 5-25 remain pending in the application; Claims 10-20 are withdrawn.
4. Claims 1, 5-9, and 21-25 have been fully considered in examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is still not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7-9 and 24-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (U.S. PG Pub No US2019/0378911A1) (of record).
Regarding claim 7, Lee teaches a transistor structure [see fig. 10, 0028, 0081] comprising:
a channel region (comprising 110, 210) fig. 10 [0036] of a gate structure (comprising 120) fig. 10 [0087-0088] of a transistor [0028];
a first (lower 136) fig. 10 [0050] and a second (upper 136) fig. 10 [0050] spacer at a first (lower end comprising 110) and a second end (upper end comprising 210) of the channel region (comprising 110, 210);
a high-k dielectric layer (137) fig. 10 [0051-0053] on top of and surrounding the channel region (comprising 110, 210) of the gate structure (comprising 120) of the transistor [0028], the high-k dielectric layer (137) being between the first (lower 136) and second (upper 136) spacers and substantially nitrogen-free (substantially Al2O3 [0051]); and
a silicon-nitride layer (131) fig. 10 [0083] surrounding the high-k dielectric layer (137).
Regarding claim 8, Lee teaches the transistor structure [see fig. 10, 0028, 0081] of claim 7. Lee also teaches wherein the high-k dielectric layer (137) fig. 10 [0051-0053] is a first high-k dielectric layer (137) fig. 10 [0051-0053], further comprising a second high-k dielectric layer (132) fig. 10 [0085] (may be titanium oxide/oxynitride [0085] - known in the art as high-k dielectric metal oxide) on top of and surrounding the silicon-nitride layer (131) fig. 10 [0083], and wherein the silicon-nitride layer (131) is a nitrogen-containing monolayer (at least a monolayer).
Regarding claim 9, Lee teaches the transistor structure [see fig. 10, 0028, 0081] of claim 8. Lee also teaches wherein the channel region (comprising 110, 210) fig. 10 [0036] is a silicon nanosheet [0028, 0040] (may be nanosheet or nanowire [0028]);
the second high-k dielectric layer (132) fig. 10 [0085] is thinner than the first high-k dielectric layer (137) fig. 10 [0051-0053] and has a nitrogen concentration level (TiON [0085]) that is higher than a nitrogen concentration level (substantially-zero nitrogen concentration in Al2O3) [0051] of the first high-k dielectric layer (137) fig. 10 [0051-0053].
Regarding claim 24, Lee teaches the transistor structure [see fig. 10, 0028, 0081] of claim 7. Lee also teaches wherein at least a portion of the silicon-nitride layer (131) fig. 10 [0083] is a silicon-monolayer (at-least-a-monolayer, comprising silicon).
Regarding claim 25, Lee teaches the transistor structure [see fig. 10, 0028, 0081] of claim 7. Lee also teaches wherein the high-k dielectric layer (137) fig. 10 [0051-0053] is completely nitrogen-free (because Lee is completely-silent with respect to the presence of nitrogen in layer 137, layer 137 is assumed to be completely-without nitrogen).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 5-6 rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2019/0378911A1) (of record) in view of Cheng (U.S. PG Pub No US2023/0343847A1).
Regarding claim 1, Lee teaches a transistor structure [see fig. 10, 0028, 0081] comprising:
a channel region (comprising 110, 210) fig. 10 [0036] of a gate structure (comprising 120) fig. 10 [0087-0088] of a transistor [0028], the channel region (110, 210) being a silicon [0039-0040] nanosheet (could be nanosheet instead of nanowire [0028]);
a first high-k dielectric layer (137) fig. 10 [0051-0053] (may be aluminum oxide [0051]) above and surrounding the silicon nanosheet (110, 210) to form a gate-all-around structure [0028]; and
a silicon-nitride layer (131) fig. 10 [0083] directly on top of and surrounding the first high-k dielectric layer (137); and
a second high-k dielectric layer (132) fig. 10 [0085] (may be titanium oxide/oxynitride [0085] - known in the art as high-k dielectric metal oxide) above and surrounding the silicon-nitride layer (131), the first high-k dielectric layer (137), and the silicon nanosheet (110, 210),
wherein the high-k dielectric layer (137) is substantially free of nitrogen (substantially composed of metal-oxide such as aluminum oxide [0051]; assumed to be free of nitrogen since nitrogen presence not explicitly disclosed in 137), and has a first thickness (unspecified) and the second high-k dielectric layer (132) has a second thickness (unspecified).
However, Lee does not explicitly disclose wherein the first thickness (thickness of inner 137 Al2O3 layer) is larger than the second thickness (thickness of outer 132 TiO2 layer) (thicknesses of first and second high-k dielectrics 137, 132 not explicitly disclosed).
Cheng teaches a transistor structure [see fig. 22, 0083-0084] wherein the first thickness (thickness of inner 220 high-k layer) fig. 22 [0023] (9 angstroms) is larger than the second thickness (thickness of outer 230) fig. 22 [0023] (6 angstroms) (“second gate dielectric layer 230… is substantially thinner than the first gate dielectric layers 222, 220” [0023 Cheng]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the relative thicknesses of the high-k dielectric layers surrounding the channels such that the second, outer high-k dielectric layer is substantially thinner than the first, inner high-k dielectric layer [0023, 0076] in order to optimize the thickness characteristics of the atomically-thin dielectric layers [0023] based on their material’s properties and device functions [0024] in order to enhance the scaling-down of transistor components [0013-0014, 0002], as taught by Cheng.
Regarding claim 5, Lee teaches the transistor structure [see fig. 10, 0028, 0081] of claim 1. Lee also teaches wherein the second high-k dielectric layer (132) fig. 10 [0085] (may be titanium oxide/oxynitride [0085] - known in the art as high-k dielectric metal oxide) includes nitrogen to have a nitrogen concentration level (TiON [0085]) that is higher than a nitrogen concentration level (substantially-zero nitrogen concentration in Al2O3) [0051] of the first high-k dielectric layer (137) fig. 10 [0051-0053].
Regarding claim 6, Lee teaches the transistor structure [see fig. 10, 0028, 0081] of claim 1. Lee also teaches wherein the silicon-nitride layer (131) fig. 10 [0083] is a nitrogen-containing monolayer (at-least-a-monolayer, comprising nitrogen) having a portion thereof being a silicon (comprising) monolayer (at-least-a-monolayer, also comprising silicon).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2019/0378911A1) (of record) modified by Cheng (U.S. PG Pub No US2023/0343847A1), as applied in claim 1 above, and further in view of Yoshida (U.S. PG Pub No US2017/0309479A1).
Regarding claim 22, Lee teaches the transistor structure [see fig. 10, 0028, 0081] of claim 1. However, Lee does not explicitly disclose wherein the silicon-nitride layer (131) fig. 10 [0083] is a nitrogen- containing monolayer having a thickness between 1 angstrom and 10 angstroms (thickness not explicitly disclosed).
Yoshida teaches a transistor structure (applicable to GAA-FET dielectric processing [0050]) wherein the silicon-nitride layer is a nitrogen-containing monolayer having a thickness between 1 angstrom and 10 angstroms (thickness of silicon-rich, SiNx monolayer(s) [0044-0045] may be approximately 0.2nm = 2 angstroms total thickness [0045], within 1-10 angstrom range).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the GAA-FET structure of Lee [0050 Yoshida] such that the silicon nitride layer is formed by ALD-stacked SiNx-monolayer(s) [0049-0050] in order to enable surface passivation [0024, 0044] and other other desired SiN layer functionalities [0022] without generating unwanted trap defect states [0044] and without undesirable oxygen contamination [0022], as taught by Yoshida.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub No US2019/0378911A1) (of record) modified by Cheng (U.S. PG Pub No US2023/0343847A1), as applied in claim 1 above, and further in view of Yoshida (U.S. PG Pub No US2017/0309479A1).
Regarding claim 23, Lee teaches the transistor structure [see fig. 10, 0028, 0081] of claim 7. However, Lee does not explicitly disclose wherein the silicon-nitride layer (131) fig. 10 [0083] is a nitrogen- containing monolayer having a thickness between 1 angstrom and 10 angstroms (thickness not explicitly disclosed).
Yoshida teaches a transistor structure (applicable to GAA-FET dielectric processing [0050]) wherein the silicon-nitride layer is a nitrogen-containing monolayer having a thickness between 1 angstrom and 10 angstroms (thickness of silicon-rich, SiNx monolayer(s) [0044-0045] may be approximately 0.2nm = 2 angstroms total thickness [0045], within 1-10 angstrom range).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the GAA-FET structure of Lee [0050 Yoshida] such that the silicon nitride layer is formed by ALD-stacked SiNx-monolayer(s) [0049-0050] in order to enable surface passivation [0024, 0044] and other other desired SiN layer functionalities [0022] without generating unwanted trap defect states [0044] and without undesirable oxygen contamination [0022], as taught by Yoshida.
Response to Arguments
Applicant's arguments filed 11/18/2026 have been fully considered but they are not persuasive.
With respect to Applicant’s argument(s) of independent claim 7 that “elements 110 and 210 in FIG. 10 of Lee are two different channel regions, and the lower 136 and upper 136 are two interfacial layers, not spacers, that surround the channel region 110 and the channel region 210, respectively. They are neither at a first end nor at a second end of a channel region that the Office Action failed to identify. Applicant submits the lower 136 and upper 136 are not at a first end and a second end of the channel region 110, neither they are at a first end and a second end of the channel region 210” --- it is emphasized that the rejection of record defines a single “channel” region as comprising both channel layers 110 and 210. That is, elements 110 and 210 are separate portions of a single channel region of the device. Considering “a channel region” as the space in Lee’s device comprising 110 and 210 fig. 10 [0036 Lee] - a first spacer (lower 136) fig. 10 [0050] is positioned at/ borders a first end (lower end of channel region = bottom of 110), and a second spacer (upper 136) fig. 10 [0050] is positioned at / borders a second end (upper end of channel region = top of 210). Because claim 7 presently places no structural limitations on what can and cannot be considered as a part of the claimed “channel region”, such as describing it as a ‘continuous’ or ‘contiguous’ region – there is nothing which prevents the Examiner from making this interpretation of the claimed “channel region”.
With respect to Applicant’s argument(s) of claims 1, 24, and 25 that “Applicant submits Lee never discloses the alleged high-k dielectric layer 137 is "free of nitrogen" or "substantially free of nitrogen", which is specifically recited in claim 1 of present application. In fact, the cited [0051] of Lee never describes whether the alleged high-k dielectric layer 137 contains nitrogen or does not contain nitrogen. Instead, [0051] describes "[t]he first high dielectric constant insulating layer 137 may include an insulating material containing a metal “--- it is noted that because Lee is entirely silent with respect to the presence of the specific element “nitrogen” in layer 137, Lee does not teach a high-k dielectric layer 137 having any nitrogen. Conversely stated, the high-k dielectric layer 137 of Lee cannot be assumed to have nitrogen, and is therefore considered to be entirely without nitrogen. In part based upon Applicant’s own admission in the Remarks filed 11/18/2025 that “In fact, the cited [0051] of Lee never describes whether the alleged high-k dielectric layer 137 contains nitrogen or does not contain nitrogen” --- the high-k dielectric layer 137 is assumed to not contain any nitrogen for the purposes of rejection.
Applicant’s arguments, see page 3, filed 11/18/2025, with respect to the rejection(s) of claim(s) 1 and 5-6 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Cheng (U.S. PG Pub No US2023/0343847A1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they all feature transistor gate stacks.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 01/15/2026
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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