DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 11/5/2025, responding to the Office action mailed
on 8/11/2025, has been entered into the record. The present Office action is made
with all the suggested amendments being fully considered. Accordingly, claims 1, 3, and 5-15 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A).
Re Claim 1 Iwabuchi teaches a method (FIG. 7) for manufacturing a semiconductor structure, comprising:
providing a first wafer (52a at FIG. 7c) [0008] having a first side (bottom, surface away from 58) and a second side (top) opposite to each other,
thinning the first wafer (52a at FIG. 7e, separation step 108) from the second side (bottom of 52 a, wafer flipped in FIG. 7d) along a direction perpendicular to the first side (top), until a thickness of the remaining first wafer reaches a preset thickness (thickness at step 108, wafer 52a);
wherein the thinning comprises performing film peeling (FIG. 7) at least once and the film peeling comprises:
performing hydrogen ion implantation [0010] on the second side (top, surface near 58) to form a hydrogen ion-containing layer (58) in the first wafer (52a, FIG. 7c); and
heating the first wafer [0013] to cause the hydrogen ion-containing layer (58) to fall off (FIG. 7e).
wherein prior to the film peeling (heating in step 108, [0013], FIG. 7c), the method further comprises: polishing (cleaning, step 105) [0011] the second side (top, entire wafer is cleaned) of the first wafer (52a) from the second side (top and bottom surfaces cleaned) along the direction perpendicular to the first side, until the thickness of the remaining first wafer becomes a first thickness (52a post 105 step), the first thickness being larger than the preset thickness (thickness of 52a at FIG. 7d is larger than thickness of 52a at FIG. 7e);
wherein the method further comprises: providing a second wafer (56a) [0013] having a front side (top) and a back side (bottom) opposite to each other (FIG. 7d) and bonding the second side of the first wafer (bottom) with the second wafer (52a, FIG. 7d).
Iwabuchi does not teach a first conductive structure being provided in the first wafer, and an end of the first conductive structure being located in the first wafer;
thinning the first wafer to expose the end of the first conductive structure;
wherein the front side of the second wafer exposes a second conductive structure, and after the thinning, bonding the second side of the first wafer with the front side of the second wafer.
Hong teaches a first conductive structure (130-1, page 6 par 3) being provided in the first wafer (100-1, page 6 par 2), and an end of the first conductive structure being located in the first wafer (FIG. 8G);
thinning the first wafer to expose the end of the first conductive structure (130-1, FIG. 8H);
wherein the front side of the second wafer (100-2) exposes a second conductive structure (130-2, page 6 par 4, FIG. 8I), and after the thinning (FIG. 8G and 8H, page 19 last par), bonding the second side of the first wafer (FIG. 8I, 100-1, wafer flipped from FIG. 8H) with the front side of the second wafer (top of 100-2, FIG. 8I, page 20 par 4).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Hong in the structure of Iwabuchi since Hong teaches a method of wafer thinning and wafer bonding.
The ordinary artisan would have been motivated to modify Hong in combination with Iwabuchi in the above manner for the motivation of exposing conductive structures in a wafer to bond with a second wafer to allow the wafers have optimal packaging to help realize high performance and large capacity and miniaturization. Page 3 par 4 states, “The semiconductor package used in the electronic device, requiring high performance and large capacity and miniaturization and light weight. In response to these requirements, in order to realize high performance and large capacity and miniaturization and lightweight, it is continuously researching and developing the semiconductor package in which a plurality of semiconductor wafers are combined.”
Re Claim 13 Iwabuchi in view of Hong teaches the method according to claim 1, but does not explicitly teach a heating temperature for the heating the first wafer is 400-600 °C
Iwabuchi teaches a heating temperature for the heating the first wafer ([0013] “Then, by applying heat treatment (separation heat treatment) at a temperature of 500.degree. C. or higher…”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Iwabuchi in combination with Hong since Iwabuchi teaches a method of film peeling after thinning (cleaning, FIG. 7A, [0008]).
The ordinary artisan would have been motivated to modify Iwabuchi in combination with Hong in the above manner for the motivation of finding optimal heat treatment temperatures. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal heat treatment temperatures.
Re Claim 15 Iwabuchi in view of Hong teaches a semiconductor structure formed by the method for manufacturing a semiconductor structure according to claim 1 (device formed after completing claim 1, refer to claim 1 mapping/figures for device structure).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A) as applied to claim 1 above, and further in view of パク (JP 2007535809 A).
Re Claim 3 Iwabuchi in view of Hong teaches the method according to claim 1, but does not teach prior to the polishing, the method further comprises: providing a carrier wafer; and bonding the first side of the first wafer with the carrier wafer.
パク teaches prior to the polishing, the method further comprises: providing a carrier wafer; and bonding the first side (top of 600, page 7 par 5) of the first wafer with the carrier wafer (606, FIG. 6, page 7 last 2 par, “support wafer 606 is attached thereon (FIG. 6E). At this time, as the wax, a water-soluble one that dissolves well in water can be selected. The support wafer is bonded by vertical or horizontal bonding. The support wafer 606 protects the SOI wafer during the subsequent polishing process and facilitates the process. That is, when polishing an SOI wafer, there is a problem that the wafer is thinned while being polished and the wafer is broken in the polishing chuck. Even if polished, the wafer can be safely held in the chuck without cracking.
In the state where the support wafer 606 is attached in this manner, the base wafer 600is polished to a predetermined thickness”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by パク in combination with Iwabuchi in view of Hong since パク teaches a method of bonding and polishing wafers.
The ordinary artisan would have been motivated to modify Liu in combination with パク in combination with Iwabuchi in view of Hong in the above manner for the motivation of bonding the wafer to a carrier before polishing to help protect the structural integrity of the wafer from mechanical issues during processing. Page 7 par 7 states, “Even if polished, the wafer can be safely held in the chuck without cracking.”
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A) and パク (JP 2007535809 A) as applied to claims 1 and 3 above, and further in view of Liu (CN 210607189 U).
Re Claim 5 Iwabuchi in view of Hong and パク teaches the method according to wherein prior to bonding the first wafer with the second wafer, but does not teach the method further comprises:
forming a groove at the second side of the first wafer, the groove exposing the first conductive structure; and
forming a third conductive structure in the groove, the third conductive structure being electrically connected with the first conductive structure.
Liu teaches the method further comprises:
forming a groove (201) at the second side (top) of the first wafer (page 4 par 8,200), the groove exposing the first conductive structure (202, page 4 par 9, FIG. 2C); and
forming a third conductive structure (213, page 6 last par) in the groove (201), the third conductive structure (213) being electrically connected with the first conductive structure (202, FIG. 2E).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Liu in combination with Iwabuchi in view of Hong and パク since Liu teaches a method forming a groove to expose a conductive layer and then add another conductive layer in the groove.
The ordinary artisan would have been motivated to modify Liu in combination with Iwabuchi in view of Hong and パク in the above manner for the motivation of exposing the embedded conductive layer to help optimize the device structure and function at peak levels. Page 1 states, “The utility model has advantages as follows: low package height for forming semiconductor package structure, high stability, high reliability and low warping.”
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A) and パク (JP 2007535809 A) and Liu (CN 210607189 U) as applied to claims 1 and 3 and 5 above, and further in view of Yu (US 20200009844 A1).
Re Claim 6 Iwabuchi in view of Hong and パク and Liu teaches the method according to claim 5, but does not teach after bonding the second side of the first wafer with the front side of the second wafer, the method further comprises: removing the carrier wafer.
Yu teaches after bonding the second side (bottom) of the first wafer (602) [0095] with the front side (top) of the second wafer (608) [0095], the method further comprises: removing the carrier wafer (600, [0095], FIG. 38/39).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Yu in combination with Iwabuchi in view of Hong and パク and Liu since Yu teaches a method of stacking and bonding wafers.
The ordinary artisan would have been motivated to modify Yu in combination with Iwabuchi in view of Hong and パク and Liu in the above manner for the motivation of removing the carrier/handler wafer after the wafer structure is able to support itself. [0095] states, “The process repeats until the wafer stacks are self supporting and the handler wafer removed (FIG. 39g).”
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A) as applied to claim 1 above, and further in view of Morimoto (US 20090023269 A1).
Re Claim 7 Iwabuchi in view of Hong teaches the method according to claim l, but does not teach after the polishing, the hydrogen ion implantation is performed throughout the second side of the polished first wafer.
Morimoto teaches after the polishing (FIG. 1, wafer 10 post S101) [0056], the hydrogen ion implantation (S103) [0057] is performed throughout the second (top) side of the polished first wafer (10, FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Morimoto in combination with Iwabuchi in view of Hong since Morimoto teaches a method of wafer polishing and ion implantation.
The ordinary artisan would have been motivated to modify Liu in combination with Morimoto in combination with Iwabuchi in view of Hong in the above manner for the motivation of polishing the wafer and implanting hydrogen ions post polishing to help the wafer function at high speeds and low power consumption. [0002] states, “An SOI wafer has been used in an LSI of high-speed low-power consumption, as it is considered superior to a conventional silicon wafer in some properties, including separation between devices, reduced parasitic capacitance between a device and a substrate and a three-dimensional structure to be feasible.”
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A) as applied to claim 1 above, and further in view of Song (US 20060008993 A1).
Re Claim 8 Iwabuchi in view of Hong teaches the method according to claim 1, wherein after the polishing and prior to the film peeling, the method further comprises:
performing hydrogen ion implantation (Iwabuchi, FIG. 7, 104) on a structure formed at the second side (top) when polishing (wafer cleaned in step 101).
Hong in view of Iwabuchi does not teach performing ion implantation on a convex structure, wherein a depth of the hydrogen ion implantation is the same as a depth difference between the convex structure and a concave structure formed at the second side when polishing.
Song teaches ion implantation (100) on a convex structure (above 12, FIG. 5),
wherein a depth of the ion implantation (‘d’ in image below) is the same as a depth difference between the convex structure (cavity region above 12, FIG. 5) and a concave structure (16a) formed at the second side when polishing (FIG. 5).
Image below shows a fragment of FIG 5 with ‘d’ added to show the distance the ion implanted layer spans vertically
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Song in combination with Iwabuchi in view of Hong since Song teaches a method of ion implantation.
The ordinary artisan would have been motivated to modify Song in combination with Iwabuchi in view of Hong in the above manner for the motivation of implanting ions onto the wafer to help improve the reliability of the device. [0007] states, “Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a flash memory device in which an overlay margin between an active region and a floating gate is secured, the overlay margin uniformity is obtained across the entire wafer, and generation of moats at the boundary between an isolation film and the active region across the entire wafer is prevented, whereby reliability of the flash memory device is improved…”
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A) and Song (US 20060008993 A1) as applied to claim 1 and 8 above, and further in view of Bateman (US 20140120647 A1).
Re Claim 9 Iwabuchi in view of Hong and Song teaches the method according to claim 8, wherein prior to the hydrogen ion implantation (Iwabuchi, FIG. 7C), the method further comprises: oxidizing [0009] the convex structure (taught in previous claim) on a surface of the second (top 52a) side to form an oxide layer (54a, FIG. 7B).
Hong in view of Iwabuchi and Song does not teach removing the oxide layer.
Bateman teaches removing the oxide layer. (FIG. 3D-3F, [0049] states, “After removing the thermal oxide layer 322, the second ion implantation process may be performed.”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Bateman in combination with Iwabuchi in view of Hong and Song since Bateman teaches a method of removing an oxide layer before an ion implantation process.
The ordinary artisan would have been motivated to modify Bateman in combination with Iwabuchi in view of Hong and Song in the above manner for the motivation of removing the oxide layer before the ion implantation to optimize the implantation process top optimally change one of its electrical, optical, chemical, and mechanical properties. [0002] states, “An ion implantation process is a process used in a device manufacturing to implant one or more desired species into a target to change at least one of its electrical, optical, chemical, and mechanical property.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A) and Song (US 20060008993 A1) and Bateman (US 20140120647 A1) as applied to claims 1 and 8 and 9 above, and further in view of 西畑 秀樹 (JP 4730645 B2).
Re Claim 10 Iwabuchi in view of Hong and Song and Bateman teaches the method according to claim 9, but does not teach the oxidizing comprises an in-situ steam generation oxidation or a furnace oxidation.
西畑 秀樹 teaches the oxidizing comprises a furnace oxidation (page 5 par 3, “The oxide films 12a and 12b are formed by placing a silicon wafer in an oxidation furnace”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by 西畑 秀樹 in combination with Iwabuchi in view of Hong and Song and Bateman since 西畑 秀樹 teaches a method of ion implantation.
The ordinary artisan would have been motivated to modify 西畑 秀樹 in combination with Iwabuchi in view of Hong and Song and Bateman in the above manner for the motivation of using a furnace to oxidize the wafer to build a semiconductor structure that that functions at an optimal level and can be used in high or low power consumption circuits. Page 1 par 2 states, “Compared with conventional silicon wafers, SOI wafers have superiority such as isolation between elements, reduction in parasitic capacitance between the elements and the substrate, and a three-dimensional structure, and are used in high-speed and low-power consumption LSIs.”
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A) as applied to claim 1 above, and further in view of Onodera (US 20190271073 A1).
Re Claim 11 Iwabuchi in view of Hong teaches the method according to claim 2, but does not teach after the polishing, the method further comprises: measuring a flatness of the second side.
Onodera teaches after the polishing [0063], the method further comprises: measuring a flatness of the second side (top of 20, FIG. 3, [0064] states, “The flatness (local flatness) of a freely selected 20 mm square on the wafer W was measured…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Onodera in combination with Iwabuchi in view of Hong since Onodera teaches a method of polishing a wafer and then measuring its surface flatness.
The ordinary artisan would have been motivated to modify Liu in combination with Onodera in combination with Iwabuchi in view of Hong in the above manner for the motivation of achieving a healthy flatness profile on the wafer surface after polishing it to help the device have high wear resistance. [0003] states, “SiC members formed of a SiC sintered body have high rigidity and high wear resistance.”
Re Claim 12 Iwabuchi in view of Hong and Onodera teaches the method according to claim 11, wherein an apparatus for measuring the flatness of the second side (Onodera, top of 20, FIG. 3) comprises a laser interferometer ([0064] states, “The flatness (local flatness) of a freely selected 20 mm square on the wafer W was measured with a laser interferometer…”).
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Iwabuchi (US 20060154445 A1) in view of Hong (CN 112701100 A) as applied to claim 1 above, and further in view of Tomonori (EP 2793267 A1).
Re Claim 14 Iwabuchi in view of Hong teaches the method according to claim 1, wherein the thinning comprises performing the film peeling (Iwabuchi, FIG. 7 cleaning (101), ion implant (104) and heating/separation, (108)) multiple times (film peeling is only done once in Iwabuchi, but the process can be repeated).
Hong in view of Iwabuchi does not teach an implantation depth of the hydrogen ion implantation gradually becomes smaller from a first hydrogen ion implantation to a last hydrogen ion implantation.
Tomonori teaches an implantation depth of the hydrogen ion implantation gradually becomes smaller from a first hydrogen ion implantation to a last hydrogen ion implantation (Page 4 par 2 states, “The hydrogen ions are implanted in a plurality of continuous individual steps in which the amount of hydrogen ions implanted is gradually reduced…”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Tomonori in combination with Iwabuchi in view of Hong since Tomonori teaches a method of ion implantation.
The ordinary artisan would have been motivated to modify Tomonori in combination with Iwabuchi in view of Hong in the above manner for the motivation of optimizing the ion implantation process to help the device function at an ideal electric field range. Page 2 last par states, “In a edge termination structure region 100b which reduces the electric field on the front surface side of the n- drift region 101 and holds a breakdown voltage…”
Response to Arguments
Applicant’s arguments with respect to claims 1, 3, and 5-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 5/27/26
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