DETAILED ACTION
This Office action responds to the patent application no. 18/153,013 filed on January 11, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in CN on August 30, 2021. It is noted, however, that applicant has not filed a certified copy of the CN202111001404.9 application as required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a second TSV structure … coming into contact with the first TSV structure at the first side of the substrate” and “both the first TSV structure and the second TSV structure come into contact with the metal line” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Farooq et al. (Farooq hereinafter).
Regarding Claim 1:
Farooq (see, paras. [0018] – [0025] and Figs 1, 2, and 4A) teaches the instant invention: a semiconductor structure, comprising: a substrate 210, comprising a first side 211 and a second side 412 opposite to each other; a dielectric layer 250, provided at the first side of the substrate; a first through silicon via (TSV) structure 252, extending from a top surface of the dielectric layer to the first side of the substrate; and a second TSV structure 220 & 430, extending from the second side of the substrate to the first side of the substrate, coming into contact with the first TSV structure at the first side of the substrate, and having a preset opening width.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (Farooq hereinafter).
Regarding to Claim 7:
Farooq (see, paras. [0018] and [0024]) teaches the top section via with a width in a range of 0.04 to 5 μm and “bottom via width 431 can be selected relative to the length D(b) based on a manageable length to width (i.e., aspect ratio), which can be between 10 and 1, and can preferably be between 1.5 and 5 … bottom section via width 431 can be equal to the top via width 421 (or if a section has a non-uniform cross section, then at least at the intersection of the top and bottom via sections”, but does not explicitly teach wherein the preset opening width ranges from 2μm to 20μm.
However, the differences in width range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such width ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the width range of through vias, it would have been obvious to one of ordinary skill in the art to use this range to control the width of a through via based on the penetrated height of the substrate or the dielectric layer to meet the design rules.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions or locations or are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934, 1936s (Fed. Cir. 1990).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (Farooq hereinafter) as applied to claim 1 above, and further in view of Oganesian et al. (Oganesian hereinafter).
Regarding Claims 2 and 3:
Although Farooq (see, para. [024] and Fig. 5A) teaches “bottom section via width 431 can be equal to the top via width 421 (or if a section has a non-uniform cross section, then at least at the intersection of the top and bottom via sections” and multilayered Inter-Metal Dielectric (IMD) structures above the substrate and a variety of through silicon via (TSV) structures contacting a metal layer in IMD, Farooq does not explicitly teach wherein a metal liner is provided in the dielectric layer, and both the first TSV structure and the second TSV structure come into contact with the metal liner. However, the differences in specific locations of the through vias and metal layer will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such specific locations are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Oganesian (see, FIGs. 4, 5, 16-20, 21, 29-32, 35-37, 39, 41-44, 46, 48-51, 53) teaches a variety of embodiments showing two through vias sandwiched a metal layer within a dielectric layer, or a through via contacting both the metal layer and the other through via, but not two through vias contacting each other and the metal layer at the same time.
Accordingly, since the applicant has not established the criticality (see the paragraph on page 5) of the relative locations of through vias and metal pads, it would have been obvious to one of ordinary skill in the art to choose any configuration electrically connecting two through vias with or without contacting the metal layer and each other at the same time to achieve the interconnection purpose.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (Farooq hereinafter) in view of Oganesian as applied to claim 2 above, and further in view of Chen et al. (Chen hereinafter).
Regarding Claim 4:
Farooq (see, para [004]) teaches “a TSV’s axis is typically substantially normal to the planar orientation of the chip”. The combination of the device of Farooq in view of Oganesian does not explicitly teach tapered through silicon via and tapered through dielectric via (bold text below).
an extension direction of the first TSV structure serves as a first direction,
the first direction refers to an axial direction of the first TSV structure, and along the first direction,
a radial size of the first TSV structure decreases gradually; and
an extension direction of the second TSV structure serves as a second direction opposite to the first direction,
the second direction refers to an axial direction of the second TSV structure, and along the second direction,
a radial size of the second TSV structure decreases gradually.
However, Chen (see, para. [0028] and FIGs. 1A-1D, and 2A-2D) teaches “the conductive vias 104 comprise a sidewall tapered from their respective openings 104-1 to their bottoms” and tapered protective structures 312.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of the device Farooq in view of Oganesian to further include the teaching of Chen. The motivation for doing so is to tailor the design rules with desired conical shape or tapering profile of the through vias with the benefit of better manufacturability, less cross talk, and better counterbalance of power and thermal distribution.
Regarding Claims 5 and 6:
Farooq (see, paras. [0033]-[0034] and FIG. 7) teaches “the retrograde shaped … provides an advantageous profile for depositing barrier, seed, and/or liner layer … minimizes the amount of area … at the wafer top surface”, “joining a plurality of small top vias 720a and 720b with bottom side via 730”, and “when the current minimum dimensions are larger than the typical dimension for the process layer selected for forming such top via sections”. However, the combination of the device of Farooq in view of Oganesian does not explicitly teach more than one TSVs in the substrate as in the instant invention (bold text below).
the semiconductor structure further comprises: a third TSV structure, extending from the second side of the substrate to the first side of the substrate, and connected to the metal liner.
the first TSV structure defines a first pattern at a bottom surface of the dielectric layer, and
projection of the first pattern on the substrate falls within projection of the metal liner on the substrate; and
the second TSV structure defines a second pattern at the first side of the substrate,
the third TSV structure defines a third pattern at the first side of the substrate, and
projection of each of the second pattern and the third pattern on the substrate falls within the projection of the metal liner on the substrate.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of the device of Farooq in view of Oganesian to further include the teaching of Chen. The motivation for doing so is to tailor the design rules with desired conical shape or tapering profile of the through vias and with a plurality of tapered TSVs having current minimum dimensions in the substrate electrically connected in the same metal line as one tapered TSV in the dielectric layer with the benefit of better manufacturability of barrier, seed, and/or liner layer and minimum wafter surface area occupied by interconnection structures.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (Farooq hereinafter) in view of Oganesian et al. (Oganesian hereinafter).
Regarding Claim 8:
Farooq (see, paras. [0018] – [0034] and FIGs. 1, 2, 4A-4C, 5A-5B, and 7) teaches two trenches formed in the same figure and “optionally all top vias 720 are formed simultaneously” besides a forming method of a semiconductor structure, comprising:
providing a substrate 100 and a dielectric layer (150, 151) or (250, 251) disposed on the substrate,
the substrate comprising a first side 211 and a second side 412, and
the dielectric layer being provided at the first side of the substrate;
forming a first through silicon via (TSV) structure 252,
the first TSV structure extending from a top surface of the dielectric layer to the first side of the substrate; and
However, Farooq does not explicitly teach the other forming method (bold text below).
forming a second TSV structure,
the second TSV structure extending from the second side of the substrate to the first side of the substrate,
coming into contact with the first TSV structure at the first side of the substrate, and having a preset opening width.
Oganesian (see, FIGs. 4, 5, 16-20, 21, 29-32, 35-37, 39, 41-44, 46, 48-51, 53) teaches a variety of embodiments showing one through silicon via and one through dielectric via sandwiching a metal layer within a dielectric layer or a through via contacting both the metal layer and the other through via.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of the method of Farooq to further include the teaching of Oganesian to reduce the number of manufacturing steps for the through via in the substrate.
Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (Farooq hereinafter) in view of Oganesian et al. (Oganesian hereinafter) as applied to claim 8 above, and further in view of Woo et al. (Woo hereinafter).
Regarding Claims 9-11:
The combination of Farooq in view of Oganesian does not explicitly teach annealing step nor forming a plurality of TSVs at the same time during the method of forming a semiconductor structure (the bold text below).
the forming a first TSV structure comprises:
forming a first opening,
the first opening extending from the top surface of the dielectric layer to the first side of the substrate;
forming the first TSV structure,
the first TSV structure covering the first opening; and
performing first annealing on the semiconductor structure.
the forming a second TSV structure comprises:
forming a second opening,
the second opening extending from the second side of the substrate to the first side of the substrate;
forming the second TSV structure,
the second TSV structure covering the second opening; and
performing second annealing on the semiconductor structure.
etching back the second side of the substrate,
thinning the substrate according to a length of the second TSV structure to be formed.
forming a metal liner,
the metal liner being provided in the dielectric layer, wherein
a first side of the metal liner covers a bottom surface of the first TSV structure, and
a second side of the metal liner covers a bottom surface of the second TSV structure.
forming a third TSV structure,
the third TSV structure extending from the second side of the substrate to the first side of the substrate, wherein
the second side of the metal liner covers a bottom surface of the third TSV structure.
the forming a third TSV structure comprises:
forming a third opening, the third opening extending from the second side of the substrate to the first side of the substrate, and
exposing a part of the second side of the metal liner; and
forming the third TSV structure,
the third TSV structure covering the third opening and the exposed second side of the metal liner.
the forming a second TSV structure and the forming a third TSV structure are performed at the same time; and after the second TSV structure and the third TSV structure are formed,
the second annealing is performed on the semiconductor structure.
However, Woo (see, col.5//ll.54-col.6/ll.13) teaches a first annealing step after filling up the narrower metal trenches formed of substantially pure copper.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teachings of the method of Farooq in view of Oganesian to further include the teaching of Woo to insert an annealing step after each set of the through vias filled up with metal material on the same side, to substantially eliminate or significantly reduce the formation of voids in narrower trenches and to form a plurality of TSVs on the same side simultaneously to reduce the manufacturing steps.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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