DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, species I (Fig. 2A) (claims 1-7, 11-14, 17-20) in the reply filed on 12/04/2025 is acknowledged.
Claims 8-10, 15-16, 21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/04/25.
Drawings
Figure 1A, 1B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 5 is objected to because of the following informalities: “TL layer” should be “TR layer”.. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-7, 11-14, 17-20 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 defines in line 3 “a silicon substrate” has antecedent issue. It should be “the silicon substrate”.
Claim 1 defines in line 13 “..in a region about the peak” is unclear. Is it a separate region near the peak as in line 6 it defines “a peak,,a region of the BOX layer”? “The BOX layer in the region around/near the peak” is suggested.
Claims 2-7, 11-14, 17-20 are also rejected being dependent on rejected claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsumura et al (JP 2002289552 A).
Regarding claim 1: Matsumura teaches in different embodiments of Fig. 1 about a method for simultaneous generation of a buried oxide (BOX) layer and a trap-rich (TR) layer in a silicon substrate, the method comprising:
PNG
media_image1.png
687
786
media_image1.png
Greyscale
providing a silicon substrate 1;
implanting oxygen (O+) into the silicon substrate;
based on the implanting, producing an implantation concentration profile that includes:
a peak at a target depth of the silicon substrate that corresponds to a region of the BOX layer (as shown);
a leading-edge that extends from a region of the silicon substrate proximal a surface of said substrate to the peak (As marked); and
a trailing edge that extends from the peak to a region of the silicon substrate distal the surface of the silicon substrate (as marked); and
annealing the silicon substrate thereby simultaneously generating (page 6 teaches a BOX layer similar to a conventional low-dose SIMOX is once manufactured by first oxygen ion implantation and first high-temperature heat treatment):
the BOX layer in a region about the peak (As marked), and
a first damaged layer in a region below the BOX layer that extends along the trailing edge, the first damaged layer providing functionality of the TR layer (as marked and page 7 teaches the damage that occurs in the substrate in the second ion implantation can be concentrated inside or below the BOX layer formed by the first high-temperature heat treatment).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7, 11-13, 17-20 are rejected under 35 U.S.C. 103 as being obvious over Matsumura et al (JP 2002289552 A).
Regarding claim 2: Matsumura does not explicitly talk about wherein:
the implantation concentration profile in the region about the peak is stoichiometric, and
the implantation concentration profile in the region that extends along the trailing edge and away from the peak is under-stoichiometric.
However Matsumura shows in Fig. 1-4 about where the damage/free atoms are away from the peak/middle.
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the application was filed, to realize that region near the peak would be stoichiometric and the implantation concentration profile in the region that extends along the trailing edge and away from the peak is under-stoichiometric as an inherent working function/outcome of the ion implantation and annealing/heating step.
Regarding claim 3: As explained abobe in claims 1-2, Matsumura teaches as an inherent working function/outcome of the ion implantation and annealing/heating step wherein: the BOX layer is provided by a region of silicon oxide that is substantially devoid of free silicon or oxygen atoms, and the first damaged layer is provided by defects imparted to a crystalline structure of the silicon substrate.
Regarding claims 4, 18: As explained above in claims 1-2, Matsumura teaches as an inherent working function/outcome of the ion implantation and annealing/heating step wherein:
the defects imparted to the crystalline structure include one or more of: a) implanted oxygen, b) diffused oxygen, or c) random bonding of oxygen with silicon.
Regarding claims 5, 19: Matsumura teaches in page 6, wherein: a thickness of the BOX layer is in a range from 20 nm to 500 nm (the thickness of the BOX layer is 60 nm or more and 250 nm or less), and
Matsumura does not explicitly talk about a thickness of the TL layer is in a range from 20 nm to 3 um.
However Matsumura teaches in different embodiments of Fig. 2-3 in pages 9-11 about increasing/adjusting the BOX layer thickness depending number of io implantations steps, implantation doses and energy and would decrease/adjust the damaged/TR layer accordingly.
It would have been obvious to one having ordinary skill in the art at the time of the application was filed to have specific values of the TR layer in the range as claimed, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 6: Matsumura teaches in Fig. 1 about further comprising: based on the annealing, further generating a thin layer of silicon 3 above the BOX layer, the thin layer of silicon provided by a region of the silicon substrate between the surface of the silicon substrate and a start of the leading-edge.
Regarding claim 7: Matsumura teaches in [0003] – 0004] forming at least one transistor in the thin layer of silicon, the at least one transistor configured for operation as a radio frequency (RF) device.
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987).
Regarding claim 11: Matsumura teaches in [0003] – 0004] wherein: the silicon substrate is a high resistivity silicon substrate.
Regarding claim 12: Matsumura does not explicitly talk about wherein: the high resistivity is provided by a resistivity of the silicon substrate that is equal to or higher than 200 Ohm.cm.
However Matsumura teaches in [0005] by interposing the BOX layer, it is electrically insulated from the main body of the substrate, so that it is possible to improve radiation resistance and latch-up resistance
It would have been obvious to one having ordinary skill in the art at the time of the application was filed to have specific values of the resistivity in the range as claimed, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 13: Matsunura teaches in Fig. 3 depending on ion doses, energy, number of implantations, wherein: the trailing-edge of the implantation concentration profile is longer that the leading-edge of the implantation concentration profile.
Regarding claims 17, 20: As explained in claims 1-2, Matsumura teaches the limitations.
Claim 14 is rejected under 35 U.S.C. 103 as being obvious over Matsumura et al (JP 2002289552 A) in view of Robert et al. (US PGPUB 2004/0126985 A1)
Regarding claim 14: Matsumura does not explicitly show further comprising: masking a top surface of the silicon substrate prior to the implanting and the annealing, thereby generating localized layered structures separated by a separation region that exclusively contains a crystalline structure of the silicon substrate, wherein each of the localized layered structures comprises a localized region of the BOX layer and a localized region of the first damaged layer.
Robert teaches in Fig. 3D about masking 18 a top surface of the silicon substrate 10 prior to the implanting 22 and the annealing, thereby generating localized layered structures 24 separated by a separation region (between 24’s) that exclusively contains a crystalline structure of the silicon substrate.
PNG
media_image2.png
300
586
media_image2.png
Greyscale
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the application was filed, to have the features as claimed by masking Matsumura’s device according to the teachings of Robert and thereby where a particular IC requires that the active device regions be separated in IC fabrication (Robert, [0004])).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
Prosecution Insights