Prosecution Insights
Last updated: April 19, 2026
Application No. 18/153,375

CAPACITOR STRUCTURE

Final Rejection §103
Filed
Jan 12, 2023
Examiner
LOPEZ, JORGE ANDRES
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Powerchip Semiconductor Manufacturing Corporation
OA Round
2 (Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
4y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
14 granted / 14 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
4y 4m
Avg Prosecution
28 currently pending
Career history
42
Total Applications
across all art units

Statute-Specific Performance

§103
70.3%
+30.3% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
9.9%
-30.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 14 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims Claims 1-20 remain pending, with claim 1 being independent. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. 103 as being obvious over US 2023/0307492 A1; Chou et al.; 09/2023; (“492”) in view of US 10,468,187 B2; Shin et al.; 11/2019; (“187”). Regarding Claim 1. 492 teaches in Fig. 3 about a capacitor structure comprising: a substrate (item 202); a capacitor (MIM capacitor item 104) comprising: first electrode layers (items 102a and 102c) and at least one second electrode layer (items 102b and 102d) alternately disposed on the substrate (first and second electrode layers are alternately disposed on the substrate); and a first dielectric layer (item 114a) disposed between one of the first electrode layers and the at least one second electrode layer (disposed between items 102a and 102b); a second dielectric layer (item 117) disposed on the first electrode layers and the at least one second electrode layer (disposed on layer items 102a, 102c and at least on layer item 102b) and having a first opening (opening for conductive plug structure item 106) and at least one second opening (opening for conductive plug structure item 108), wherein the first opening exposes the first electrode layers (first opening exposes layers 102a and 102c), and the at least one second opening exposes the at least one second electrode layer (second opening exposes at least layer 102b); a first conductive layer (layer embodying the conductive plug structure item 106) electrically connected to the first electrode layers (layer item 106 connects to layer items 102a and 102c), wherein the first conductive layer is a single conductive layer disposed on the second dielectric layer (first conductive layer is a single layer item 106 disposed on layer item 117) and extending into the first openings (first conductive layer extends into opening for item 106); and a second conductive layer (layer embodying the conductive plug structure item 108) electrically connected to the at least one second electrode layer (layer item 108 connects to at least layer items 102b) and disposed on the second dielectric layer (second conductive layer disposed on layer item 117) and in the at least one second opening (second conductive layer disposed on at least opening for conductive plug structure item 108). PNG media_image1.png 834 1297 media_image1.png Greyscale Top part of Fig. 3 (annotated by Examiner), from Chou et al., “492” 492 does not teach about a capacitor structure comprising: first openings. 187 teaches in Figs. 1 and 2 about a capacitor structure comprising: first openings (Fig. 1, openings for via items 41), wherein the first openings expose the first electrode layers (Fig. 2, first openings expose the first electrode layers items 21). It would have been obvious to try by one of ordinary skill in the art, at the time the invention was made, to consider utilizing the first openings of 187 to connect the first electrode layers at multiple locations via a plurality of first openings in the capacitor structure of 492 in order to provide connection redundancy (“since the first via 41 is connected to all of the first electrode layers 21 …, even if some of the internal electrodes … are not connected to the via … there is no problem in forming capacitance, such that reliability may be excellent”) as taught by 187 in Col. 9, Ln. 47-54. Regarding Claim 2. 492 teaches in Fig. 3 about a capacitor structure, wherein the first conductive layer extends into the first opening. 492 does not teach about a capacitor structure, wherein the first conductive layer extends into all the first openings. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first conductive layer extend into the duplicated first openings as explained in Claim 1 rejection, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 3. 492 teaches in Fig. 3 about a capacitor structure, wherein the first conductive layer comprises: a conductive line portion (upper horizontal line portion of item 106); and contact portions connected to the conductive line portion (lower horizontal line portion items 208a and 208b). 492 does not teach about a capacitor structure, wherein each of the contact portions is disposed in the corresponding first opening. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each of the contact portions disposed in the corresponding first opening for each duplicated first opening as explained in Claim 1 rejection, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 4. 492 teaches in Fig. 3 about a capacitor structure, wherein the conductive line portion and the contact portions are integrally formed (conductive line portion and contact portions 208a-b are integrally formed into conductive layer item 106). Regarding Claim 5. 492 teaches in Fig. 3 about a capacitor structure, wherein a portion of the first openings exposes the same first electrode layer (portion items 208b expose the same first electrode layer item 102c). Regarding Claim 6. 492 teaches in Fig. 3 about a capacitor structure, wherein a first opening exposes different first electrode layers. 492 does not teach about a capacitor structure, wherein two adjacent first openings expose different first electrode layers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate first openings as explained in rejection for Claim 1 and to provide redundant connections by exposing different first electrode layers, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 7. 492 teaches in Fig. 3 about a capacitor structure, comprising a plurality of the second electrode layers (items 102b and 102d), wherein the second dielectric layer comprises a second opening, the second opening exposes the second electrode layers (second opening exposes electrode layer 102b and 102d), and the second conductive layer is a single conductive layer (conductive layer item 108 is a single layer) disposed on the second dielectric layer (disposed on layer item 117) and extending into the second openings (second conductive layer extends into opening for item 108). 492 does not teach about a capacitor structure, wherein the second dielectric layer comprises a plurality of the second openings. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate the second opening as the first opening was duplicated and explained for the rejection of Claim 1, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 8. 492 teaches in Fig. 3 about a capacitor structure, wherein the second conductive layer extends into the second opening (second conductive layer item 108 extends into the second opening). 492 does not teach about a capacitor structure, wherein the second conductive layer extends into all the second openings. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate the second opening as the first opening was duplicated and explained for the rejection of Claim 1, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 9. 492 teaches in Fig. 3 about a capacitor structure, wherein a portion of the second openings exposes the same second electrode layer (portion items 208d expose the same second electrode layer item 102d). Regarding Claim 10. 492 teaches in Fig. 3 about a capacitor structure, wherein a second opening exposes different second electrode layers. 492 does not teach about a capacitor structure, wherein two adjacent second openings expose different second electrode layers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate second openings as explained in rejection for Claim 1 regarding first openings and to provide redundant connections by exposing different second electrode layers, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 11. 492 teaches in Fig. 3 about a capacitor structure, wherein the second conductive layer comprises: conductive line portion (upper horizontal line portion of item 108); and at least one contact portion connected to the conductive line portion (lower horizontal line portion items 208c and 208d), wherein the at least one contact portion is disposed in the at least one second opening (at least item 208c is disposed in the second opening). Regarding Claim 12. 492 teaches in Fig. 3 about a capacitor structure, wherein the conductive line portion and the at least one contact portion are integrally formed (conductive line portion and contact portions 208c-d are integrally formed into conductive layer item 108). Regarding Claim 13. 492 teaches in Fig. 3 about a capacitor structure, wherein a top surface of the first conductive layer and a top surface of the second conductive layer have the same height (top surfaces of layer items 106 and 108 have the same height). Regarding Claim 14. 492 teaches in Fig. 3 about a capacitor structure, wherein there are two openings in the capacitor. 492 does not teach about a capacitor structure, wherein there are third openings in the capacitor. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate openings as explained in rejection for Claim 1 regarding first openings and to provide redundant connections between first or second conductive layers and first or second electrode layers, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 15. 492 teaches in Fig. 3 about a capacitor structure, wherein a portion of the second dielectric layer is disposed in the first and second openings (second dielectric portion items 116a-c are disposed in the first and second openings). 492 does not teach about a capacitor structure, wherein a portion of the second dielectric layer is disposed in the third openings. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate openings to create third openings as explained in rejection for Claim 1 and to include portions of the second dielectric layer in these duplicated third openings (to provide an insulative dielectric layer within the third openings), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 16. 492 teaches in Fig. 3 about a capacitor structure, wherein a top-view pattern of the first conductive layer and a top-view pattern of the second conductive layer match each other (first and second conductive layers match number of horizontal and vertical segments from a top-view). Regarding Claim 17. 492 teaches in Fig. 3 about a capacitor structure, wherein a top-view pattern of the first conductive layer is not disclosed, a top-view pattern of the second conductive layer is not disclosed. 492 does not teach about a capacitor structure, wherein a top-view pattern of the first conductive layer comprises a first comb-shaped portion, a top-view pattern of the second conductive layer comprises a second comb shaped portion, and the first comb-shaped portion and the second comb-shaped portion match each other. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the shape, size, or coverage of the first and second conductive layers to fit any semiconductor package where the invention may be deployed (to meet capacitance and design needs), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Regarding Claim 18. 492 teaches in Fig. 3 about a capacitor structure, wherein a second connection terminal (item 210) electrically connected to the at least one second electrode layer by the second conductive layer (item 210 connects to at least item 102b by layer item 108). 492 does not teach about a capacitor structure, wherein a first connection terminal electrically connected to the first electrode layers by the first conductive layer; and It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate the second connection terminal type and use the same terminal type for the first connection terminal (to provide the capacitor structure with top connection accessibility for the first and second conductive layers), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04. Regarding Claim 19. 492 teaches in Fig. 3 about a capacitor structure, wherein the second connection terminal is shown in a cross-sectional view and no details regarding possible top views are disclosed. 492 does not teach about a capacitor structure, wherein a top-view pattern of the first connection terminal comprises a first side, a second side, a third side, and a fourth side, the first side and the third side are opposite to each other, the second side and the fourth side are opposite to each other, the second side is connected to the first side and the third side and is disposed between the first side and the third side, the fourth side is connected to the first side and the third side and is disposed between the first side and the third side, a top-view pattern of the second connection terminal comprises a fifth side, a sixth side, a seventh side, and an eighth side, the fifth side and the seventh side are opposite to each other, the sixth side and the eighth side are opposite to each other, the sixth side is connected to the fifth side and the seventh side and is disposed between the fifth side and the seventh side, and the eighth side is connected to the fifth side and the seventh side and is disposed between the fifth side and the seventh side. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the layout of a first and second connection terminals to comprise a plurality of sides and/or shapes (to meet capacitance and design needs), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Regarding Claim 20. 492 teaches in Fig. 3 about a capacitor structure, wherein first and second conductive layers are represented as whole and independent from each other. 492 does not teach about a capacitor structure, wherein a top-view pattern of the first conductive layer comprises: a first main portion disposed directly below the top-view pattern of the first connection terminal; a first extension portion connected to the first main portion, wherein the first extension portion is disposed between the top-view pattern of the first connection terminal and the top-view pattern of the second connection terminal and is adjacent to the fifth side of the second connection terminal; and a second extension portion connected to the first main portion, wherein the second extension portion surrounds the sixth side, the seventh side, and the eighth side of the second connection terminal, and a top-view pattern of the second conductive layer comprises: a second main portion disposed directly below the top-view pattern of the second connection terminal, a third extension portion connected to the second main portion, wherein the third extension portion is disposed between the top-view pattern of the first connection terminal and the top-view pattern of the second connection terminal and is adjacent to the first side of the first connection terminal; and a fourth extension portion connected to the second main portion, wherein the fourth extension portion surrounds the second side, the third side, and the fourth side of the first connection terminal. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the layout of a first and second connection terminals and conductive layers to comprise a plurality of conductive sub-layers embodying a greater in size first and second conductive layers (to meet capacitance and design needs), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Response to Arguments Applicant's arguments filed on 01/15/2026 have been fully considered but they are not persuasive. Regarding applicant’s arguments concerning prior art reference 492 not teaching about a plurality of first openings not exposing the first electrode layers, this additional subject matter is taught by Shin et al. (US 10,468,187 B2) as detailed in the above rejection of claim 1. Therefore, applicant’s arguments are not persuasive. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached Monday-Friday 8 am - 5 pm MST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jan 12, 2023
Application Filed
Oct 31, 2025
Non-Final Rejection — §103
Jan 15, 2026
Response Filed
Feb 03, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604762
METHODS AND APPARATUS TO REDUCE THICKNESS OF ON-PACKAGE MEMORY ARCHITECTURES
2y 5m to grant Granted Apr 14, 2026
Patent 12598997
INDUCTOR WITH INTEGRATED MAGNETICS
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 2 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
4y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 14 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month