DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 23, 2026 has been entered.
Response to Amendment
The Amendment filed February 23, 2026 has been entered. Applicant' s amendments to the Specification have overcome the objections of the prior Office Action.
Response to Arguments
Applicant’s arguments with respect to claims 1-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specifically, the claims are rejected in view of newly identified prior art Huang; Ho-Chung et al. (US 4458215) in combination with previously cited references. Please see the claim rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-9, 11-12, 16-17, 22-25, and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Du; Guochen et al. (US 2024/0213946; hereinafter Du) in view of Paital; Sameer et al. (US 2023/0085411; hereinafter Paital), Weis; Gerald et al. (US 2024/0113037; hereinafter Weis), and Huang; Ho-Chung et al. (US 4458215; hereinafter Huang).
Regarding claim 1, Du discloses a tunable filter (Figs 1,3-7; ¶ [0034-72]), comprising:
a substrate (10, comprised of glass; Figs 3-7; ¶ [0040]);
a varactor (C2, capacitance may be changed by changing an input voltage; Fig 1, and comprising plates 31 and 32 of Fig 3; ¶ [0035-36, 0040]) and a capacitor (C1; Fig 1, and comprising plates 31 and 32 of Fig 3; ¶ [0035-36, 0040]);
one or more through-substrate-vias (TSV) (213; Figs 3,5-7; ¶ [0053]) in the substrate, each TSV extending from the frontside of the substrate to a backside of the substrate;
one or more frontside redistribution layer (RDL) metals (212; Figs 3,5-7; ¶ [0040-41]) on the frontside of the substrate and electrically connected with the one or more TSVs; and
one or more backside RDL metals (211; Figs 3,5-7; ¶ [0040]) on the backside of the substrate and electrically connected with the one or more TSVs,
wherein the one or more TSVs, the one or more frontside RDL metals, and the one or more backside RDL metals are configured to form one or more inductors (L; Figs 1,2, and comprising 211-213 of Fig 3; ¶ [0035-41]).
Du does not disclose (1) the substrate has a blind substrate cavity (BSC) formed therein, the BSC penetrating a depth from a frontside of the substrate; (2) a varactor/cap die within the BSC, the varactor/cap die comprising the varactor and the capacitor; (3) a conductive dry film, the conductive dry film located in a gap between a side surface of the BSC and the varactor/cap die; and (4) wherein the varactor/cap die further comprises: a varactor/cap substrate, wherein the varactor and the capacitor are formed on and in contact with a first side of the varactor/cap substrate, and wherein a second side of the varactor/cap substrate is on a lateral surface of the substrate within the (BAC), the second side of the varactor/cap substrate being opposite the first side of the varactor/cap substrate.
Regarding (1), (2), and (3), in the same field of endeavor, Paital discloses a microelectronic assembly (100; Fig 1; ¶ [0066-0081]), comprising:
a substrate (102, comprised of glass; Fig 1; ¶ [0066]) with a blind substrate cavity (BSC) (106; Fig 1; ¶ [0067-68]) formed therein, the BSC penetrating a depth from a frontside of the substrate;
a die (108; Fig 1; ¶ [0067-68]) within the BSC, which may be a varactor/cap die comprising a varactor and a capacitor (108 may comprise {only} passive elements, or any suitable IC; ¶ [0068]); and
a dielectric (122; Figs 1,4G; ¶ [0071,0085], the dielectric located in a gap between a side surface of the BSC and the die.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the substrate with BSC of Paital’s microelectronic assembly with the tunable filter of Du by placing the varactor and capacitor of Du into a die within a BSC in the substrate as taught by Paital. One would have been motivated to do this in order to reduce the size of the device (at least vertically, by moving the varactor and capacitor within the height of the substrate), while maintaining capability for stringent via-to-pad overlay requirements enabled by the rigid substrate (Paital; ¶ [0014-17]). One would have had a reasonable expectation of success due to the similar materials (glass substrates) and structures (TSV’s {Paital; 118; Fig 1; ¶ [0070]} making connection to RDL metals on either side of the substrate {Paital; 124, on either side of core 104; Fig 1; ¶ [0071]}) of Du and Paital, and because formation or acquisition of a varactor/cap die comprising a varactor and a capacitor is readily within the capability of a person having ordinary skill in the art.
Neither Paital nor Du disclose that the dielectric is a conductive dry film.
In the same field of endeavor, Weis discloses a die (112; Fig. 2; ¶ [0081]) disposed within a BSC (110; Fig. 2; ¶ [0080]) of a substrate (102; Fig 2; ¶ [0078]) comprising a conductive dry film (dielectric 114, having high thermal conductivity; Fig 2; ¶ [0083-84,0087,0092-93]) located in a gap between a side surface of the BSC and the die).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have replaced the dielectric of Paital in view of Du with the dielectric 114 of Weis. One would have been motivated to do this in order to include the efficient heat transfer capability it provides (Weiss; ¶ [0025,0084]). One would have had a reasonable expectation of success because of the similar BSC-disposed die and similar substrate materials (a variety of carrier/substrate materials are disclosed by Weis, including comprising glass or aluminum oxide; ¶ [0046, 0049, 0043-50]; further, a variety of substrate materials are known in the art, being selected depending upon a variety of characteristics which must be weighed against a variety of performance and manufacturing requirements for a particular application; it would have been obvious for one to consider a variety of combinations of substrate materials and dielectric materials to best satisfy requirements.)
Regarding (4), in the same field of endeavor, Huang discloses a varactor/cap die (10; Figs 1, 3; Col 1, line 30 – Col 3, line 54) comprising:
a varactor/cap substrate (20; Fig 3; Col 1, lines 65-68),
wherein a varactor (12; Figs 1,3; Col 1, lines 53-57) and a capacitor (16; Figs 1,3; Col 1, lines 53-57) are formed on and in contact with a first side of the varactor/cap substrate (upper side of 20, as shown in Fig 3).
Accordingly, it would have been obvious to have used a varactor/cap die structure similar to that of Huang for the varactor/cap die of Du in view of Paital and Weiss, wherein a second side of the varactor/cap substrate (lower side of 20; Huang) is on a lateral surface of the substrate within the (BAC), the second side of the varactor/cap substrate being opposite the first side of the varactor/cap substrate. One would have been motivated to do this as a suitable tunable filter structure (Huang; means for tuning frequency; Col 1, lines 9-20), since Paital has not disclosed the detailed structure of the varactor/cap die 108. One would have had a reasonable expectation of success because of the similarly disclosed purpose (tunable filter) for the varactor and capacitor of Du and Huang, and because Paital discloses that any suitable IC fabricated on a semiconductor substrate may be used (Paital; ¶ [0068]).
Regarding claim 6, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 1, wherein the one or more TSVs are formed from any one or more of copper (Cu) aluminum (Al), and tungsten (W), or
wherein the one or more frontside RDL metals are formed from any one or both of Cu, Al, and W, or
wherein the one or more backside RDL metals are formed from any one or both of Cu, Al, and W, or any combination of the above (Du; 211-213; Fig 5; ¶ [0053-56]).
Regarding claim 7, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 1, wherein the varactor is a III-V varactor (Huang; GaAs substrate, compound semiconductor active layer; Col 1, lines 66-67, Col 2, lines 6-8).
Regarding claim 8, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 7, wherein the varactor is a gallium arsenide (GaAs) varactor (Huang; GaAs substrate, compound semiconductor active layer; Col 1, lines 66-67, Col 2, lines 6-8).
Regarding claim 9, Du in view of Paital, Weis and Huang discloses the tunable filter of claim 7, wherein the varactor comprises a hyper-abrupt junction active layer (Huang; Col 3, lines 1-3).
Regarding claim 11, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 1, wherein the capacitor (Huang; 16) is a metal-insulator-metal (MIM) capacitor (Huang; Col 3, lines 36-49).
Regarding claim 12, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 1, but does not disclose wherein the varactor/cap die further comprises: one or more varactor/cap connects in electrical connection with the varactor and the capacitor and with at least one frontside RDL metal; however, this would have been obvious to a person having ordinary skill in the art.
Paital discloses (Fig 1) that the die 108 is connected to frontside RDL metal 124 (¶ [0071]). In order for the varactor and capacitor to function as intended as elements in the tunable filter, they must have an electrical connection external to the die and to the inductor, which as applied to claim 1 is in electrical connection with the frontside RDL metal. In order for this to be true the connection from 108 to 124 must include varactor/cap connects that provide electrical connection with the varactor and the capacitor and with 124.
Regarding claim 16, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 1, wherein the tunable filter is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle (Paital; Fig 8; ¶ [0115-0129])
Regarding claim 17, Du discloses a method of fabricating a tunable filter (Figs 1,3-7; ¶ [0034-72]), the method comprising:
providing a substrate (10, comprised of glass; Figs 3-7; ¶ [0045]);
providing a varactor (C2, capacitance may be changed by changing an input voltage; Fig 1, and comprising plates 31 and 32 of Fig 3; ¶ [0035-36, 0040, 0053-64]) and a capacitor (C1; Fig 1, and comprising plates 31 and 32 of Fig 3; ¶ [0035-36, 0040-43]);
filling a gap between a side surface of the BSC and the varactor with a dielectric;
forming one or more through-substrate-vias (TSV) (213; Figs 3,5-7; ¶ [0053]) in the substrate, each TSV extending from the frontside of the substrate to a backside of the substrate;
forming one or more frontside redistribution layer (RDL) metals (212; Figs 3,5-7; ¶ [0040-41, 0053-60]) on the frontside of the substrate and electrically connected with the one or more TSVs; and
forming one or more backside RDL metals (211; Figs 3,5-7; ¶ [0040, 0053-61]) on the backside of the substrate and electrically connected with the one or more TSVs,
wherein the one or more TSVs, the one or more frontside RDL metals, and the one or more backside RDL metals are configured to form one or more inductors (L; Figs 1,2, and comprising 211-213 of Fig 3; ¶ [0035-41]).
Du does not disclose (1) the substrate has a blind substrate cavity (BSC) formed therein, the BSC penetrating a depth from a frontside of the substrate; (2) providing a varactor/cap die within the BSC, the varactor/cap die comprising the varactor and the capacitor; (3) filling a gap between a side surface of the BSC and the varactor/cap die with a conductive dry film; and (4) wherein the varactor/cap die further comprises: a varactor/cap substrate, wherein the varactor and the capacitor are formed on and in contact with a first side of the varactor/cap substrate, and wherein a second side of the varactor/cap substrate is on a lateral surface of the substrate within the (BAC), the second side of the varactor/cap substrate being opposite the first side of the varactor/cap substrate.
Regarding (1), (2), and (3), in the same field of endeavor, Paital discloses a microelectronic assembly (100; Fig 1; ¶ [0066-0081]), comprising:
a substrate (102, comprised of glass; Fig 1; ¶ [0066]) with a blind substrate cavity (BSC) (106; Fig 1; ¶ [0067-68]) formed therein, the BSC penetrating a depth from a frontside of the substrate;
a die (108; Fig 1; ¶ [0067-68]) within the BSC, which may be a varactor/cap die comprising a varactor and a capacitor (108 may comprise {only} passive elements, or any suitable IC; ¶ [0068]);
a dielectric (122; Figs 1,4G; ¶ [0071,0085], the dielectric located in a gap between a side surface of the BSC and the die.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the substrate with BSC of Paital’s microelectronic assembly with the tunable filter of Du by providing a substrate with BSC of Paital and placing the varactor and capacitor of Du into a die within the BSC as taught by Paital. One would have been motivated to do this in order to reduce the size of the device (at least vertically, by moving the varactor and capacitor within the height of the substrate), while maintaining capability for stringent via-to-pad overlay requirements enabled by the rigid substrate (Paital; ¶ [0014-17]). One would have had a reasonable expectation of success due to the similar materials (glass substrates) and structures (TSV’s making connection to RDL metals on either side of the substrate) of Du and Paital, and because formation or acquisition of a varactor/cap die comprising a varactor and a capacitor is readily within the capability of a person having ordinary skill in the art.
Neither Paital nor Du disclose that the dielectric is a conductive dry film.
In the same field of endeavor, Weis discloses a die (112; Fig. 2; ¶ [0081]) disposed within a BSC (110; Fig. 2; ¶ [0080]) of a substrate (102; Fig 2; ¶ [0078]) comprising a conductive dry film (dielectric 114, having high thermal conductivity; Fig 2; ¶ [0083-84,0087,0092-93]) located in a gap between a side surface of the BSC and the die).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have replaced the dielectric of Paital in view of Du with the dielectric 114 of Weis. One would have been motivated to do this in order to include the efficient heat transfer capability it provides (Weiss; ¶ [0025,0084]). One would have had a reasonable expectation of success because of the similar BSC-disposed die and similar substrate materials (a variety of carrier/substrate materials are disclosed by Weis, including comprising glass or aluminum oxide; ¶ [0046, 0049, 0043-50]; further, a variety of substrate materials are known in the art, being selected depending upon a variety of characteristics which must be weighed against a variety of performance and manufacturing requirements for a particular application; it would have been obvious for one to consider a variety of combinations of substrate materials and dielectric materials to best satisfy requirements.)
Regarding (4), in the same field of endeavor, Huang discloses a varactor/cap die (10; Figs 1, 3; Col 1, line 30 – Col 3, line 54) comprising:
a varactor/cap substrate (20; Fig 3; Col 1, lines 65-68),
wherein a varactor (12; Figs 1,3; Col 1, lines 53-57) and a capacitor (16; Figs 1,3; Col 1, lines 53-57) are formed on and in contact with a first side of the varactor/cap substrate (upper side of 20, as shown in Fig 3).
Accordingly, it would have been obvious to have used a varactor/cap die structure similar to that of Huang for the varactor/cap die of Du in view of Paital and Weiss, wherein a second side of the varactor/cap substrate (lower side of 20; Huang) is on a lateral surface of the substrate within the (BAC), the second side of the varactor/cap substrate being opposite the first side of the varactor/cap substrate. One would have been motivated to do this as a suitable tunable filter structure (Huang; means for tuning frequency; Col 1, lines 9-20), since Paital has not disclosed the detailed structure of the varactor/cap die 108. One would have had a reasonable expectation of success because of the similarly disclosed purpose (tunable filter) for the varactor and capacitor of Du and Huang, and because Paital discloses that any suitable IC fabricated on a semiconductor substrate may be used (Paital; ¶ [0068]).
Regarding claim 22, Du in view of Paital, Weis, and Huang discloses the method of claim 17, wherein the one or more TSVs are formed from any one or more of copper (Cu) aluminum (Al), and tungsten (W), or
wherein the one or more frontside RDL metals are formed from any one or both of Cu, Al, and W, or
wherein the one or more backside RDL metals are formed from any one or both of Cu, Al, and W, or any combination of the above (Du; 211-213; Fig 5; ¶ [0053-56]).
Regarding claim 23, Du in view of Paital, Weis, and Huang discloses the method of claim 17, wherein the varactor is a III-V varactor (Huang; GaAs substrate, compound semiconductor active layer; Col 1, lines 66-67, Col 2, lines 6-8).
Regarding claim 24, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 23, wherein the varactor is a gallium arsenide (GaAs) varactor (Huang; GaAs substrate, compound semiconductor active layer; Col 1, lines 66-67, Col 2, lines 6-8).
Regarding claim 25, Du in view of Paital, Weis and Huang discloses the tunable filter of claim 23, wherein the varactor comprises a hyper-abrupt junction active layer (Huang; Col 3, lines 1-3).
Regarding claim 27, Du in view of Paital, Weis, and Huang discloses the method of claim 17, wherein the capacitor (Huang; 16) is a metal-insulator-metal (MIM) capacitor (Huang; Col 3, lines 36-49).
Regarding claim 28, Du in view of Paital, Weis, and Huang discloses the method of claim 17, but does not disclose wherein the varactor/cap die further comprises: one or more varactor/cap connects in electrical connection with the varactor and the capacitor and with at least one frontside RDL metal; however, this would have been obvious to a person having ordinary skill in the art.
Paital discloses (Fig 1) that the die 108 is connected to frontside RDL metal 124 (¶ [0071]). In order for the varactor and capacitor to function as intended as elements in the tunable filter, they must have an electrical connection external to the die and to the inductor, which as applied to claim 17 is in electrical connection with the frontside RDL metal. In order for this to be true the connection from 108 to 124 must include varactor/cap connects that provide electrical connection with the varactor and the capacitor and with 124.
Claims 2-5, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Du; Guochen et al. (US 2024/0213946; hereinafter Du) in view of Paital; Sameer et al. (US 2023/0085411; hereinafter Paital), Weis; Gerald et al. (US 2024/0113037; hereinafter Weis), and Huang; Ho-Chung et al. (US 4458215; hereinafter Huang) and further in view of Lan; Je-Hsiung et al. (US 2021/0099149; hereinafter Lan).
Regarding claim 2, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 1, but does not disclose wherein a thermal conductivity of the substrate is greater than 2 W/m-K.
In the same field of endeavor, Lan discloses a passive filter device, comprising:
an alumina ceramic substrate (150; Fig 1; ¶ [0027]), having a thermal conductivity greater than 2 W/m-K (¶ [0025]);
a capacitor (160; Fig 1; ¶ [0028]) and an inductor (180; Fig 1; ¶ [0029]), wherein one or more TSVs (155; Fig 1; ¶ [0029]), one or more frontside RDL metals (155; Fig 1; ¶ [0029]), and one or more backside RDL metals (140; Fig 1; ¶ [0029]) are configured to form the inductor (180; Fig 1; ¶ [0029]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have replaced the glass substrate of Du in view of Paital, Weis, and Huang with an alumina ceramic substrate, as disclosed by Lan. One would have been motivated to do this in order to improve the filter performance and reduce the filter size by taking advantage of the lower loss tangent and higher thermal conductivity along with higher coefficient of thermal expansion (CTE) of an alumina ceramic substrate vs a glass substrate.
One would have had a reasonable expectation of success because of the similar configurations of Du, Paital, Weis, each having TSV’s, frontside RDL metals and backside RDL metals, and because Lan specifically directs the background and summary disclosure towards replacing a glass substrate with an alumina ceramic one for use in the similar passive filter device.
Regarding claim 3, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 1, but does not disclose wherein the substrate is an alumina ceramic substrate, and wherein the one or more TSVs are one or more through-alumina-vias (TAV).
In the same field of endeavor, Lan discloses a passive filter device, comprising:
an alumina ceramic substrate (150; Fig 1; ¶ [0027]);
a capacitor (160; Fig 1; ¶ [0028]) and an inductor (180; Fig 1; ¶ [0029]), wherein one or more TAVs (155; Fig 1; ¶ [0029]), one or more frontside RDL metals (155; Fig 1; ¶ [0029]), and one or more backside RDL metals (140; Fig 1; ¶ [0029]) are configured to form the inductor (180; Fig 1; ¶ [0029]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have replaced the glass substrate of Du in view of Paital, Weis, and Huang with an alumina ceramic substrate, as disclosed by Lan. One would have been motivated to do this in order to improve the filter performance and reduce the filter size by taking advantage of the lower loss tangent and higher thermal conductivity along with higher coefficient of thermal expansion (CTE) of an alumina ceramic substrate vs a glass substrate.
One would have had a reasonable expectation of success because of the similar configurations of Du, Paital and Lan, each having TSV’s, frontside RDL metals and backside RDL metals, and because Lan specifically directs the background and summary disclosure towards replacing a glass substrate with an alumina ceramic one for use in the similar passive filter device.
Regarding claim 4, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 1, wherein at least one inductor is a 3D inductor comprising one or more loops (Du; L; Figs 1,2, and comprising 211-213 of Fig 3; ¶ [0035-41]), each loop comprising at least one TSV (Du; 213; Fig 3) in electrical connection with at least one frontside RDL metal (Du; 212; Fig 3) and with at least one backside RDL metal (Du; 211; Fig 3)
Du in view of Paital, Weis, and Huang does not disclose wherein the at least one TSV is at least one TAV.
In the same field of endeavor, Lan discloses a passive filter device, comprising:
an alumina ceramic substrate (150; Fig 1; ¶ [0027]), wherein one or more TSVs are one or more through-alumina-vias (TAV);
a capacitor (160; Fig 1; ¶ [0028]) and an inductor (180; Fig 1; ¶ [0029]), wherein one or more TAVs (155; Fig 1; ¶ [0029]), one or more frontside RDL metals (155; Fig 1; ¶ [0029]), and one or more backside RDL metals (140; Fig 1; ¶ [0029]) are configured to form the inductor (180; Fig 1; ¶ [0029]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have replaced the glass substrate of Du in view of Paital, Weis, and Huang with an alumina ceramic substrate, as disclosed by Lan. One would have been motivated to do this in order to improve the filter performance and reduce the filter size by taking advantage of the lower loss tangent and higher thermal conductivity along with higher coefficient of thermal expansion (CTE) of an alumina ceramic substrate vs a glass substrate.
One would have had a reasonable expectation of success because of the similar configurations of Du, Paital and Lan, each having TSV’s, frontside RDL metals and backside RDL metals, and because Lan specifically directs the background and summary disclosure towards replacing a glass substrate with an alumina ceramic one for use in the similar passive filter device.
Regarding claim 5, Du in view of Paital and Weis and further in view of Lan discloses the tunable filter of claim 4, wherein the one or more inductors comprise a plurality of 3D inductors (Du discloses that the tunable filter is formed from at least one inductor {¶ [0015]}, and provides a specific example tunable filter comprising a plurality of 3D inductors {L1, L2; Figs 8-9a, and comprising 211-213 of Figs 9b, 11a-12b; ¶ [0073-96]}. Accordingly, it would have been obvious for the one or more inductors to comprise a plurality of 3D inductors.)
Regarding claim 18, Du in view of Paital, Weis, and Huang discloses the method of claim 17, but does not disclose wherein a thermal conductivity of the substrate is greater than 2 W/m-K.
In the same field of endeavor, Lan discloses a passive filter device, comprising:
an alumina ceramic substrate (150; Fig 1; ¶ [0027]), having a thermal conductivity greater than 2 W/m-K (¶ [0025]);
a capacitor (160; Fig 1; ¶ [0028]) and an inductor (180; Fig 1; ¶ [0029]), wherein one or more TSVs (155; Fig 1; ¶ [0029]), one or more frontside RDL metals (155; Fig 1; ¶ [0029]), and one or more backside RDL metals (140; Fig 1; ¶ [0029]) are configured to form the inductor (180; Fig 1; ¶ [0029]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have replaced the glass substrate of Du in view of Paital, Weis, and Huang with an alumina ceramic substrate, as disclosed by Lan. One would have been motivated to do this in order to improve the filter performance and reduce the filter size by taking advantage of the lower loss tangent and higher thermal conductivity along with higher coefficient of thermal expansion (CTE) of an alumina ceramic substrate vs a glass substrate.
One would have had a reasonable expectation of success because of the similar configurations of Du, Paital and Lan, each having TSV’s, frontside RDL metals and backside RDL metals, and because Lan specifically directs the background and summary disclosure towards replacing a glass substrate with an alumina ceramic one for use in the similar passive filter device.
Regarding claim 19, Du in view of Paital, Weis, and Huang discloses the method of claim 17, but does not disclose wherein the substrate is an alumina ceramic substrate, and wherein the one or more TSVs are one or more through-alumina-vias (TAV).
In the same field of endeavor, Lan discloses a passive filter device, comprising:
an alumina ceramic substrate (150; Fig 1; ¶ [0027]);
a capacitor (160; Fig 1; ¶ [0028]) and an inductor (180; Fig 1; ¶ [0029]), wherein one or more TAVs (155; Fig 1; ¶ [0029]), one or more frontside RDL metals (155; Fig 1; ¶ [0029]), and one or more backside RDL metals (140; Fig 1; ¶ [0029]) are configured to form the inductor (180; Fig 1; ¶ [0029]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have replaced the glass substrate of Du in view of Paital, Weis, and Huang with an alumina ceramic substrate, as disclosed by Lan. One would have been motivated to do this in order to improve the filter performance and reduce the filter size by taking advantage of the lower loss tangent and higher thermal conductivity along with higher coefficient of thermal expansion (CTE) of an alumina ceramic substrate vs a glass substrate.
One would have had a reasonable expectation of success because of the similar configurations of Du, Paital and Lan, each having TSV’s, frontside RDL metals and backside RDL metals, and because Lan specifically directs the background and summary disclosure towards replacing a glass substrate with an alumina ceramic one for use in the similar passive filter device.
Regarding claim 20, Du in view of Paital, Weis, and Huang discloses the method of claim 17, wherein at least one inductor is a 3D inductor comprising one or more loops (Du; L; Figs 1,2, and comprising 211-213 of Fig 3; ¶ [0035-41]), each loop comprising at least one TSV (Du; 213; Fig 3) in electrical connection with at least one frontside RDL metal (Du; 212; Fig 3) and with at least one backside RDL metal (Du; 211; Fig 3)
Du in view of Paital, Weis, and Huang does not disclose wherein the at least one TSV is at least one TAV.
In the same field of endeavor, Lan discloses a passive filter device, comprising:
an alumina ceramic substrate (150; Fig 1; ¶ [0027]), wherein one or more TSVs are one or more through-alumina-vias (TAV);
a capacitor (160; Fig 1; ¶ [0028]) and an inductor (180; Fig 1; ¶ [0029]), wherein one or more TAVs (155; Fig 1; ¶ [0029]), one or more frontside RDL metals (155; Fig 1; ¶ [0029]), and one or more backside RDL metals (140; Fig 1; ¶ [0029]) are configured to form the inductor (180; Fig 1; ¶ [0029]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have replaced the glass substrate of Du in view of Paital, Weis, and Huang with an alumina ceramic substrate, as disclosed by Lan. One would have been motivated to do this in order to improve the filter performance and reduce the filter size by taking advantage of the lower loss tangent and higher thermal conductivity along with higher coefficient of thermal expansion (CTE) of an alumina ceramic substrate vs a glass substrate.
One would have had a reasonable expectation of success because of the similar configurations of Du, Paital and Lan, each having TSV’s, frontside RDL metals and backside RDL metals, and because Lan specifically directs the background and summary disclosure towards replacing a glass substrate with an alumina ceramic one for use in the similar passive filter device.
Regarding claim 21, Du in view of Paital, Weis, and Huang and further in view of Lan discloses the method of claim 20, wherein the one or more inductors comprise a plurality of 3D inductors (Du discloses that the tunable filter is formed from at least one inductor {¶ [0015]}, and provides a specific example tunable filter comprising a plurality of 3D inductors {L1, L2; Figs 8-9a, and comprising 211-213 of Figs 9b, 11a-12b; ¶ [0073-96]}. Accordingly, it would have been obvious for the one or more inductors to comprise a plurality of 3D inductors.)
Claims 10 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Du; Guochen et al. (US 2024/0213946; hereinafter Du) in view of Paital; Sameer et al. (US 2023/0085411; hereinafter Paital), Weis; Gerald et al. (US 2024/0113037; hereinafter Weis), and Huang; Ho-Chung et al. (US 4458215; hereinafter Huang), and further in view of Pathak; Divya et al. (US 2019/0393360; hereinafter Pathak).
Regarding claim 10, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 7, but does not disclose wherein a bias voltage of the varactor is 5v or less.
In the same field of endeavor, Pathak discloses a hyper-abrupt junction varactor (Figs 1B,2; ¶ [0022-25]), wherein the capacitance of the varactor varies from less than 10pF to greater than 50pF at a bias voltage range from zero to five volts (0-5v), while the range of capacitance is further extended only to approximately 5pF when the bias voltage is range is further extended from five to ten (5-10v), that is, the varactor may operate over the bulk of its capacitance range using a bias voltage of 0-5v (Fig 1B).
It would have been obvious to a person having ordinary skill in the art that the hyper-abrupt junction varactor of Huang (Huang; Col 3, lines 1-3) may operate similarly, and correspondingly for a bias voltage of the varactor to be 5v or less. One would have been motivated to come to this conclusion, with a reasonable expectation of success because of the similar material (Pathak; gallium arsenide; ¶ [0024]; Huang; GaAs substrate, compound semiconductor active layer; Col 1, lines 66-67, Col 2, lines 6-8)) similar type hyper-abrupt junction varactors of Pathak and Huang).
Regarding claim 26, Du in view of Paital, Weis, and Huang discloses the method of claim 23, but does not disclose wherein a bias voltage of the varactor is 5v or less.
In the same field of endeavor, Pathak discloses a hyper-abrupt junction varactor (Figs 1B,2; ¶ [0022-25]), wherein the capacitance of the varactor varies from less than 10pF to greater than 50pF at a bias voltage range from zero to five volts (0-5v), while the range of capacitance is further extended only to approximately 5pF when the bias voltage is range is further extended from five to ten (5-10v), that is, the varactor may operate over the bulk of its capacitance range using a bias voltage of 0-5v (Fig 1B).
It would have been obvious to a person having ordinary skill in the art that the hyper-abrupt junction varactor of Huang (Huang; Col 3, lines 1-3) may operate similarly, and correspondingly for a bias voltage of the varactor to be 5v or less. One would have been motivated to come to this conclusion, with a reasonable expectation of success because of the similar material (Pathak; gallium arsenide; ¶ [0024]; Huang; GaAs substrate, compound semiconductor active layer; Col 1, lines 66-67, Col 2, lines 6-8)) similar type hyper-abrupt junction varactors of Pathak and Huang).
Claims 14-15, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Du; Guochen et al. (US 2024/0213946; hereinafter Du) in view of Paital; Sameer et al. (US 2023/0085411; hereinafter Paital), Weis; Gerald et al. (US 2024/0113037; hereinafter Weis), and Huang; Ho-Chung et al. (US 4458215; hereinafter Huang), and further in view of Elsherbini; Adel A. et al. (US 2023/0207439; hereinafter Elsherbini).
Regarding claim 14, Du in view of Paital, Weis, and Huang discloses the tunable filter of claim 1, but does not disclose further comprising: another die within the BSC, wherein the another die is made from a technology different from a technology of the varactor/cap die.
In the same field of endeavor, Elsherbini discloses a substrate (660{cross-section}/760{plan view}; Fig 6A/7B; ¶ [0056/0060-61]) with a blind substrate cavity (BSC) formed therein (662{cross-section}/762{plan view}; Fig 6A/7B; ¶ [0056/0060-61]), the BSC penetrating a depth from a frontside of the substrate; a die (665{cross-section}/765A{plan view}; Fig 6A/7B; ¶ [0056/0060-61]) within the BSC; and, another die (765A{plan view}; Fig 7B; ¶ [0060-61]) within the BSC.
Elsherbini does not disclose the another die is made from a technology different from a technology of the varactor/cap die; however, in another, similar embodiment, Elsherbini discloses that an embedded die 215 (Fig 2B; ¶ [0029]) may be a passive die, an active die, and may be silicon based, III-V based, or the like. It would have been obvious to a person having ordinary skill in the art that there be no particular limitation as to what type of technology the die and the another die may be made from, beyond what the overall circuit design and structural limitations require, and may comprise at least the various examples put forth by Elsherbini in ¶ [0029]).
Accordingly, it would have been obvious to have included another die within the BSC of claim 1, wherein the another die is made from a technology different from a technology of the varactor/cap die. One would have been motivated to include the another die in order to include another circuit function into the tunable filter of claim 1 without increasing its size (Paital; improved package performance by reduced package dimensions; ¶ [0014]). One would have been motivated for the another die to be made from another technology in order to optimize the performance/cost benefit of the tunable filter; for example, the varactor/cap die may be gallium-arsenide based to optimize performance (Du; ¶ [0003]), whereas the another die may be a silicon-based CMOS device in order to minimum cost with a widely available commodity device. One would have had a reasonable expectation of success because none of Du, Paital or Elsherbini has suggested limitations on what type of die may suitably be disposed within a BSC, and such consideration is well-known in the art.
Regarding claim 15, Du in view of Paital, Weis, and Huang and further in view of Elsherbini discloses the tunable filter of claim 14, wherein the technology of the another die is CMOS (as is described for claim 14.)
Regarding claim 30, Du in view of Paital, Weis, and Huang discloses the method of claim 17, but does not disclose further comprising: providing another die within the BSC, wherein the another die is made from a technology different from a technology of the varactor/cap die.
In the same field of endeavor, Elsherbini discloses a substrate (660{cross-section}/760{plan view}; Fig 6A/7B; ¶ [0056/0060-61]) with a blind substrate cavity (BSC) formed therein (662{cross-section}/762{plan view}; Fig 6A/7B; ¶ [0056/0060-61]), the BSC penetrating a depth from a frontside of the substrate; a die (665{cross-section}/765A{plan view}; Fig 6A/7B; ¶ [0056/0060-61]) within the BSC; and, another die (765A{plan view}; Fig 7B; ¶ [0060-61]) within the BSC.
Elsherbini does not disclose the another die is made from a technology different from a technology of the varactor/cap die; however, in another, similar embodiment, Elsherbini discloses that an embedded die 215 (Fig 2B; ¶ [0029]) may be a passive die, an active die, and may be silicon based, III-V based, or the like. It would have been obvious to a person having ordinary skill in the art that there be no particular limitation as to what type of technology the die and the another die may be made from, beyond what the overall circuit design and structural limitations require, and may comprise at least the various examples put forth by Elsherbini in ¶ [0029]).
Accordingly, it would have been obvious to have provided another die within the BSC of claim 17, wherein the another die is made from a technology different from a technology of the varactor/cap die. One would have been motivated to include the another die in order to include another circuit function into the tunable filter of claim 17 without increasing its size (Paital; improved package performance by reduced package dimensions; ¶ [0014]). One would have been motivated for the another die to be made from another technology in order to optimize the performance/cost benefit of the tunable filter; for example, the varactor/cap die may be gallium-arsenide based to optimize performance (Du; ¶ [0003]), whereas the another die may be a silicon-based CMOS device in order to minimum cost with a widely available commodity device. One would have had a reasonable expectation of success because none of Du, Paital or Elsherbini has suggested limitations on what type of die may suitably be disposed within a BSC, and such consideration is well-known in the art.
Conclusion
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817