ilDETAILED ACTION
This Office action responds to the Amendment file on October 2, 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments with respect to the claims filed on October 2, 2025 have been considered. The substrate 110 of the Im priort art corresponds to the claimed “a stress-relief substrate”, not the solder of the Im prior art as argued by the Applicant.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the electronic component being electrically connected to a die terminal, a die substrate, a plurality of conductive vias, more passivation layers, a further electronic component, a first further die terminal, another die terminal, a second further die terminal, a thickness of the further semiconductor die corresponds to a thickness of the substrate, a cascode circuit, a half-bridge circuit, a conductive adhesive material between the clip lead and the substrate, a conductive adhesive material between the die terminal and the substrate, a conductive adhesive material between the semiconductor die and the die pad, a conductive adhesive material between the further clip lead and the second further die terminal, a leadframe comprising a die pad electrically connected the electronic component, a leadframe comprising a frame portion connected with a die pad, a plurality of the frame portions and die pads, a plurality of semiconductor device packages, must be shown or the feature(s) canceled from the Claims 1, 3, 4, 6, 8, 9, 11-14, 16, and 18-20. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the substrate" in Line 9. There is insufficient antecedent basis for this limitation in the claim. It is unclear if it is referring to “a stress relief substrate” in Line 6.
Claims 2-7 recite the limitation "The semiconductor device package" in Line 1. There is insufficient antecedent basis for this limitation in the claim. It is unclear if it is referring to “A leadframe-based semiconductor device package” in Line 1 of Claim 1.
Claims 3 and 8 recite the limitation "the substrate" twice in Lines 2 and 4-5. It is unclear if they are referring to “a stress relief substrate” in Line 6 of Claim 1 or “a die substrate” in Line 4 of Claim 3.
Claims 4 and 9 recite the limitation "the substrate" thrice in Lines 2, 5, and 9. It is unclear if it is referring to “a stress relief substrate” in Line 6 of Claim 1 or “the substrate” in Line 8 of Claim 1.
Claims 4 and 9 recite the limitation "conductive vias" in Line 6. It is unclear if it is referring to “a plurality of conductive vias” in Line 3.
Claim 4 recites the limitation “the conductive vias” in Line 6. It is unclear if it is referring to “a plurality of conductive vias” in Line 3 or “conductive vias” in Line 6.
Claims 4 and 9 recite the limitation "the group” in Line 7. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "polycrystalline material” in last line. It is unclear if it is referring to “polycrystalline material” in Line 9.
Claim 5 recites the limitation "the substrate" quadruple in Lines 3, 4, 6, and 8. It is unclear if it is referring to “a stress relief substrate” in Line 6 of Claim 1 or “the substrate” in Line 9 of Claim 1.
Claim 5 recites the limitation "the semiconductor device package" in Line 7. It is unclear if it is referring to “the semiconductor device package” in Line 1 or “A leadframe-based semiconductor device package” in Line 1 of Claim 1.
Claim 7 recites the limitation "the further clip lead" in Line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the further semiconductor die" in Line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the group” in Line 4. There is insufficient antecedent basis for this limitation in the claim.
Claims 8-11 recite the limitation "The semiconductor device package" in Line 1. It is unclear if it is referring to “A leadframe-based semiconductor device package” in Line 1 of Claim 1 or “The semiconductor device package” in Line 1 of Claim 2.
Claim 9 recites the limitation “the conductive vias” in Lines 6-7. It is unclear if it is referring to “a plurality of conductive vias” in Line 3 or “conductive vias” in Line 6.
Claim 9 recites the limitation "polycrystalline material” in last line. There is insufficient antecedent basis for this limitation in the claim. It is unclear if it is referring to “polycrystalline material” in Lines 9-10.
Claim 10 recites the limitation "the substrate" quadruple in Lines 3, 5, and 7. It is unclear if it is referring to “a stress relief substrate” in Line 6 of Claim 1 or “the substrate” in Line 9 of Claim 1.
Claim 10 recites the limitation "the semiconductor device package" in Line 6. It is unclear if it is referring to “the semiconductor device package” in Line 1 or “A leadframe-based semiconductor device package” in Line 1 of Claim 1.
Claim 12 recites the limitation "The semiconductor device package" in Line 1. It is unclear if it is referring to “A leadframe-based semiconductor device package” in Line 1 of Claim 1 or “The semiconductor device package” in Line 1 of Claim 6.
Claim 13 recites the limitation "The semiconductor device package" in Line 1. It is unclear if it is referring to “A leadframe-based semiconductor device package” in Line 1 of Claim 1 or “The semiconductor device package” in Line 1 of Claim 12.
Claim 13 recites the limitation "the conductive adhesive material" in Line 13. It is unclear if it is referring to “a conductive adhesive material” in Line 3, Line 5, Line 7, Line 9, and/or Lines 11-12 when one of “and/or” is “and”.
Claim 14 recites the limitation "the substrate" in Line 8. There is insufficient antecedent basis for this limitation in the claim. It is unclear if it is referring to “a stress relief substrate” in Line 6.
Claim 14 recites the limitation "the steps" in Line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "the substrate" quadruple in Lines 2-3, 3, 5, and 8-9. It is unclear if it is referring to “a stress relief substrate” in Line 6 of Claim 14 or “the substrate” in Line 8 of Claim 14.
Claim 15 recites the limitation "the steps" in Line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "the group" in Line 8 and the limitation “the frame portions” in Line 10. There is insufficient antecedent basis for these limitations in the claim.
Claim 17 recites the limitation "the further clip lead" in Line 2 and the limitation “the frame portion” in Line 4. There is insufficient antecedent basis for these limitations in the claim.
Claim 18 recites the limitation "the package material" in Line 11. There is insufficient antecedent basis for this limitation in the claim.
Claims 19 and 20 recite the limitation "the group" in Lines 2-3. There is insufficient antecedent basis for this limitation in the claim. It is unclear if it is referring to “the group” in Line 8 of Claim 16.
Claims 19 and 20 recite the limitation "the substrate" twice in Lines 5 and 6. It is unclear if it is referring to “a stress relief substrate” in Line 6 of Claim 14 or “the substrate” in Line 8 of Claim 14.
Claim 19 recites the limitation "the group" in Line 19. There is insufficient antecedent basis for this limitation in the claim. It is unclear if it is referring to “the group” in Lines 2-3 or “the group” in Line 8 of Claim 16.
Examiners have examined the
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Im et al. (Im hereinafter) (US 2021/0143107).
Regarding Claims 1, 2, 7, and 14:
Examiner has assumed “the substrate” is “the stress relief substrate” and “the semiconductor device package” is “the leadframe-based semiconductor device package” and “the steps” is “steps” when the rejections are made.
Im (see, paras. [0003], [0016]-[0018], [0022]-[0035], [0045] and FIGs. 2B, 2C, 4B) teaches {1} a leadframe-based semiconductor device package 100, comprising: a semiconductor die 120 having an electronic component integrated thereon and having a die terminal that is electrically connected to the electronic component; a stress relief substrate 110 fixedly and electrically connected 134/133/132/140 to the die terminal; a clip lead 130(132/133/134)/430(430a/430b/430c); and wherein the substrate is configured to provide an electrical short 134/133/132/140 between the clip lead and the die terminal; {2} the substrate 110 is configured to distribute a mechanical force exerted by the clip lead; {7} the clip lead and the further clip lead are gullwing-shaped 133 / (132c/132d) / (132a/132b) ; and/or wherein the semiconductor die and/or the further semiconductor die is based on one technology selected from the group consisting of Silicon, Silicon Carbide, Gallium Nitride, and Gallium Arsenide technology; and {14} a method for manufacturing a semiconductor device package 100, the method comprising the steps of: a) providing a semiconductor die 120 having an electronic component integrated thereon and having a die terminal that is electrically connected to the electronic component; b) providing a stress relief substrate 110 as defined in claim 1, and fixedly and electrically connecting 134/133/132/140 the substrate to the die terminal; and c) providing a clip lead 130(132/133/134) / 430(430a/430b/430c), wherein the substrate provides an electrical short 134/133/132/140 between the clip lead and the die terminal.
Im (see ¶ [0003], [0016], [0018], [0021], [0023], [0024], [0031], [0035], [0045]) teaches “controlling thickness of conductive adhesive layers (e.g., solder) to be sufficiently thick (e.g., to reduce thermal-mechanical stresses that can cause die cracks), but also prevent solder overflow”, “the use of the buffer legs … can prevent electrical shorts resulting from solder overflow, and can also reduce mechanical stresses … prevent die cracking and/or substrate cracking”, “the substrate 110 can be a direct-bonded metal (DBM) substrate, such as a direct-bonded-copper (DBC) substrate, that includes a dielectric layer and patterned metal layers disposed on the dielectric layer (e.g. on opposite surfaces of the dielectric layer)”, “the leadframe 130 also includes a plurality of buffer legs 134 that are configured to contact the substrate 110 and act as mechanical stops for the leadframe 130 when it is being coupled (e.g., soldered) to the semiconductor die 120 and and/or to the substrate 110”, “the indentation 132 of the leadframe 130 … can be coupled (directly coupled) with the semiconductor die 120”, “the semiconductor die 120 can be coupled to the metal 116 of the substrate 110 using a conductive adhesive (e.g., solder) layer 142 and the indentation 132 can coupled to the semiconductor die (e.g., a transistor, a diode, etc.) 120 using the conductive adhesive (e.g., solder) layer 140”, “the wire bonds 470 (along with signal leads of the leadframe 430) can provide electrical connections to the IGBT devices of the semiconductor dies 420a and 420c (e.g., with gate terminals, sense terminals, etc.)”, “the indentation 432a of the first leadframe portion 430a of the first leadframe portion 430a can be coupled (soldered) to an emitter terminal of the IGBT of the first semiconductor die 420a … the indentation 432c can be coupled (soldered) to an emitter terminal of the IGBT of the third semiconductor 420c”, and “semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Silicon Carbide (SiC) and/or so forth.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5, 8, 10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al. (Im hereinafter) (US 2021/0143107) as applied to claims 1, 2, and 14 above, and in view of Yoshihara et al. (Yoshihara hereinafter) (US 2016/0343590).
Regarding Claims 3, 5, 8, 10, and 15:
Examiner has assumed “the substrate” is “the stress relief substrate” and “the semiconductor device package” is “the leadframe-based semiconductor device package” and “the steps” is “steps” and “the further clip lead” is “a further clip lead” and “the further semiconductor die” is “a further semiconductor die” and “the group” is “a group” and “the step” is “step” when the rejections are made.
Im (see ¶ [0042] and FIGs. 1 and 2C) teaches a molding compound 150 encapsulate the package and the contact surface areas between the leadframe 130 and the conductive adhesive 140 and between the buffer legs 134 and the substrate 110 depicted smaller than the contact surface area between the conductive adhesive 140 and the semiconductor die 120.
Im does not explicitly teach {3} {8} the substrate is configured to bridge a difference between a coefficient of thermal expansion of the clip lead and a coefficient of thermal expansion of a die substrate of the semiconductor die, and wherein the substrate has a coefficient of thermal expansion that is lower than that of the clip lead; and {5} {10} {15} the clip lead comprises a second end that is arranged externally to the package material.
Yoshihara (see, paras. [0003], [0011], [0072]-[0073], and [0133]-[0135] and FIGs. 5, 18, 19, and 25A) teaches silicon carbide power devices having advantage over silicon power devices, “a leadframe electrically connected to the semiconductor device; and a stress buffering layer disposed on an upper surface of the semiconductor device, stress buffering layer capable of buffering a coefficient of thermal expansion (CTE) difference between the semiconductor device and the leadframe … a CTE of the stress buffering layer is equal to or less than a CTE of the leadframe”, the specific combination of the Si or SiC semiconductor device 1 having approximately 3x10-6 /K, Cu or Al leadframe 12 having approximately 17x10-6 /K or 24x10-6 /K and the stress buffer layer 10 having relative low CTE materials (8 ppm/K to 10 ppm/K) , e.g., Mo, W, CuMo, CuW, and a mold resin layer 33 formed in a power module 200 with a built-in half-bridge.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Im to include the teaching of Yoshihara to select different material for the conductive adhesive layer 140 with lower coefficient of thermal expansion for the same purpose to relief the stress between the semiconductor device and the leadframe besides having an underneath substrate contacting the buffer legs of the leadframe to relieve stress, to selectively encapsulate the semiconductor device package with mold resin so that the leadframe extends outside the mold resin which is the common practice in semiconductor package, and to use the semiconductor substrate materials for the semiconductor die since such materials are commonly used for transistors and other electronic components.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al. (Im hereinafter) (US 2021/0143107) as applied to claims 1 and 2 above, and in view of Kim (US 2014/0042608).
Regarding Claims 4 and 9:
Examiner has assumed “the substrate” is “the stress relief substrate” and “the semiconductor device package” is “the leadframe-based semiconductor device package” and “conductive vias” is “the plurality of conductive vias” and “the conductive vias” is “the plurality of conductive vias” and “the group” is “a group” and “the crystalline or polycrystalline material” is “the crystalline or the polycrystalline material” when the rejections are made.
Im does not explicitly teach the substrate comprises a dielectric material having arranged therein a plurality of conductive vias, wherein the clip lead is electrically connected to the die terminal through the plurality of conductive vias, wherein the substrate comprises a printed circuit board (PCB), including the dielectric material and conductive vias, wherein the conductive vias comprises a conductive material, selected from the group consisting of copper, gold, aluminum, tungsten, nickel and graphene; or wherein the substrate comprises a crystalline or polycrystalline material, wherein the clip lead is electrically connected to the die terminal through the crystalline or polycrystalline material.
Kim (see ¶ [0068]-[0073] and FIGs 3-8) teaches a lower semiconductor chip 140 having an active face 140a attached onto a lower printed circuit board (PCB) 120 having first, second, and third lower connection pads 122a, 122b,and 122c formed of Cu, Ni, or Au, a solder resist layer 126 on opposite surfaces of the PCB; a first solder layers 710a formed in the first through hole 510 in a first lower mold layer 162, and a second solder layer 720 in the second through hole 520 in a second lower mold layer 164 and teach “a lower base substrate 128 may be formed of a single layer or of a plurality of stacked thin substrates”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Im to include the teaching of Kim to form the conductive adhesive 140 with interlayer dielectric (ILD) technique commonly utilized in the interconnection structures by using printed circuit board with a plurality of connection vias.
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al. (Im hereinafter) (US 2021/0143107) as applied to claims 1 and 2 above, and in view of Palm et al. (Palm herein after) (US 2015/0228616).
Regarding Claims 6 and 11:
Examiner has assumed “the semiconductor device package” is “the leadframe-based semiconductor device package” when the rejections are made.
Im does not explicitly teach the die terminal is arranged in a metal layer of a layer stack on top of the semiconductor die, the layer stack comprising a stack of one or more metal layers, one or more intermetallic dielectric layers and one or more passivation layers; and/or wherein the semiconductor die is arranged on a die pad, wherein the die pad is conductive and electrically connected to the electronic component.
Palm (see, paras. [0033] and [0064]-[0067] and FIGs. 2G and 6G-7) teaches “first micro-vias connections extended through the electrically insulating material 212 from the terminals 208” and “second micro-via connections can be similarly formed which extend through the electrically insulating material 212”, and metal composite substrate electrically connected to a die 710 through a structured metal layer 720.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Im to include the teaching of Palm to form the die terminals with multilayered metal layers through vias in the insulating material and to connect the die with the metal layer within the substrate 110 which are commonly utilized in the interconnection structures of the semiconductor art.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al. (Im hereinafter) (US 2021/0143107) in view of Palm et al. (Palm herein after) (US 2015/0228616) as applied to claim 6 above, in view of Glenn et al. (Glenn herein after) (US 6,577,013), and further in view of Yoshihara et al. (Yoshihara hereinafter) (US 2016/0343590).
Regarding Claims 12 and 13:
Examiner has assumed “the substrate” is “the stress relief substrate” and “the semiconductor device package” is “the leadframe-based semiconductor device package” and “the conductive adhesive material” is any of the four “a conductive adhesive material” sandwiched between different parts when the rejections are made.
Im (see, paras. [0002], [0015]-[0016], and [0030]) teaches “power semiconductor devices (e.g., multi-chip packages or modules) can be implemented in package apparatus (e.g., semiconductor device packages, packages, modules, multi-chip modules, etc.) that can include multiple substrates, one or more conductive spacers, multiple semiconductor die, and three or more conductive adhesive layers (e.g., solder layers), which can be arranged in a stacked configuration” and the semiconductor die can include insulated-gate bipolar transistor (IGBT) or power transistor or diodes, but does not explicitly teach stacked semiconductor dies nor half-bridge circuit.
Glen (see Figs 1 and 8) teaches two or more of the singulated dies are stacked on top of one another and electrically connected to form a chip-size semiconductor package (CSP) with stacked dies. Yoshihara (see ¶ [0136] and FIGs. 16-25B) teaches power module 200 with built-in half-bridge in which a SiC Metal Oxide Semiconductor Field Effect Transistor (MISFET) applied as a semiconductor device.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Im in the device of Palm to include the teaching of Glenn to stack two semiconductor dies together and electrically connect them together to eliminate some of the manufacturing steps and to further include the teaching of Yoshihara to integrate power transistor with half-bridge circuit together in the same semiconductor device package for higher performance and more efficient use of space, to utilize proper thickness of the conductive adhesive layer between the each of the dies and leadframe, between the dies, and between any other two layers where the thermal-mechanical stress is observed, and to balance the leadframe on two sides (133, 132c, 132a) and (133, 132d, 132b) with stacked dies underneath one side and (multilayered ILD structure and die) underneath the other side to provide reliable and stable way for external connections.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al. (Im hereinafter) (US 2021/0143107) as applied to claim14 above, and in view of Thompson et al. (Thompson hereinafter) (US 2021/0398882).
Regarding Claims 16 and 17:
Examiner has assumed “the group” is “a group” and “a plurality of the frame portions” is “a plurality of frame portions” and “the clip lead and the further clip lead” is “the clip lead and a further clip lead” and “the frame portion” is “a frame portion” when the rejections are made.
Im (see ¶ [0029]-[0037] and FIGs. 4A-4E) teaches the leadframe 430 including a first leadframe portion 430a and a second leadframe portion 430b and indentations 432a-432d coupled the leadframe and the semiconductor dies 420a-420d, but does not explicitly teach singulating the semiconductor device package from the leadframe, by performing at least one action selected from the group consisting of punching, drilling, cutting and sawing.
However, Thompson (see ¶ [0030] and FIG. 1D) teaches the feet 126 on plating layers 128 and the singulation cuts separate the leadframe strip into separate IC packages and each IC package include a singulated leadframe, at least one die, electrical connections between the die and leadframe and the mold compound which covers at least part of these structure.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Im to include the teaching of Thompson to have different shape for the leadframe 130 formed on plating layers and to perform singulation cuts to separate the packages which has been commonly adopted by the semiconductor package industry.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al. (Im hereinafter) (US 2021/0143107) in view of Thompson et al. (Thompson hereinafter) (US 2021/0398882) as applied to claim 16 above, and in view of Glenn et al. (Glenn herein after) (US 6,577,013) and further in view of Yoshihara et al. (Yoshihara hereinafter) (US 2016/0343590).
Regarding Claims 18-20:
Examiner has assumed “the package material” is “a package material” and “the group” is “a group”, “the substrate” is “the stress relief substrate” when the rejections are made.
Im (see, paras. [0002], [0015]-[0016], and [0030]) teaches “power semiconductor devices (e.g., multi-chip packages or modules) can be implemented in package apparatus (e.g., semiconductor device packages, packages, modules, multi-chip modules, etc.) that can include multiple substrates, one or more conductive spacers, multiple semiconductor die, and three or more conductive adhesive layers (e.g., solder layers), which can be arranged in a stacked configuration” and the semiconductor die can include insulated-gate bipolar transistor (IGBT) or power transistor or diodes, but does not explicitly teach stacked semiconductor dies nor half-bridge circuit.
Glen (see, Figs 1 and 8) teaches two or more of the singulated dies are stacked on top of one another and electrically connected to form a chip-size semiconductor package (CSP) with stacked dies. Yoshihara (see, FIGs. 16-25B) teaches power module 200 with built-in half-bridge in which a SiC Metal Oxide Semiconductor Field Effect Transistor (MISFET) applied as a semiconductor device.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Im in the device and method of Thompson to include the teaching of Glenn to stack two semiconductor dies together and electrically connect them together to eliminate some of the manufacturing steps and to further include the teaching of Yoshihara to integrate power transistor with half-bridge circuit together in the same semiconductor device package for higher performance and more efficient use of space, to utilize proper thickness of the conductive adhesive layer between the each of the dies and leadframe, between the dies, and between any other two layers where the thermal-mechanical stress is observed. and to balance the leadframe on two sides (133, 132c, 132a) and (133, 132d, 132b) with stacked dies underneath one side and (multilayered ILD structure and die) underneath the other side to provide reliable and stable way for external connections.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814