DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 4 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Timme et al. (“Timme” US 2012/0086129) and Jin et al. (“Jin” US 2021/0366729).
Regarding claim 12, Timme discloses an electronic package, comprising:
a semiconductor die (10) having a first surface (top surface in Figure 3J) and an opposing second surface (lower surface), the semiconductor die (10) having a circuit integrated thereon (para. [0013] discloses types of integrated circuits in the semiconductor chip 10), wherein each of the first surface and the second surface has a respective terminal arranged thereon (first surface has terminals 27, second surface has terminal 25), the terminals being electrically connected to the circuit (each terminal is an electrode for the chip, and thus is electrically coupled to the integrated circuit, see para. [0026]);
a conductive element (28) spaced apart from the semiconductor die (10) and having a top surface and a bottom surface (see Figure 3J);
a body of solidified molding compound (13) at least partially encapsulating the semiconductor die (10) and the conductive element (28, see Figure 3J), the body of solidified molding compound (13) having a top side facing the first surface and a bottom side facing the second surface (see Figure 3J);
a first package terminal (42) at the top side that is electrically connected to the terminal at the first surface (42 is electrically connected to the terminals 27), and a second package terminal (43) at the top side that is electrically connected to the conductive element (28, 43 is electrically connected to 28);
a conductive layer (14, para. [0020]) electrically connecting the bottom surface of the conductive element (28) to the terminal arranged at the second surface (terminal 25) of the semiconductor die (10, see Figure 3J);
wherein the conductive element (28) is separately formed from the second package terminal (43) and the conductive layer (14, “separately formed” is interpreted to mean that the elements are not placed simultaneously, see Figures 3B, 3G, and 3I), and
Timme does not discloses wherein the first or second package terminal (42, 43, respectively) extends along a side wall of the body of solidified molding compound (13, the terminals extend on the upper side wall of the molding compound 13, see Figure 3J) to form a side-wettable flank of the electronic package, the side wall extending perpendicularly between the top side facing surface and the bottom side facing surface (see Figure 3J, which shows the terminals only extending along the top surface of the molding compound, not a lateral side surface extending from the top and bottom surfaces of the molding compound).
Jin discloses in Figure 11, however, a package terminal (30/70) extending along a side wall of the body of solidified molding compound (22, see Figure 11) to form a side-wettable flank of the electronic package (80), the side wall extending perpendicularly between the top side facing surface and the bottom side facing surface (of the molding compound 22, see Figure 11).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Jin into the teachings of Timme above to include the side-wettable flank extending along a lateral side surface of the molding compound for the purpose of allowing for easier inspection for defects (Jin, para. [0003]).
Regarding claim 13, Timme discloses wherein the second package terminal (43) is electrically connected to the conductive element (28) via an intermediate layer (40, see Figure 3J) and/or wherein the first package terminal (42) is electrically connected to the terminal at the first surface (27) via an intermediate layer (layer 40, see Figure 3J), and
wherein the intermediate layer (40) is a seed layer (para. [0039]) comprising a different material composition compared to at least one of the conductive element (28, materials listed in para. [0028], copper, aluminum, or a metal alloy), the first package terminal and the second package terminal (materials listed in para. [0027], thus Timme discloses an embodiment where in all three elements will have a different material composition), wherein the first package terminal (42 and/or the second package terminal (43) are electroplated terminals (terminals 42, 43 are formed by galvanic deposition, para. [0040]).
Note that although shown by the prior art, it is the position of the Office that the limitation “the first package terminal and/or the second package terminal are electroplated terminals” is a product-by-process limitation. Determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. See MPEP 2113.
Regarding claim 14, Timme discloses wherein the terminal arranged at the first surface (27) of the semiconductor die (10) comprises one or more conductive studs (27, metal layers para. [0027], interpreted to be conductive studs because the terminals 27 are conductive interconnects).
Regarding claim 15, Timme discloses wherein the conductive element (28) has a length along a direction from the bottom surface thereof to the top surface thereof (see Figure 3J), that is greater than a thickness of the semiconductor die (10) along the direction (see Figure 3J, para. [0024] and [0028] disclose overlapping thickness/height ranges for the conductive element 28 and the semiconductor die 10, however Figure 3J shows that the conductive element 28 has a greater height than the semiconductor die 10); and/or
wherein the electronic package further comprises a cover material encapsulating the conductive layer, wherein the cover material comprises a solidified molding compound or a solder mask; and/or
wherein the electronic package further comprises one or more interconnection elements extending from the conductive element to a side surface of the electronic package.
Regarding claim 17, Timme discloses wherein the conductive element (28) comprises a metal (para. [0028] discloses the conductive element metallic materials) or metal-coated post or pillar (28 is disclosed as a post); and/or
wherein the conductive element (28), when viewed in a direction from the bottom surface to the top surface (Figure 3J shows a cross-sectional view), has a substantially constant or increasing cross-sectional area along the direction (see Figure 3J, 28 has a constant thickness and thus cross-sectional area from bottom to top).
Regarding claim 18, Timme discloses wherein the first package terminal (27), the second package terminal (25) and/or the conductive layer (28) comprises at least one element selected from the group consisting of copper, aluminum, silver, gold, and tin (terminal 27 and conductive element 28 have embodiments in which they comprise one or more of the listed materials, see para. [0027]-[0028]);
wherein the first package terminal (42) and/or the second package terminal (43) are plated with a conductive solderable layer (the conductive solderable layer is interpreted to be the outer layer of the terminals 42, 43 because the instant specification, see para. [0031], discloses that a conductive solderable layer material can be tin, and in para. [0019] Timme discloses that solder material may be deposited on external contact pads, i.e. terminals 42, 43 thus Timme discloses the intended use of outer layers of terminals 42, 43 to be capable of being solderable); and/or
wherein the circuit integrated on the semiconductor die comprises:
a diode (para. [0026]) having a first terminal arranged at the first surface (terminals 24, 26) of the semiconductor die (10) and having a second terminal arranged at the second surface of the semiconductor die (electrode 25 at second surface of die 10); or
a transistor (para. [0026]) having a first (24) and third terminal (26) thereof arranged at the first surface of the semiconductor die (10), and having a second terminal (25) thereof arranged at the second surface of the semiconductor die (10), the electronic package comprising a third package terminal (44) at the top side that is electrically connected to the third terminal (26) at the first surface (see Figure 3J).
Regarding claim 19, Timme discloses wherein the body of solidified molding compound (13) has a recess for exposing the terminal at the first surface (27) of the semiconductor die (10, see Figure 3J, the recess is occupied by the terminal 27 and the molding compound 13 exposes the surface of the terminal 27 contacting the semiconductor die 10).
Response to Arguments
Applicant’s amendments filed March 4 2026, with respect to the 112 rejections of claim 12 have been considered and appear to overcome the 112 rejections. The 112 rejections of claim 12 have been withdrawn.
Applicant’s arguments with respect to the prior art rejection of claim 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights