DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe et al. (US 2018/0277746) in view of Noguchi et al. (US 2018/0040358).
Regarding claim 1: Abe (FIG. 5 using the memory cell 10A of FIG. 3, for example;
[0043-0051] and comprising structure of FIG. 6) teaches a device comprising:
a first spin-orbit torque line (left most 12 of region 213 in FIG. 6; a single 12 is illustrated in a memory cell of FIG. 2 or FIG. 3 or FIG. 5);
a write transistor (31 in FIG. 3) coupling a first end (left end in FIG. 3) of the spin-
orbit torque line to a first source line (WBL in FIG. 3 or WBL₀ in FIG. 5), the write transistor disposed at a first physical design level (level 200 in FIG. 6);
a source transistor (32 in FIG. 3) coupling a second end of the spin-orbit torque line
to a second source line (SL in FIG. 3 or SL₀ in FIG. 5); and
a plurality of magnetic tunnel junctions (memory elements 200-N in FIG. 3; an individual memory element is illustrated in FIG. 2, which is a magnetic tunnel junction MTJ, see [0043]; also are present along each line 12 in FIG. 6) coupled to the spin-orbit torque line, the magnetic tunnel junctions being in a current path between the write transistor and the source transistor ([0051]; FIG. 3), wherein the second source lines are disposed above the first spin-orbit torque line and the magnetic tunnel junctions, wherein the first spin-orbit torque line and the magnetic tunnel junctions are disposed above the first physical design level (FIG. 6); and
a second spin-orbit torque line (right most 12 of region 213 in FIG. 6).
Abe does not specifically teach the following:
the write transistor disposed at an active surface of a semiconductor substrate;
the source transistor disposed at an active surface of the semiconductor substrate
wherein the first source line and the second source line are disposed above the first spin-orbit torque line and the magnetic tunnel junctions, wherein the first spin-orbit torque line and the magnetic tunnel junctions are disposed above the semiconductor substrate;
a first interconnect between the first spin-orbit torque line and the second spin-orbit torque line, the first interconnect coupling the write transistor to the first source line; and
a second interconnect between the first spin-orbit torque line and the second spin- orbit torque line, the second interconnect coupling the source transistor to the second source line.
Noguchi (FIG. 9; [0147-0152]) teaches the following:
a write transistor (Qs or Qw) disposed at an active surface of a semiconductor substrate;
a source transistor (the other of Qs or Qw) disposed at an active surface of the semiconductor substrate, wherein a first source line (SBL or WBL) and a second source line (the other of SBL or WBL) are disposed above a first spin-orbit torque line and magnetic tunnel junctions, wherein the first spin-orbit torque line and the magnetic tunnel junctions are disposed above the semiconductor substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Noguchi into the device and/or method of Abe in a manner such that the source transistor 32 of Abe would be arranged in the lower physical design level 200 and connected to the end of a respective torque line like Abe already discloses in FIG. 3, the lower physical design level 200 would be a semiconductor substrate like that taught y Noguchi, and both the source lines and the bit lines of Abe would be arranged in physical design level or levels above the level 210 such they would be disposed above both the first and the second torque lines and their magnetic tunnel junctions as disclosed by Noguchi, wherein vertical connections or vias would then be needed and provided to connect a S/D terminal of each source transistor 32 to a source line above and vertical connections or vias would be needed and provided to connect a S/D terminal of each write transistor 31 to a bit line above. Note that considering that there is a transistor 32 now in a substrate having a first S/D terminal connected to the right end of the left most spin-torque line in region 213 of FIG. 6 of Abe along with a transistor 31 in the substrate having a first S/D terminal connected to the left end of the right most spin-torque line in region 213 of FIG. 6 then there would be a first via connection and a second via connection in physical level 210 between the first and second spin-torque lines for making the connection from a second S/D terminal of 31 and 32, respectively, to a bit line and a source line in a level or levels above 210. Hence, the following would be observed:
the write transistor would be disposed at an active surface of a semiconductor substrate;
the source transistor would be disposed at an active surface of the semiconductor substrate, wherein the first source line and the second source line would be disposed above the first spin-orbit torque line and the magnetic tunnel junctions, wherein the first spin-orbit torque line and the magnetic tunnel junctions would be disposed above the semiconductor substrate;
a first interconnect would be between the first spin-orbit torque line and the second spin-orbit torque line, the first interconnect coupling the write transistor to the first source line; and
a second interconnect would be between the first spin-orbit torque line and the second spin- orbit torque line, the second interconnect coupling the source transistor to the second source line.
The motivation to do so would have been to use an alternative physical design, wherein the source lines and bit lines are in physical levels or layers above a semiconductor substrate and above layers that comprise the spin-torque lines and the MTJs as exemplified by Noguchi. Integrated circuits are already commonly known to have layers stacked above a substrate, wherein multiple layers above the substrate include wiring levels for horizonal and vertical interconnects for intra-layer and inter-layer connections.
:
Regarding claim 2: Abe as modified above teaches the device of claim 1 further comprising:
access transistors (25) coupling the magnetic tunnel junctions to bit lines (BL), the access transistors disposed at the active surface of the semiconductor substrate, each of the access transistors coupling a respective one of the magnetic tunnel junctions to a respective one of the bit lines (illustrated in FIG. 5 or FIG. 6).
Regarding claim 3. Abe teaches the device of claim 2 further comprising:
a current source (120 in FIG. 5) coupled to the first source line and the second source line, the current source configured to provide a first write current to the first spin-orbit torque line during a programming operation; and
a bit line driver (120 in FIG. 5) coupled to the bit lines, the bit line driver configured to provide second write currents to the bit lines during the programming operation.
Regarding claim 4: Abe as modified above (Abe [0051]) discloses providing a write current to the first spin-orbit torque line but does not specifically teach the device of claim 3, wherein the current source provides the first write current to the spin-orbit torque line by setting the first source line (WBL) to a higher voltage than the second source line (SL).
Noguchi (FIG. 18A) teaches providing a write current to a spin-obit torque line by setting a first line WBL to a higher voltage than a second line SBL.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Noguchi into the device and/or method of Abe as modified above in a manner such that the current source would provide the first write current to the spin-orbit torque line by setting the first source line (WBL) to a higher voltage than the second source line (SL) like that taught by Noguchi such as applying VDD to WBL and VSS=0V to SL. The motivation to do so would have been to apply a suitable potential across the ends of the SOT line to provide the write current already disclosed by Abe.
Regarding 5: Abe teaches the device of claim 2 further comprising:
a bit line driver (120 in FIG. 5) coupled to the bit lines, the bit line driver configured to provide read currents during a read operation.
Regarding claim 6: Abe as modified above (Abe, [0057-0058]) teaches providing a read current by biasing WBL and SL to 0V while applying a VREAD voltage to a selected BL and 0V to unselected BLs such but does not specifically teach the bit line driver provides the read currents to the bit lines by setting a first subset of the bit lines to a greater voltage than the second source line and setting a second subset of the bit lines to a lesser voltage than the second source line.
Noguchi (FIG. 22; [0190]) teaches a read operation, wherein a read voltage Vdd_r is applied to a selected bit line and a Vinhibit_r is applied to unselected bit lines, wherein Noguchi states that Vinhibit_r is that does not urge the read current to be generated in the remaining bit lines.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Noguchi into the device and/or method of Abe as modified above in a manner such that the bit line driver would provide the read currents to the bit lines by setting a first subset of the bit lines to a greater voltage (a VREAD voltage like that disclosed by Abe or Vdd_r like that of Noguchi ) than the second source line (SL=0V or a voltage slight above 0V) and setting a second subset of the bit lines to a lesser voltage than the second source line (an appropriate Vinhibit_r voltage that does not urge a read current through the remaining bit lines, which are unselected in the read operation such as either a slightly negative voltage or one that is just slightly below the voltage applied to second source line SL).
Regarding 7: Abe teaches the device of claim 2, wherein gates of the access transistors, the write transistor, and the source transistor are coupled to a word line (see WL in FIG. 3 and FIG. 6).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe (2018/0277746 A1) as modified by Noguchi et al. (US 2018/0040358), and further in view of Nikitin (2019/0273202 A1).
Regarding 8: Abe as modified above does not specifically teach the device of claim 1, wherein the magnetic tunnel junctions are in-plane magnetic tunnel junctions.
Nikitin (20190273202; [0003]) teaches a magnetic tunnel junction in an SOT-MRAM may have in-plane magnetizations.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Nikitin into the device and/or method of Abe as modified above in a manner such that the magnetic tunnel junctions would be in-plane magnetic tunnel junctions. The motivation to do so would have been to use a conventional MTJ having in-plane magnetization as exemplified by Nikitin.
Regarding 9. Abe as modified above does not specifically teach the device of claim 1, wherein the magnetic tunnel junctions are perpendicular magnetic tunnel junctions.
Nikitin (20190273202; [0003]) teaches a magnetic tunnel junction in an SOT-MRAM may have perpendicular-to-plane magnetizations.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Nikitin into the device and/or method of Abe in a manner such that the magnetic tunnel junctions would be in-plane magnetic tunnel junctions. The motivation to do so would have been to use a conventional MTJ having perpendicular-to-plane magnetization as exemplified by Nikitin.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe (2018/0277746 A1) as modified by Noguchi et al. (US 2018/0040358), and further in view of Watanabe (20210098689 A1).
Regarding claims 10 and 11. Abe as modified above doee not specifically teach the device of claim 1, wherein the first spin-orbit torque line comprises a heavy metal and a light transition metal, wherein the heavy metal comprises platinum, palladium, or tungsten, and (regarding claim 11) wherein the light transition metal comprises scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, or copper
Watanabe ([0131]) teaches a spin orbit torque line E1 comprising an alloy of a heavy metal such as Pt or Pd and a transition metal, wherein W and Co are mentioned.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Watanabe into the device and/or method of Abe as modified above in a manner such that the first spin-orbit torque line would comprise an alloy of a heavy metal such as platinum Pt or palladium Pd and a light transition metal such as cobalt Co. The motivation to do so would have been to use specific elements already known to be suitable for use in an SOT type layer as exemplified by Watanabe, and known by one or ordinary skill in the art using the periodic table.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe (2018/0277746 A1) in view of Noguchi et al. (US 2018/0040358) and Watanabe (20210098689 A1).
Regarding claim 12: Abe teaches a device comprising:
a first spin-orbit torque line (left most 12 of region 213 in FIG. 6; a single 12 is illustrated in a memory cell of FIG. 2 or FIG. 3 or FIG. 5) over a first physical design level (200);
first magnetic tunnel junctions coupled to the first spin-orbit torque line (memory elements 200-N in FIG. 3; an individual memory element is illustrated in FIG. 2, which is a magnetic tunnel junction MTJ, see [0043]; also these MTJs 200-7 are present along each line 12 in FIG. 6), the first magnetic tunnel junctions spaced apart along the first spin-orbit torque line (FIG. 6);
a first interconnect coupling the first spin-orbit torque line to the first physical design level (see electrical connection represented by a dashed line from each 31 to a respective end of each spin-torque line 12 in FIG. 6);
a second spin-orbit torque line (right most 12 of region 213 in FIG. 6) over the first physical design level;
second magnetic tunnel junctions coupled to the second spin-orbit torque line (another series of MTJS 200-7 of MTJs as seen in FIG. 6);
bit lines (BL) below the first magnetic tunnel junctions and the second magnetic tunnel junctions (see FIG. 6).
Abie does not specifically teach the following:
the first spin-orbit torque line over a semiconductor substrate;
the first interconnect coupling the first spin-orbit torque line to the semiconductor substrate
a second interconnect coupling the first spin-orbit torque line to the semiconductor substrate;
the second spin-orbit torque line over the semiconductor substrate
bit lines above the first magnetic tunnel junctions and the second magnetic tunnel junctions; and
third interconnects between the first spin-orbit torque line and the second spin-orbit torque line, the third interconnects coupling the bit lines to the semiconductor substrate.
Noguchi (FIG. 9; [0147-0152]) teaches the following:
a write transistor (Qs or Qw) disposed at an active surface of a semiconductor substrate;
a source transistor (the other of Qs or Qw) disposed at an active surface of the semiconductor substrate, wherein a first source line (SBL or WBL) and a second source line (the other of SBL or WBL) are disposed above a first spin-orbit torque line and magnetic tunnel junctions, wherein the first spin-orbit torque line and the magnetic tunnel junctions are disposed above the semiconductor substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Noguchi into the device and/or method of Abe in a manner such that the source transistor 32 of Abe would be arranged in the lower physical design level 200 and connected to the end of a respective torque line like Abe already discloses in FIG. 3, the lower physical design level 200 would be a semiconductor substrate like that taught y Noguchi, and both the source lines and the bit lines of Abe would be arranged in physical design level or levels above the level 210 such they would be disposed above both the first and the second torque lines and their magnetic tunnel junctions as disclosed by Noguchi, wherein vertical connections or vias would then be needed and provided to connect a S/D terminal of each source transistor 32 to a source line above and vertical connections or vias would be needed and provided to connect a S/D terminal of each write transistor 31 to a bit line above. Note that considering that there is a transistor 32 now in a substrate having a first S/D terminal connected to the right end of the left most spin-torque line in region 213 of FIG. 6 of Abe along with a transistor 31 in the substrate having a first S/D terminal connected to the left end of the right most spin-torque line in region 213 of FIG. 6 then there would be a first via connection and a second via connection in physical level 210 between the first and second spin-torque lines for making the connection from a second S/D terminal of 31 and 32, respectively, to a bit line and a source line in a level or levels above 210. Hence, the following would be observed:
the first spin-orbit torque line would be over a semiconductor substrate;
the first interconnect would be coupling the first spin-orbit torque line to the semiconductor substrate
a second interconnect would be coupling the first spin-orbit torque line to the semiconductor substrate;
the second spin-orbit torque line would be over the semiconductor substrate
bit lines would be above the first magnetic tunnel junctions and the second magnetic tunnel junctions; and
third interconnects would be between the first spin-orbit torque line and the second spin-orbit torque line, the third interconnects coupling the bit lines to the semiconductor substrate.
The motivation to do so would have been to use an alternative physical design, wherein the source lines and bit lines are in physical levels or layers above a semiconductor substrate and above layers that comprise the spin-torque lines and the MTJs as exemplified by Noguchi. Integrated circuits are already commonly known to have layers stacked above a substrate, wherein multiple layers above the substrate include wiring levels for horizonal and vertical interconnects for intra-layer and inter-layer connections.
Abe as modified above does not specifically teach the first spin-orbit torque line comprising an alloy of a heavy metal and a light transition metal.
Watanabe ([0131]) teaches a spin orbit torque line E1 comprising an alloy of a heavy metal such as Pt or Pd and a transition metal, wherein W and Co are mentioned.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Watanabe into the device and/or method of Abe as modified above in a manner such that the first spin-orbit torque line would comprise an alloy of a heavy metal such as platinum Pt or palladium Pd and a light transition metal such as cobalt Co. The motivation to do so would have been to use specific elements already known to be suitable for use in an SOT type layer as exemplified by Watanabe, and known by one or ordinary skill in the art using the periodic table.
Regarding claim 13: Abe (FIG. 6) teaches the device of claim 12, wherein the first magnetic tunnel junctions are disposed below the first spin-orbit torque line.
Regarding claim 14: Abe as modified above (FIG. 6 of Abe) teaches the device of claim 13 further comprising:
fourth interconnects beneath the first magnetic tunnel junctions, the fourth interconnects coupling the first magnetic tunnel junctions to the semiconductor substrate (see the dashed lines between each MTJ and level 200 or semiconductor substrate).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe (2018/0277746 A1) as modified by Noguchi et al. (US 2018/0040358) and Watanabe (20210098689 A1), and further in view of Saito et al. (US 2019/0088860).
Regarding claim 15: Abe teaches device of claim 12, wherein the first magnetic tunnel junctions are disposed below the first spin-orbit torque line.
Abe does not specifically teach device of claim 12, wherein the first magnetic tunnel junctions are disposed above the first spin-orbit torque line.
Saito (FIG. 15) teaches magnetic tunnel junctions being disposed above a spin-torque line with a physical design layer comprising transistors being on a level below the spin-torque line.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Watanabe into the device and/or method of Abe as modified above in a manner such that the first magnetic tunnel junctions would be disposed above the first spin-orbit torque line. The motivation to do would have been to use an alternative order of the design layers, one with the MTJs being disposed on the other side of the spin-torque line opposite the side of the lower physical design level or semiconductor substrate having the transistors.
Regarding claim 16: Abe as modified above teaches the device of claim 15 further comprising:
fourth interconnects above the first magnetic tunnel junctions, the fourth interconnects coupling the first magnetic tunnel junctions to the semiconductor substrate (due to the modification above, each of the interconnects indicated by a dashed line between a respective MTJ and a transistor 25 now would be reaching up and around to connected to the MTJ terminal; hence, there would an interconnect above each MTJ for coupling the MTJ to the transistor 25 in the semiconductor substrate).
Claim(s) 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe (2018/0277746 A1) in view of Noguchi et al. (US 2018/0040358) and Saito et al. (US 2019/0088860).
Regarding claim 18: Abe (FIG. 6) teaches a method comprising:
forming a first metallization layer of an interconnect structure (the dashed lines connecting transistors in physical design level 200 to level 210 may be referred to as a first metallization layer) over a first physical design level, the first metallization layer comprising first interconnects, the first physical design level comprising access transistors (25);
forming a second metallization layer of the interconnect structure (210) over the first metallization layer, the second metallization layer comprising a spin-orbit torque line (any one of the spin-torque lines 12), magnetic tunnel junctions (20), each of the magnetic tunnel junctions contacting a respective portion of the spin-orbit torque line; and
forming a third metallization layer of the interconnect structure (220) over the second metallization layer, the third metallization layer comprising source lines, wherein each of the magnetic tunnel junctions is coupled to a respective one of the bit lines through a respective one of the access transistors.
Abe does not specifically teach:
forming a first metallization layer of an interconnect structure over a semiconductor substrate, the first metallization layer comprising first interconnects, the semiconductor substrate comprising access transistors;
forming a second metallization layer of the interconnect structure over the first metallization layer, the second metallization layer comprising a spin-orbit torque line, magnetic tunnel junctions, and second interconnects, each of the magnetic tunnel junctions contacting a respective portion of the spin-orbit torque line; and
forming a third metallization layer of the interconnect structure over the second metallization layer, the third metallization layer comprising bit lines, the first interconnects and the second interconnects interconnecting the bit lines, the magnetic tunnel junctions, the spin- orbit torque line, and the access transistors such that each of the magnetic tunnel junctions is coupled to a respective one of the bit lines through a respective one of the access transistors.
Noguchi (FIG. 9; [0147-0152]) teaches the following:
a write transistor (Qs or Qw) disposed at an active surface of a semiconductor substrate;
a source transistor (the other of Qs or Qw) disposed at an active surface of the semiconductor substrate, wherein a first source line (SBL or WBL) and a second source line (the other of SBL or WBL) are disposed above a first spin-orbit torque line and magnetic tunnel junctions, wherein the first spin-orbit torque line and the magnetic tunnel junctions are disposed above the semiconductor substrate.
Saito (FIG. 15) teaches magnetic tunnel junctions being disposed above a spin-torque line with a physical design layer comprising transistors being on a level below the spin-torque line.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Noguchi into the device and/or method of Abe in a manner such that the MTJs would be formed either above or below each spin-torque line since Abe already teaches disposing them above and Saito teaches disposing them below (two alternatives), the source transistor 32 of Abe would be arranged in the lower physical design level 200 and connected to the end of a respective torque line like Abe already discloses in FIG. 3, the lower physical design level 200 would be a semiconductor substrate like that taught y Noguchi, and both the source lines and the bit lines of Abe would be arranged in physical design levels above the level 210 such they would be disposed above both the first and the second torque lines and their magnetic tunnel junctions, wherein vertical connections or vias would connect a S/D terminal of each source transistor 32 to a source line above and vertical connections or vias would connect a S/D terminal of each write transistor 31 to a bit line above. Note that considering that there is a transistor 32 now in a substrate having a first S/D terminal connected to the right end of the left most spin-torque line in region 213 of FIG. 6 of Abe along with a transistor 31 in the substrate having a first S/D terminal connected to the left end of the right most spin-torque line in region 213 of FIG. 6 then there would be a first via connection and a second via connection in physical level 210 between the first and second spin-torque lines for making the connection from a second S/D terminal of 31 and 32, respectively, to a bit line and a source line, respectively, above the level 210. Hence, the following would be observed:
a first metallization layer of an interconnect structure would be formed over a semiconductor substrate, the first metallization layer comprising first interconnects, the semiconductor substrate comprising access transistors;
a second metallization layer of the interconnect structure would be formed over the first metallization layer, the second metallization layer comprising a spin-orbit torque line, magnetic tunnel junctions, and second interconnects, each of the magnetic tunnel junctions contacting a respective portion of the spin-orbit torque line; and
a third metallization layer of the interconnect structure would be formed over the second metallization layer, the third metallization layer comprising bit lines, the first interconnects and the second interconnects interconnecting the bit lines, the magnetic tunnel junctions, the spin- orbit torque line, and the access transistors such that each of the magnetic tunnel junctions would be coupled to a respective one of the bit lines through a respective one of the access transistors.
The motivation to do so would have been to use an alternative physical design, wherein the source lines and bit lines are in a physical level or levels above a semiconductor substrate and above levels that comprise the spin-torque lines and the MTJs as exemplified by Noguchi, wherein the MTJs may be disposed either above or below a spin-torque line. Integrated circuits are already commonly known to have layers stacked above a substrate, wherein multiple layers above the substrate include metal wiring levels for horizonal and vertical interconnects for intra-layer and inter-layer connections.
Regarding claim 19: Abe as modified above teaches the method of claim 18, wherein the magnetic tunnel junctions are formed below the spin-orbit torque line (FIG. 6 of Abe).
Regarding claim 20: Abe as modified above teaches the method of claim i8, wherein the magnetic tunnel junctions are formed above the spin-orbit torque line (an alternative design as taught by Saito in the modification above).
Regarding claim 21: Abe as modified above teaches the method of claim i8, wherein the semiconductor substrate further comprises a source transistor (32 from FIG. 3 of Abe but now in the semiconductor substrate 200 in FIG. 6 as modified by Noguchi), the third metallization layer further comprises a source line, and the first interconnects and the second interconnects further interconnect the source transistor and the source line such that the spin-orbit torque line is coupled to the source line through the source transistor (see modification above).
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because new grounds of rejection are being made.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827