Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Species AA in the reply filed on 11/20/25 is acknowledged.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected product/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/20/25.
Priority
The instant application contains additional disclosure not presented in the previous applications in the family and therefore the claims have different priority dates based on when the subject matter was disclosed. It is noted that figures 26B-86 were not included in application 16/849600 and figures 41-78B were not included in application 17/090420, and Figures 63-78B were not included in application 17/543987, and figures 69-78B are not included in application 18/145275.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 8-10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 and 13 of copending Application No. 18/344411 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because they contain the same subject matter.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Eom et al. (US PGPub 2020/0388686) in view of Choi et al. (US PGPub 2021/0388686).
Claim 1: Eom teaches a method of forming a memory device, comprising: forming an alternating stack of disposable material layers (13) and silicon nitride layers (12) over a substrate (Fig. 10A); forming a memory opening (14) through the alternating stack (Fig. 10B); forming a memory film (15, 16) and a vertical semiconductor channel (17) in the memory opening, wherein the memory film comprises a continuous silicon nitride charge storage material layer and a tunneling dielectric layer [0138] (Fig. 10C); forming a backside trench (21) through the alternating stack (Fig. 10D); forming laterally-extending cavities (22) by removing the disposable material layers (13) selective to the silicon nitride layers through the backside trench (Fig. 10E); oxidizing portions of the continuous silicon nitride charge storage material layer [0146] (Fig. 10E) exposed in the laterally-extending cavities to form silicon oxide insulating layers and to separate the continuous silicon nitride charge storage material layer; and replacing remaining portions of the silicon nitride layers with electrically conductive layers (28A) (Fig. 10H-10I). Eom does not teach oxidizing portions of the silicon nitride layers, or that the oxidation separates the continuous silicon nitride charge storage material into a vertical stack of discrete silicon nitride charge storage material portions. Choi teaches oxidizing portions of the remaining alternating insulating layer, the oxidation separating the continuous silicon nitride charge storage material into a vertical stack of discrete silicon nitride charge storage material portions (134P) (Fig. 12K) [0134] to prevent cell interference due to charge diffusion between cells [0004].Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the method taught by Eom to have included oxidizing the SiN layer and creating a discrete charge storage pattern to improve device performance as taught by Choi [0004].
Claim 2: Choi teaches (Fig. 12K) the portions of the continuous silicon nitride charge storage material layer that are exposed in the laterally-extending cavities are converted into a vertical stack of annular silicon oxide material portions (162A) during the oxidizing; and the vertical stack of discrete silicon nitride charge storage material portions (134P/D) is interlaced with the vertical stack of annular silicon oxide material portions along a vertical direction.
Claim 3: Choi teaches (Fig. 12K) the portions of the silicon nitride layers that are exposed in the laterally-extending cavities are converted into silicon oxide material portions that expand in volume to fill the laterally-extending cavities.
Claim 4: Choi teaches (Fig. 12K) laterally recessing the silicon oxide material portions, wherein remaining parts of the silicon oxide material portions that fill the laterally- extending cavities comprise the silicon oxide insulating layers.
Claim 5: Choi teaches (Fig. 12K) the memory film further comprises a blocking dielectric layer (132B).
Claim 6: Choi teaches (Fig. 12D-E) removing portions of the blocking dielectric layer exposed in the laterally-extending cavities, wherein remaining portions of the blocking dielectric layer comprise a vertical stack of tubular insulating spacers.
Claim 9: Choi teaches (Fig. 4B, 7, 9) an air gap (AG1/2/3) is formed in each of the silicon oxide insulating layers during the oxidation.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach thinning the oxide to remove a bird’s beak issue.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814