DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11, 24-28 & 36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 24 & 36 recite the limitation “the conductive routing disposed between the bottom surface of the interposer substrate and the first shielding film”. This limitation raises ambiguity as the conductive routing 256A (e.g. Fig. 1-2) is not between the bottom surface 350BS of the interposer 350A/B and the first shielding film 356A. It is rather the first shielding film 330A/B that is between the conductive routing 356A and the bottom surface 350BS of the interposer 350A/B (see Applicant’s Fig. 2), and in a different embodiment shown in Fig. 1, the bottom surface 350BS is shown to be between the conductive routing 356A and the first shielding film 330A (Applicant’s Fig. 1). Correction/clarification is required.
Claims 2-11 & 25-29 are rejected for being dependent on independent claims 1 & 24.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As best understood, claims 1-6, 8-11, 24-29 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over CHUANG et al. (US PUB. 2020/0075503) in view of TSAI et al. (US PUB. 2021/0125961).
Regarding claim 1, CHUANG teaches a semiconductor package assembly, comprising:
a base 100 (Fig. 1E);
a first system-on-chip (SOC) die 110A (Fig. 1C) disposed on the base and having a front surface (bottom surface) and a back surface (top surface, see Fig. 1E);
a conductive routing disposed on the back surface of the first SOC die 110A (see Fig. 1E below); and
a first shielding film 208 disposed between the first SOC die 110A and the conductive routing, wherein the first shielding film 208 covers the back surface of the first SOC die 110A (see Fig. 1E below), and
an interposer 20 disposed on the back surface of the first SOC die 110A (e.g. Fig. 1C), wherein the interposer 20 comprises: an interposer substrate 200 having a top surface away from the first SOC die 110A and a bottom surface close to the first SOC die 110A (Fig.1E); and
the conductive routing disposed between the bottom surface (e.g. top surface of 20) of the interposer substrate and the first shielding film 208 (see Fig. 1E).
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CHUANG is silent on wherein the first Soc die 110A comprises a first inductor close to the front surface; and the first shielding film 208 fully overlaps the first inductor.
TSAI teaches in Fig. 1 a SOC die that includes inductor/s (Para [0056 & 0073]), perhaps close to the front surface near the conductive connectors 142 for electrical connection. In addition to storing energy, one of the advantages of inductors is to separate signals of different frequencies. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of CHUANG with the SOC die including inductors, as taught by TSAI, so as to provide energy storage and separating signals of different frequencies. Furthermore, TSAI’s inductors, one incorporated into CHUANG’s SoC die will be fully overlapped by the shielding film 208.
Regarding claim 2, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 1, wherein the first shielding film 208 is electrically floating (Fig. 1E). Furthermore, the limitation that “the first shielding film is electrically floating", is a recitation of the intended use of the claimed invention, and such use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 3, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 1, wherein the shielding film 228 is electrically connected to a ground (GND) terminal (Fig. 1E). Furthermore, the limitation that “the first shielding film is electrically connected to a ground (GND) terminal", is a recitation of the intended use of the claimed invention, and such use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 4, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 1, wherein the first shielding film 208 overlaps the conductive routing (Fig. 1E).
Regarding claim 5, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 1, wherein the conductive routing overlaps the first inductor (Fig. 1E).
Regarding claim 6, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 1, wherein the first shielding film 208 fully covers the back surface of the first SOC die 110A (Fig. 1E).
Regarding claim 8, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 1, wherein the first SOC die 110A/140 further comprises a second inductor close to the first inductor and disposed close to the front surface, wherein the first inductor and the second inductor collectively form a transformer (TSAI teachers that the SOC die comprises multiple inductors and two inductors can form/operate as a transformer, Para [0073]).
Regarding claim 9, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 1, wherein the first SOC die 110a/140 and the conductive routing are included in a first system-on-chip (SOC) package (CHUANG’s Fig. 1E and TSAI’s Fig. 9).
Regarding claim 10, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 9, wherein the first SOC package further comprises:
a first substrate 102 disposed on the front surface of the first SOC die 110A and electrically connected to pads of the first SOC die 110A, wherein the pads are disposed on the front surface of the first SOC die 110A (see CHUANG’s Fig. 1E).
Regarding claim 11, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 10, wherein the first shielding film 208 is formed as a conductive plane in the interposer 200 (CHUANG’s Fig. 1E).
Regarding claim 24, CHUANG teaches semiconductor package assembly, comprising:
a base 100 (Fig. 1E);
a first system-on-chip (SOC) die 110A disposed on the base 100 (Fig. 1C & Fig. 1E);
a conductive routing disposed on the first SOC die 110A in a direction of a vertical projection to the first SOC die 110A (see Fig. 1E above); and
a first shielding film 208 disposed between the first SOC die 110A and the conductive routing, wherein the first shielding film 208 is in the direction of a vertical projection to the first SOC die 110A (see Fig. 1E above), and
an interposer 20 disposed on the back surface of the first SOC die 110A (e.g. Fig. 1C), wherein the interposer 20 comprises:
an interposer substrate 200 having a top surface away from the first SOC die 110A and a bottom surface close to the first SOC die 110A (Fig.1E); and
the conductive routing disposed between the bottom surface (e.g. top surface of 20) of the interposer substrate and the first shielding film 208 (see Fig. 1E).
CHUANG is silent on wherein the first Soc die 110A comprises a first inductor therein; and the first shielding film 208 fully overlaps the first inductor; and wherein the first shielding film 208 fully overlaps the first inductor.
TSAI teaches in Fig. 1 a SOC die that includes inductor/s (Para [0056 & 0073]), therein. In addition to storing energy, one of the advantages of inductors is to separate signals of different frequencies. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of CHUANG with the SOC die including inductors, as taught by TSAI, so as to provide energy storage and separating signals of different frequencies. Furthermore, TSAI’s inductors, one incorporated into CHUANG’s SoC die will be fully overlapped by the shielding film 208 and overlapped by the conductive routing.
Regarding claim 25, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 24, wherein the first shielding film 208 is electrically floating or electrically connected to a ground (GND) terminal (Fig. 1E). Furthermore, the limitation that “the first shielding film is electrically floating or electrically connected to a ground (GND) terminal", is a recitation of the intended use of the claimed invention, and such use must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Regarding claim 26, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 24, wherein the first shielding film 208 overlaps the conductive routing (Fig. 1E).
Regarding claim 27, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 24, wherein the first SOC die 110A/140 comprises a transformer composed of the first inductor and a second inductor, wherein the first shielding film 208 fully overlaps the transformer in the direction of a vertical projection to the first SOC die (TSAI teachers that the SOC die comprises multiple inductors and two inductors can operate as a transformer, Para [0073]).
Regarding claim 28, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 24, further comprising:
a first SOC package (the package layer comprising the dies 110A & 110B), comprising:
the first SOC die 110A; and
a first substrate 102 disposed on the front surface of the first SOC die 110A and electrically connected to pads of the first SOC die 110A, wherein the pads are close to the first inductor (it is understood that the pads are positioned close to the inductors for electrical connection, see CHUANG’s Fig. 1E and TSAI’s Fig. 9).
Regarding claim 29, the combination of CHUANG and TSAI teaches the semiconductor package assembly as claimed in claim 28, wherein the first shielding film 208 is formed as a conductive plane in the interposer (Fig. 1E).
Regarding claim 36, CHUANG teaches a semiconductor package assembly, comprising:
a base (Fig. 1E);
a system-on-chip (SOC) die 110A disposed on the base 100;
a conductive routing disposed on the SOC die 110A and in a direction of a vertical projection to the SOC die, wherein the conductive routing is used to transmit signals (see Fig. 1E above); and
a shielding film 208 disposed between the SOC die 110A and the conductive routing, wherein the shielding film 208 is electrically floating or electrically connected to a ground (GND) terminal, and wherein the shielding film is in the direction of a vertical projection to the SOC die, and
an interposer 20 disposed on the back surface of the first SOC die 110A (e.g. Fig. 1C), wherein the interposer 20 comprises:
an interposer substrate 200 having a top surface away from the first SOC die 110A and a bottom surface close to the first SOC die 110A (Fig.1E); and
the conductive routing disposed between the bottom surface (e.g. top surface of 20) of the interposer substrate and the first shielding film 208 (see Fig. 1E).
CHUANG is silent on wherein the first Soc die 110A comprises a first inductor therein; and the first shielding film 208 fully overlaps the first inductor; and wherein the first shielding film 208 fully overlaps the first inductor.
TSAI teaches in Fig. 1 a SOC die that includes inductor/s (Para [0056 & 0073]), therein. In addition to storing energy, one of the advantages of inductors is to separate signals of different frequencies. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of CHUANG with the SOC die including inductors, as taught by TSAI, so as to provide energy storage and separating signals of different frequencies. Furthermore, TSAI’s inductors, one incorporated into CHUANG’s SoC die will be fully overlapped by the shielding film 208 and overlapped by the conductive routing.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over CHUANG and TSAI as applied to claim 1 above, and further in view of Oliveira et al. (US PUB. 2014/0015614).
Regarding claim 7, the combination of CHUANG and TSAI is silent on the semiconductor package assembly as claimed in claim 1, wherein the first shielding film partially covers the back surface of the first SOC die (Fig. 1E). However, Oliveira teaches in Para [0035], wherein a shielding film can either fully or partially cover the back surface of a die. This has the advantages of offering multiple design choice for shielding layer implementation. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of CHUANG and TSAI with the shielding layer, as taught by Oliveira, so as to implement a shielding layer in selected areas within a semiconductor device.
Response to Arguments
Applicant's arguments filed on 10/18/2025 have been fully considered but they are not persuasive. Regarding claims 1, 24 & 36, first, the amended limitation raises ambiguity as it contradicts the structures shown in Fig 1-2 and in the new/replacement sheets (see 112b rejection above). As best understood, the prior art continues to read on the claims as addressed in the rejection above. As such, the argument is not found to be persuasive
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818