DETAILED ACTION
This non-final action is responsive to communications: 10/06/2025.
In the response filed, claims 1, 14, and 20 are amended; claim 11 is canceled, and no new claims are cancelled or added. Claims 1-10 and 12-20 are now pending. Claims 1 and 14 are independent.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/06/2025 has been entered.
Examiner Notes
A) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. B) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. C) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. See ADS, no priority is in the record.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1-10, and 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention. See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968). Such essential matter may include missing elements (circuitry components essential for function), steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For example, for In re Mayhew, the Court of Customs and Patent Appeals (CCPA) held that claims were not enabled under 35 U.S.C. § 112 because they omitted a cooling bath and its specific location, which were deemed essential elements based on the specification. The court found that the specification indicated these elements were critical for the invention to function as described, and their omission from the claims rendered them not supported by an enabling disclosure.
For independent claims 1 and 14, omitted elements and omitted essential structural cooperative relationships of elements (in association with underlined limitations) are described in bold:
SRAM memory bank comprises a plurality of memory sub-banks. See para [0014], [0020], [0024], Fig. 1, Fig. 4 describes sub-bank (and bank) and the component is essential for utilizing the described precharge scheme and overall circuitry does not function fully without this element, structure since sub-banks are target for precharge using the describe precharge signal input.
SRAM access control circuit comprises a plurality of flip flops for storing plurality of pre-charge signal inputs. See para [0020], [0028], Fig. Fig. 4 describes flip flops and the component is critical, essential for the function of precharge signal and precharge scheme and overall circuitry does not function in meaningful way without this component. The specific precharge signal can not be stored and propagated without this component.
Pre-charge signal comprises one or more bits and the number of bits is equal to a number of the plurality of memory sub-banks. See para [0016], [0020] describes the nature of pre-charge signal, relation to sub-banks and the functional description is essential for understanding the functions of the overall circuitry. Structure and function described in association with this feature are critical because such enables critical function of the overall circuitry.
Claim 1. A static random-access memory (SRAM) circuit comprising:
an SRAM memory bank (1 above is missing) configured to store bits of data, the SRAM memory bank comprising a plurality of bit lines; and
an SRAM access control circuit (2 above is missing) coupled to the plurality of bit lines of the SRAM memory bank,
the SRAM access control circuit configured to pre-charge the plurality of bit lines to access the stored bits of data,
wherein the SRAM access control circuit receives, at a pre-charge request input, and stores a pre-charge signal (3 above is missing) for a subsequent cycle while the SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on a current cycle, and
wherein the SRAM access control circuit comprises a pre-charge-reset input to clear the pre-charge on the plurality of bit lines and to clear pre-charge signals stored in the SRAM access control circuit.
Claim 14. A method of,
receiving, at a pre-charge request input, and storing, by an SRAM access control circuit, a pre-charge signal (3 above is missing) at an SRAM memory bank (1 above is missing);
storing the pre-charge signal while an SRAM access control circuit (2 above is missing) is accessing stored bits of data in the SRAM memory bank on a current cycle; and
pre-charging, by the SRAM access control circuit, a plurality of bit lines of the SRAM memory bank based on the pre-charge signal to access stored bits of data of the SRAM memory bank,
wherein the SRAM access control circuit comprises a pre-charge-reset input to clear the pre-charge on the plurality of bit lines and to clear pre-charge signals stored in the SRAM access control circuit.
Without these description mentioned, scope of claimed apparatus or claimed method are vague, unclear. Claims must be clear enough to understand the boundaries of the invention. This requires the scope to be precise and unambiguous. See art rejection for the interpretation of the art rejected claims.
All dependent claims inclusive of Claims 1-10, 12-20 are rejected under this category. See art rejection for the interpretation of the art rejected claims.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 1-4, 6-9, and 12-20 is/are rejected under 35 U.S.C. 103 as being obvious over Chai et al. (US 2014/0328113 A1), in view of ARSOVSKI et al. (US 2017/0352407 A1) and Mendoza et al. (US 2004/0204162 A1).
Regarding independent claim 1, Chai teaches a static random-access memory (SRAM) circuit (Fig. 5 “SRAM Cache”) comprising:
an SRAM memory bank (Fig. 5: 46 “data array”) configured to store bits of data (para [0006]), the SRAM memory bank comprising a plurality of bit lines (para [0020]); and
an SRAM access control circuit (Fig. 5: 56’, 66 combined) coupled to the plurality of bit lines of the SRAM memory bank (Fig. 5: coupled to data array and bit lines),
the SRAM access control circuit (Fig. 5: 56’, 66 combined) configured to pre-charge the plurality of bit lines to access the stored bits of data (para [0020]),
wherein the SRAM access control circuit (Fig. 5: 56’, 66) receives, at a pre-charge request input (Fig. 6: 48, 110), and
stores (index stored in Tag is used to generate “pre-charge index” associated with precharge access command. See Fig. 5: 92) a pre-charge signal (Fig. 5: 68. See Fig. 6: 110, precharge access command which is index-based precharge command) for a subsequent cycle while the SRAM access (Fig. 6-Fig. 12) control circuit is accessing stored bits of data in the SRAM memory bank on a current cycle (see “…Pre-charging in the previous clock cycle prior to all memory access…”. See e.g., Fig. 6-Fig. 12 in context of para [0039]-para [0041], para [0044], para [0046]. The pre-charge circuit 66 can enable pre-charging of the SRAM data sub-array 50(0)-50(N) containing the data entry 44 to be accessed prior to access of the data entry 44, if at least a portion of the data entry address 58 in the memory access request 48 sufficient to identify the SRAM data sub-array 50(0)-50(N) to be accessed is available.).
Chai is silent with respect to SRAM access control circuit comprises a pre-charge-reset input to clear the pre-charge on the plurality of bit lines and to clear pre-charge signals stored in the SRAM access control circuit.
ARSOVSKI teaches -
SRAM access control circuit comprises a pre-charge-reset input (combination FB, reset signals input that allows “pre-charge shut-off” and BL discharging from Vtrip to low level shown in Fig. 1 timing diagram. See e.g., Fig. 1: 10 circuitry, para [0020], para [0025]) to clear the pre-charge on the plurality of bit lines (Fig. 1 in context of para [0020], para [0025]-para [0026]).
Mendoza teaches -
access control circuit (“precharge enable register” controlled by “control logic”) comprises a pre-charge-reset input to clear the pre-charge on the plurality of bit lines and to clear pre-charge signals stored in the SRAM access control circuit ("...HSOCHG register bit 30d, when set, enables precharging of node...while the cleared state of HSOCHG register bit 30d disables precharge... the state of HSOCHG register bit 30d is set and cleared by control logic 24...", see e.g. para [0033], para [0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine ARSOVSKI and Mendoza’s circuitry and functions into the apparatus of Chai such that access control circuit with a pre-charge-reset control can be employed in order to reduce RDV-induced timing uncertainty (ARSOVSKI Background) and precisely control precharge operation with reduced power consumption.
Regarding claim 2, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 1. Chai teaches wherein when the SRAM access control circuit is not accessing stored bits of data in the SRAM memory bank on the current cycle, the pre-charge signal causes the plurality of bit lines to pre-charge (See para [0040], see also para [0041]. See Fig. 7 timings: second precharge signal 38 is high after first access wordline signal 22 transitions low and prior to second access wordline signal 22 transitions high).
Regarding claim 3, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 1. Chai teaches wherein when the SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on the current cycle, the pre- charge signal is stored in the SRAM access control circuit to automatically pre-charge the plurality of bit lines when the current memory access is completed (See Fig. 7 timings: second precharge signal 38 is high after first wordline signal 22 transitions low and prior to second wordline signal 22 transitions high. See also Fig. 6 and Fig. 8).
Regarding claim 4, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 1. Chai teaches wherein when the pre-charge signal indicates there is no pre-charge for the subsequent cycle, then the SRAM access control circuit does not pre-charge the bit lines when the current memory access is completed (see e.g., para [0029]: “…pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power…”)
Regarding claim 6, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 1. Chai teaches wherein the pre-charge signal comprises one or more bits (para [0061]: “…generates a pre-charge index…of 3 bits…”)
Regarding claim 7, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 1. Chai teaches wherein the SRAM memory bank comprises a plurality of memory sub-banks (para [0061]: sub-arrays 50_0 to 50_7) and the pre-charge signal comprises a corresponding number of bits to independently (each sub-array is selectable independently at particular cycle via precharge index bits) pre-charge the plurality of memory sub-banks (para [0061]: “…A pre-charge index 68 of 3 bits allows for the pre-charge circuit 66 to identify one of a possible eight (8) SRAM data sub-arrays 50(0)-50(7) for pre-charging…”).
Regarding claim 8, Chai, ARSOVSKI, and Mendoza teaches the SRAM circuit of claim 7. Chai teaches wherein the number of bits is equal to a number of the plurality of memory sub-banks (para [0061]: “…A pre-charge index 68 of 3 bits allows for the pre-charge circuit 66 to identify one of a possible eight (8) SRAM data sub-arrays 50(0)-50(7) for pre-charging…”).
Regarding claim 9, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 7. Chai teaches wherein the SRAM access control circuit comprises a plurality of pre-charge signal inputs equal to a number of the plurality of memory sub-banks (in context of para [0061]: eight combination inputs and eight sub-arrays).
Regarding claim 12, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 11. ARSOVSKI teaches wherein the pre-charge-reset input further clears pre-charge signals stored in the SRAM access control circuit (see Fig. 1: reset and para [0019], para [0016]).
Regarding claim 13, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 12. ARSOVSKI teaches wherein the pre-charge-reset input further turns off (when BL is discharged to low level) one or more head switches (Fig. 1: transistors connected to WL0…WLn) providing power to a plurality of word lines (see Fig. 1 circuitry configuration and supply to access transistors connected to WL0, WLn).
Regarding independent claim 14, Chai, ARSOVSKI, and Mendoza teach a method of, receiving, at a pre-charge request input, and storing, by an SRAM access control circuit, a pre-charge signal at an SRAM memory bank;
storing the pre-charge signal while an SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on a current cycle; and
pre-charging, by the SRAM access control circuit, a plurality of bit lines of the SRAM memory bank based on the pre-charge signal to access stored bits of data of the SRAM memory bank,
wherein the SRAM access control circuit comprises a pre-charge-reset input to clear the pre-charge on the plurality of bit lines and to clear pre-charge signals stored in the SRAM access control circuit. (See claim 1 rejection analysis since the claimed limitations are substantially identical. Method claim limitations are satisfied by apparatus claim limitations])
Regarding claim 15, Chai, ARSOVSKI, and Mendoza teach the method of claim 14, wherein when the SRAM access control circuit is not accessing stored bits of data in the SRAM memory bank on the current cycle, the pre-charge signal causes the plurality of bit lines to pre-charge. (See claim 2 rejection analysis)
Regarding claim 16, Chai, ARSOVSKI, and Mendoza teach the method of claim 14, wherein when the SRAM access control circuit is accessing stored bits of data in the SRAM memory bank on the current cycle, the pre-charge signal is stored in the SRAM access control circuit to automatically pre-charge the plurality of bit lines when the current memory access is completed. (See claim 3 rejection analysis)
Regarding claim 17, Chai, ARSOVSKI, and Mendoza teach the method of claim 14, wherein when the pre-charge signal indicates there is no pre-charge for the subsequent cycle, then the SRAM access control circuit does not pre-charge the bit lines when the current memory access is completed. (See claim 4 rejection analysis)
Regarding claim 18, Chai, ARSOVSKI, and Mendoza teach the method of claim 14, wherein the pre-charge signal comprises one or more bits. (See claim 6 rejection analysis)
Regarding claim 19, Chai, ARSOVSKI, and Mendoza teach the method of claim 14, wherein the SRAM memory bank comprises a plurality of memory sub-banks and the pre-charge signal comprises a corresponding number of bits to independently pre-charge the plurality of memory sub-banks. (See claim 7 rejection analysis)
Regarding claim 20, Ch Chai, ARSOVSKI, and Mendoza ai and ARSOVSKI teach the method of claim 14, wherein the SRAM access control circuit comprises a pre-charge-reset input to clear the plurality of bit lines and clear pre-charge signals stored in the SRAM access control circuit. (See claims 1-10 rejection analysis).
11. Claim 5 is/are rejected under 35 U.S.C. 103 as being obvious over Chai et al. (US 2014/0328113 A1), ARSOVSKI et al. (US 2017/0352407 A1), and Mendoza et al. (US 2004/0204162 A1), in view of Saleh (US 2006/0164904 A1).
Regarding claim 5, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 4, wherein when the pre-charge signal indicates there is no pre-charge for the subsequent cycle, then the SRAM access control circuit further turns off one or more head switches providing power to a plurality of word lines when the current memory access is completed (See Chai para [0062]: de-assertion of word lines is performed using data array circuitry or by clocking scheme when no pre-charge for the subsequent cycle is indicated).
Chai, ARSOVSKI, and Mendoza are silent with respect to turning off one or more head switches providing power to a plurality of wordlines.
Saleh teaches when the pre-charge signal indicates there is no pre-charge for the subsequent cycle (Fig. 2 and Fig. 3: B and C signal status during sleep mode), then the SRAM access control circuit further turns off one or more head switches (Fig. 2: 218 pull up switch is turned off) providing power to a plurality of word lines when the current memory access is completed (see para [0043] and Fig. 3: signal A status during 354).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Saleh’s power supply circuitry and method into the apparatus of Chai, ARSOVSKI, and Mendoza such that word line power can be controlled in order to improve leakage performance and reduce power (Saleh para [0005]).
12. Claim 10 is/are rejected under 35 U.S.C. 103 as being obvious over Chai et al. (US 2014/0328113 A1), ARSOVSKI et al. (US 2017/0352407 A1), and Mendoza et al. (US 2004/0204162 A1), in view of Kim (US 2008/0123452 A1).
Regarding claim 10, Chai, ARSOVSKI, and Mendoza teach the SRAM circuit of claim 9. Chai teaches clocked input of latches for holding the precharge index. Chai, ARSOVSKI, and Mendoza are silent with respect to remaining provisions of this claim.
Kim teaches wherein the SRAM access control circuit comprises a plurality of flip flops for storing the plurality of pre-charge signal inputs equal to the number of the plurality of memory sub-banks (Kim teaches memory in which the number of precharge bit corresponds to the number of banks. Said bits are stored in a latch. Se Fig. 11, para [0021]-para [0023]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Kim’s circuitry and method into the apparatus of Chai, ARSOVSKI, and Mendoza such that SRAM access control circuit with plurality of flip flops for storing the plurality of pre-charge signal inputs can be employed to facilitate operation “…write recovery time may help to ensure proper operation of a synchronous semiconductor memory device…”.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 14 have been considered but are partly moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed have been fully considered but they are not persuasive because applicant has provided sufficient reasons and applicant has not considered prior arts in their entirety. See new formulated rejection.
Prior art ARSOVSKI clearly teaches precharge reset of the bit lines. ARSOVSKI Fig. 1 teaches precharge reset. See addition of Mendoza reference. Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety.
Applicant has not argued substantively against dependent claim specific limitations and previous rejections are being relied upon.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: KURODA (US 2013/0044551 A1): Fig. 1A-Fig. 11 applicable for all claims. Previously cited US10217494 A: teaches precharge and operation reset signal; and US 2015/0109865 A1: Fig. 1A-Fig. 3 applicable for all claims. It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825