DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-7 in the reply filed on 8/14/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US pat 8962393) in combination with KR 100890073.
With respect to claim 1, Pagaila et al. teach a semiconductor package structure, comprising (see figs. 1-19, particularly fig. 4 and associated text):
a first base plate 202 provided with a first surface (upper);
a first chip stack body 406 located on the first base plate, and the first chip stack body is electrically connected to the first surface of the first base plate;
an interposer layer 204 located on the first chip stack body, wherein the interposer layer is provided with a first interconnection surface (upper), the first interconnection surface is provided with a first interconnection region (area in middle of 204) and a second interconnection region (right edge of 204), and the first interconnection region is electrically connected to the first base plate; and
a molding layer 418 configured to seal the first chip stack body, the interposer layer and the first surface of the first base plate, wherein the first interconnection region is unsealed by the molding layer, the second interconnection region is sealed by the molding layer, and a first material layer 304 is formed on a sidewall between the first interconnection region and a top surface of the molding layer on the second interconnection region.
Pagaila et al. fail to teach the first chip stack body includes vertically stacked chips.
KR ‘073 teaches using vertically stacked chips. See the text of Disclosure of paper.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of KR ‘073 into the device of Pagaila et al. to achieve device density and operating speed. See the text of Disclosure of paper.
With respect to claim 2, Pagaila et al. teach a material of the first material layer comprises a conductive material or an insulation material. See fig. 4 and associated text.
With respect to claim 3, Pagaila et al. teach a second material layer 306 located on the top surface of the molding layer, wherein a material of the second material layer is the same as a material of the first material layer. See fig. 4 and associated text.
With respect to claim 5, Pagaila et al. in combination with KR ‘073 teach a plurality of first conductive wires 420 , wherein each of the plurality of first semiconductor chips is electrically connected to the first base plate by means of a respective one of the plurality of first conductive wires; and a plurality of second conductive wires 408, wherein the second interconnection region is electrically connected to the first base plate by means of the plurality of second conductive wires. See fig. 4 and associated text.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila et al. (US pat 8962393) and KR 100890073 as applied to claims 1, 2, 3, and 4 above, and further in view of Shim et al. (US pat 8309397).
With respect to claim 6, Pagaila et al. fail to the edge of the molding layer facing the first connection region is sloped.
Shim et al. teach a similar device in which a mold layer 124 having a recess having a sloped opening to cover an interposer 108. See fig. 1 and associated text.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Shim et al. into the device of Pagaila et al. to allow the placement of additional IC on the disposer. See fig. 1 and associated text.
Allowable Subject Matter
Claims 5 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Cited References
The cited references generally show the similar or related structure having an interposer or chip having encapsulated part for connections and non-encapsulated part without connections claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897