Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 7 is objected to because of the following informalities: “a substrate” in line 2. For the sake of compact prosecution, claim 7 is interpreted in the instant Office action as follows: “a substrate” is found to be a grammatical error and is found to correspond to the same substrate now existing in claim 1, line 3 as a result of the instant amendments to claim 1. No actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Osanai (US 20050037559 A1) in view of Lai (US 20230328970 A1).
Regarding claim 1, Osanai discloses a method for manufacturing a semiconductor structure (Fig. 4), comprising: providing a structure to be etched (102 with 101), wherein the structure comprises a substrate ([0018]: “substrate”); forming an etched hole (103) in the structure to be etched ([0018]: “a trench 103 is selectively formed within the low impurity concentrated N-type drift layer 102”) […]; performing multiple conducting material layer deposition processes (layers 105, 106, 107) until the conducting material layer fills up the etched hole without a void ([0023]: “perfectly fill”; voids are absent from the illustration) […], wherein the method further comprises: annealing the conducting material layer deposited (annealing after deposition of each of layers 105, 106, and 107, with each successive anneal being performed on the corresponding layer as well as all prior-formed layers existing therewith; [0019] “heat treatment” with respect to 105; [0022] “heat treatment” with respect to 106; [0023] “repeatedly carried out” with respect to 107) after an odd-numbered conducting material layer deposition process (selecting the odd-numbered embodiment which is three processes, an odd number), or annealing the conducting material layer deposited after an even-numbered conducting material layer deposition process (two processes are inclusive within the selected three-process embodiment) […].
Osanai teaches the structure to be etched, however, fails to teach the specific claimed intended used and configuration thereof “wherein the etched hole comprises a bit line contact hole […] to form a bit line contact structure […] planarizing the structure to be etched in order to remove the conducting material layer situated on a top surface of the substrate”.
Lai discloses a method in the same field of endeavor with a substrate (Fig. 17; the substrate being the collection of 309 with 101; “substrate” being interpreted as a preexisting base substance worked or acted upon, consistent with the plain and ordinary meaning), wherein the etched hole (909) comprises a bit line contact hole ([0094]: “bit line contact opening 909”) to form a bit line contact structure (Fig. 19: 401; [0096]: “bit line contact 401”; subsequent manufacturing steps arrive at the resultant bit line contact structure); planarizing the structure to be etched ([0096]: “a planarization process”) in order to remove the conducting material layer (Fig. 18: 617; [0095]: “conductive material 617”) situated on a top surface of the substrate ([0095]: “completely fill the bit line contact opening 909 and cover the fourth hard mask layer 707”).
Using the method of Osanai when performing the alternative scenario (of Lai) of forming the bit line contact structure would arrive at the claimed method and intended use thereof. One would have been motivated to do so because Osanai teaches the method is useful for forming a conducting material layer without the inclusion of voids (Osanai: [0023]: “perfectly fill”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method configuration because it would enable producing a structure of alternative intended use without the inclusion of voids. MPEP 2143 (I)(C).
Illustrated below is a marked and annotated figure of Lai.
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Regarding claim 2, Osanai in view of Lai discloses the method according to claim 1 (Osanai: Fig. 4), further comprising: after each of the conducting material layer deposition processes, annealing the conducting material layer deposited (annealing after deposition of each of layers 105, 106, and 107; [0019]: “heat treatment” with respect to 105; [0022]: “heat treatment” with respect to 106; and [0023]: “repeatedly carried out” with respect to 107).
Regarding claim 6, Osanai in view of Lai discloses the method according to claim 1 (Fig. 4), wherein during performing the multiple conducting material layer deposition processes, a number of times of annealing the conducting material layer deposited is more than or equal to half of a number of times of depositing the conducting material layer (selecting “more than..half”; Osanai teaches annealing after deposition of each of layers 105, 106, and 107 as cited in the claim 1 rejection, which is more than half of the three cited layers).
Regarding claim 7, Osanai in view of Lai discloses the method according to claim 1, wherein the structure to be etched comprises a substrate (as cited in the claim 1 rejection, repeated here; Fig. 17; the substrate being the collection of 309 with 101; “substrate” being interpreted as a preexisting base substance worked or acted upon, consistent with the plain and ordinary meaning) and a dielectric layer located on the substrate (307; [0081]: “”silicon oxide”), the etched hole penetrates through the dielectric layer in a thickness direction (Z direction), and a capacitor storage node contact structure ([0100]: capacitor contacts) is formed after the conducting material layer fills up the etched hole without a void ([0100]: “capacitor contacts, and capacitors (Not shown) may be formed over the intermediate semiconductor device illustrated in FIG. 22” describing a method step performed subsequent to Figs. 17-19).
Regarding claim 8, Osanai in view of Lai discloses the method according to claim 1 (Osanai: Fig. 4), wherein the conducting material layer comprises a doped polycrystalline silicon layer ([0019]: “polycrystalline silicon film…implanted”).
Regarding claim 9, Osanai in view of Lai discloses the method according to claim 1, wherein a depth-to-width ratio of the etched hole (Lai: Fig. 18: see dashed reference lines for Depth and Width) […].
Osanai in view of Lai fails to teach a specific range for the depth-to-width ratio (i.e., a size/proportion), and therefore fails to teach “wherein a depth-to- width ratio of the etched hole is greater than or equal to 4:1”. However, the greatly exaggerated sizes/proportions of the figure (Lai, Fig. 18) suggest a ratio having a similar orientation as the ratio claimed (i.e., a very large depth relative to a very narrow width). Nevertheless and ignoring the sizes/proportions of the figure (as per MPEP 2125 (II)), the only difference between the prior art and the claims is a recitation of relative dimensions, and the claimed ratio would not perform differently than the prior art because Lai teaches the etched hole performing the same function as the claim (i.e., “a bit line contact hole”). Therefore, the claimed ratio would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because it is not patentably distinct from the prior art. MPEP 2144.04 (IV)(A) Gardner
Claims 3 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Osanai and Lai as applied to claim 1 above, and further in view of Chung (US 20120315752 A1).
Regarding claim 3, Osanai in view of Lai discloses the method according to claim 1 (Osanai: Fig. 4), however fails to teach “wherein after annealing the conducting material layer, part of the conducting material layer located at a top corner of a sidewall of the etched hole presents a rounded corner shape”.
Chung discloses a method with a conducting material layer (151; [0058]: “conductive film 151”), annealing the conducting material (method step of Fig. 12; [0058]: “annealed”), wherein after annealing the conducting material layer, part of the conducting material layer located at a top corner of a sidewall of the etched hole (the resultant shape of 151 relative to dashed reference line of initial 151) presents a rounded corner shape (both the initial and resultant shapes of 151 include rounded corner shapes). Modifying the annealing method step of Osanai in view of Lai to include the annealing method step of Chung would arrive at the claimed resultant shape. Chung provides a teaching to motivate one to include the annealing method step with the annealing method step of Osanai in view of Lai in that it would enhance the prevention of voids, thereby enabling enhanced device reliability ([0059]: “prevent voids from being formed”; [0049]: “if left untreated, would lower the reliability”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed annealing method step configuration because it would enhance device reliability. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 12 of Chung.
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Regarding claim 10, Osanai in view of Lai discloses the method according to claim 1 (Osanai: Fig. 4), wherein the conducting material layer is annealed (as cited in the claim 1 rejection), however, fails to teach “the conducting material layer is annealed under an atmosphere comprising hydrogen”.
Chung discloses a method with a conducting material layer (151; [0058]: “conductive film 151”), annealing the conducting material (method step of Fig. 12; [0058]: “annealed”), wherein the conducting material layer is annealed under an atmosphere comprising hydrogen ([0058]: “H2”). Modifying the annealing method step of Osanai in view of Lai to include the annealing method step of Chung would arrive at the claimed annealing method step. Chung provides a teaching to motivate one to include the annealing method step with the annealing method step of Osanai in view of Lai in that it would enhance the prevention of voids, thereby enabling enhanced device reliability ([0059]: “prevent voids from being formed”; [0049]: “if left untreated, would lower the reliability”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed annealing method step configuration because it would enhance device reliability. MPEP 2143 (I)(G).
Regarding claim 11, Osanai in view of Lai and Chung discloses the method according to claim 10 (Chung: Fig. 12), wherein the conducting material layer is annealed under an atmosphere of pure hydrogen (as cited in the claim 10 rejection and repeated here, [0058]: “H2”).
Regarding claim 12, Osanai in view of Lai and Chung discloses the method according to claim 10 (Chung: Fig. 13), wherein the conducting material layer is annealed under an atmosphere of mixed hydrogen and nitrogen (the mixture formed by the hydrogen that is removed while within the N2 atmosphere; [0060] “at least some of the hydrogen ions injected into the semiconductor substrate 100 are removed” being the hydrogen component; [0060] “annealed in an inert gas (for example, N2, He, or Ar) atmosphere” being the nitrogen component).
Regarding claim 13, Osanai in view of Lai and Chung discloses the method according to claim 10 (Osanai: Fig. 24), wherein an annealing temperature comprises 700 °C to 1200 °C ([0019]: “800 to 900 C”, being squarely within the claimed range).
Regarding claim 14, Osanai in view of Lai and Chung discloses the method according to claim 10 (Osanai: Fig. 2), wherein an annealing time comprises 30 s to 2 h ([0019]: “about 30 minutes”, being squarely within the claimed range).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Osanai in view of Lai and Chung as applied to claims 10 and 1 above, and further in view of Haupt.
Regarding claim 15, Osanai in view of Lai and Chung discloses the method according to claim 10 (Chung: Fig. 12), however fails to provide extensive details regarding recipe settings for the annealing process, and therefore fails to teach “wherein an annealing pressure during the annealing comprises 10 Torr to 760 Torr”.
Haupt discloses a method in the same field of endeavor, wherein an annealing method step is performed (“annealing” [0038]) as well as details regarding recipe settings for the annealing process, wherein an annealing pressure during the annealing comprises 10 Torr to 760 Torr ([0038]: “between about 10 Torr and 100 Torr”, substantially overlapping the claimed range). Modifying the recipe settings of the annealing method step of Osanai in view of Lai and Chung to include the annealing pressure of Haupt would arrive at the claimed pressure range. Haupt provides a teaching to motivate one to include the annealing pressure in that it would reduce the formation of voids within the conducting material layer ([0039]: “void has been eliminated or minimized”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed annealing pressure because it would reduce the formation of voids within the conducting material layer. MPEP 2143 (I)(G).
Regarding claim 16, Osanai in view of Chung discloses the method according to claim 10 (Chung, Fig. 12), wherein during annealing the conducting material layer under the atmosphere comprising hydrogen, a gas flow rate of hydrogen ([0058]: “H2” necessarily having at least some flow rate) […]. However, fails to provide extensive details regarding recipe settings for the annealing process, and therefore fails to teach “wherein during annealing the conducting material layer under the atmosphere comprising hydrogen, a gas flow rate of hydrogen is 1 slm to 100 slm”.
Haupt discloses a method in the same field of endeavor, wherein an annealing method step is performed (“annealing” [0038]) as well as details regarding recipe settings for the annealing process, wherein a gas flow rate of hydrogen is 1 slm to 100 slm ([0038]: “between about 2 SLPM and 25 SLPM”, substantially overlapping the claimed range). Modifying the recipe settings of the annealing method step of Osanai in view of Lai and Chung to include the hydrogen gas flow rate of Haupt would arrive at the claimed flow rate range. Haupt provides a teaching to motivate one to include the hydrogen gas flow rate in that it would reduce the formation of voids within the conducting material layer (“void has been eliminated or minimized” [0039]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed hydrogen gas flow rate because it would reduce the formation of voids within the conducting material layer. MPEP 2143 (I)(G).
Response to Arguments
Applicant's arguments filed 9/29/2025 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Osanai has revealed that annealing treatment is conducted subsequent to each deposition of the conductive material layer…The present application does not encounter the aforementioned technical issues. Thus, it can be deduced that Osanai has not disclosed the above features […] “annealing the conducting material layer deposited after an odd-numbered conducting material layer deposition process, or annealing the conducting material layer deposited after an even-numbered conducting material layer deposition process.””. Remarks at pg. 6.
Examiner’s reply:
The examiner disagrees and finds the “annealing” configuration of Osanai encompassed within the breadth of “annealing” as claimed. For example, the third annealing step of Osanai is performed not on the third layer in isolation but rather the collection of first/second/third layers regardless of whether any intermediate annealing steps have been performed. Furthermore, the claim as written reasonably encompasses annealing configurations beyond that which is claimed because it does not preclude intermediate annealing steps. The reference is being relied upon in the same way as before, though additional references are combined therewith as necessitated by other additional limitations in the claim such as “planarizing”. MPEP 2111.
Furthermore, the mapping of the reference is consistent with the guidance of Applicant’s disclosure. For example, Claim 2 as originally filed requires “The method according to claim 1, further comprising: after each of the conducting material layer deposition processes, annealing the conducting material layer deposited.” Thus, the examiner does not find any discrepancy between the mapping of the reference to the “annealing” claim terms whether in claim 1 along or when combined with claim 2.
Nonetheless, the newly added “planarizing” limitation overcomes the outstanding rejection because Kim fails to teach this method step and does not teach a method that would be modified in an obvious way to include this method step. Lai is relied upon herein to overcome this deficiency of Osanai and Kim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
/ANTONIO B CRITE/ Primary Examiner, Art Unit 2817
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