DETAILED ACTION
This office action is in response to amendment filed 12/26/2025.
Claims 1-20 are pending. Claims 11-20 have been withdrawn. Claims 1, 5-8, 10-16, 18 and 20 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “the signal lines comprises the first signal line plugs … and second signal line plugs” renders the claim indefinite. It is unclear how do the “signal lines” comprises the “signal line plugs”. The “signal lines” recited to comprise “first signal lines and second signal lines” previously in the claims.
Claim 2 reciting “the first direction” renders the claim indefinite for lacking antecedent basis. No “first direction” has been claimed previously in claim 1. It is unclear what is the referred to by “the first direction”.
Claim 5 reciting “a first direction” renders the claim indefinite. It is unclear if “a first direction” recited in claim 5 is the same as “the first direction” recited in claim 2.
Claim 10 reciting “a plurality of memory regions” renders the claim indefinite. Claim 1 previously recite details of “a memory region”. It is unclear if the “plurality of memory regions” recited in claim 10 each requires the same structure as the “memory region” as recited in claim 1.
Claim 10 reciting “one memory structure is located above each of the memory regions” renders the claim indefinite. Claim 1 previously recite details of “a memory structure above the memory region”. It is unclear if each of “memory structure … above each of the plurality of memory regions” recited in claim 10 requires the same structure as the “memory structure” as recited in claim 1.
Claim 10 reciting “a plurality of peripheral structures” renders the claim indefinite. Claim 1 previously recite details of “a peripheral structure”. It is unclear if the “plurality of peripheral structures” recited in claim 10 each requires the same structure as the “peripheral structure” as recited in claim 1.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. US 2021/0057419 A1 (Shin).
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In re claim 1, as best understood, Shin discloses (e.g. FIGs. 2-4 & 10-13 & 16-17) a semiconductor device, comprising:
a substrate SUB comprising a memory region CAR and a peripheral region PER1,PER2 located at an outer side of the memory region CAR;
a memory structure SS1,SS2,SS3,SS4 located above the memory region CAR and comprising a memory array R1,R2,R3,R4 and a plurality of signal lines CL1,CL2, the memory array R1-R4 comprising memory cells SP spaced apart from each other, and the signal lines CL1,CL2 being electrically connected with the memory cells SP, wherein the signal lines comprise a first signal lines CL1 and second signal lines CL2, the first signal lines CL1 and the second signal lines CL2 extend along different directions (e.g. CL1 elongated in D1 direction, CL2 elongated in D3 direction), the memory structure further comprises signal line plugs VI, “the signal lines” (as best understood, plugs VI) comprises the first signal line plugs VI (above CL1, e.g. see FIG. 4B) electrically connected to the first signal lines CL1 and second signal line plugs VI (above CL2, e.g. see FIGs. 4C & 17A) electrically connected to the second signal lines CL2; and
a peripheral structure located above the peripheral region PER1,PER2 and comprising peripheral stacked layers SLS,PTR, peripheral circuits (PTR, e.g. PG,SDC) located above the peripheral stacked layers SLS,PTR, and a plurality of peripheral leads VI located above the peripheral circuits PG,SDC, one end (bottom) of each of the peripheral leads VI being electrically connected with at least one of the peripheral circuits, and the other end (top) being electrically connected with at least one of the signal lines CL1,CL2 (through ML, ¶ 69,77,80), wherein the peripheral circuits PTR comprise first peripheral circuits (those connected to CL1, ¶ 69) and second peripheral circuits (those connected to CL2, ¶ 77), the peripheral leads (VI in PER1,PER2) comprises first peripheral leads (VI connected to CL1) and second peripheral leads (VI connected to CL2), the first peripheral leads VI are electrically connected to the first peripheral circuits (connecting PTR to CL1), the second peripheral leads VI are electrically connected to the second peripheral circuits (connecting PTR to CL2);
first connecting bridges ML electrically connecting the first signal line plugs (VI above CL1) and the first peripheral leads (VI above PTR connected to CL1), and second connecting bridges ML electrically connecting the second signal line plugs (VI above CL2) and the second peripheral leads (VI above PTR connected to CL2), wherein the second connecting bridges are parallel to the first connecting bridges (interconnection lines ML are formed on the same level and have one side that is parallel to each other in plan view).
More specifically, first connecting bridges connecting CL1 and PTR includes ML elongated in the D2 direction, second connecting bridges connecting CL2 and PTR includes ML elongated in the D1 direction. An example of first connecting bridge is represented by ML1 in the annotated drawing below. An example of second connecting bridge is represented by ML2 in the annotated drawing below. The right side of the first connecting bridge ML1 faces the left side of the second connecting bridge ML2, and these facing sides are parallel to each other. Therefore, the connecting bridges are considered parallel. Furthermore, top surfaces of ML1 and ML2 are also parallel, bottom surfaces of ML1 and ML2 are also parallel, etc. Alternatively, CL1 may be the second signal lines and CL2 may be the first signal lines.
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In a second interpretation, first signal lines and second signal lines correspond to different ones of CL1 or CL2. For examples, first signal lines correspond to some of CL1 and second signal lines correspond to other ones of CL1. As such, the connecting bridges ML connecting different ones of CL1 to a corresponding peripheral circuits PTR are elongated in the same D2 direction and are thus “parallel”.
In a third interpretation, in the embodiments shown FIGs. 19-20, the peripheral circuits PTR are arranged above the signal lines CL1,CL2 in the D3 direction. Connecting bridges THV connecting peripheral circuits PTR and first signal lines CL1 and connecting bridges THV connecting peripheral circuits PTR and second signal lines CL2 are both extending in the D3 direction. Thus, the connecting bridges THV are parallel to each other.
In re claim 2, as best understood, Shin discloses (e.g. FIGs. 17A-17B) wherein the peripheral stacked layers SLS comprise first semiconductor layers SL1 and second semiconductor layers SL2 alternately stacked along “the first direction” D3; and the peripheral structure further comprises:
a first isolation layer PGI,ST located between the peripheral stacked layers SLS and the peripheral circuits PG,SDC (alternatively, topmost SL2 can be the “first isolation layer” as it physically isolate SEL from underlying structure).
In an alternative interpretation, as shown in FIGs. 4C-4D (see annotated below), peripheral stacked layers correspond to lower layers of PCH alternating with other PCH layers in the peripheral region PER1,PER2. Peripheral circuit includes a topmost PCH layers above the lower stacked layers of PCH, and peripheral leads correspond to V1 electrically connected with topmost PCH (through PG or SDC). As such, the peripheral stacked layers underlying the topmost PCH are separated from the peripheral circuits (including topmost PCH) by the first isolation layer IL between topmost PCH and underlying PCH.
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In re claim 3, Shin discloses (e.g. FIGs. 17A-17B) wherein each of the peripheral circuits PTR comprises:
a peripheral substrate SEL comprising a peripheral active area PCH, a top surface of the peripheral substrate SEL being flush with or higher than a top surface of the memory array SS1-SS4; and
a peripheral electrode PG,SDC located on the peripheral active area PCH, one end (bottom) of the peripheral lead V1 being electrically connected with the peripheral electrode PG,SDC, and the other end (top) being electrically connected with the signal line CL1,CL2 (through ML, ¶ 69,77,80).
In the alternative interpretation, as shown in FIGs. 4C-4D (see annotated above), Shin teaches wherein each of the peripheral circuits comprises:
a peripheral substrate (structure above the second IL layer, see annotated in figure above) comprising a peripheral active area (topmost PCH), a top surface of the peripheral substrate being flush with or higher than a top surface of the memory array (corresponding to the array of cells SP layers below the level of topmost PCH); and
a peripheral electrode PG,SDC located on the peripheral active area, one end (bottom) of the peripheral lead V1 being electrically connected with the peripheral electrode PG,SDC, and the other end (top) being electrically connected with the signal line CL1,CL2 (through ML, ¶ 69,77,80).
In re claim 4, Shin discloses (FIGs. 4C-4D, see annotated figure above) wherein the peripheral substrate (including topmost PCH) is a fully depleted silicon-on-insulator substrate, a partly depleted silicon-on-insulator substrate, or a metal oxide semiconductor substrate. PCH being formed from SL1 is a silicon layer (¶ 90,93) which is on insulator IL. During the operation of the transistor formed by the topmost PCH, the channel is depleted.
In re claim 5, as best understood, Shin discloses (e.g. FIGs. 4A-4D) wherein the first signal lines CL2 extend along “a first direction” D3, each of the first signal lines CL2 is electrically connected to a plurality of the memory cells SP spaced apart from each other along the first direction D3, the first direction D3 is perpendicular to a top surface of the substrate SUB; and
the top surface of the peripheral substrate (as defined by top of ILD2) is flush with top surfaces of the first signal lines CL2.
In re claim 6, Shin disclose (e.g. FIGs. 2-4 & 16-17) the signal line plugs (VI above CL1,CL2) extend along a first direction D3, the peripheral leads (VI in PER1,PER2) extend along the first direction D3, and a length of the peripheral leads VI in the first direction D3 is less than or equal to a length of the signal line plugs VI in the first direction D3;
the peripheral region PER1,PER2 is arranged at the outer side of the memory region CAR along a second direction D1, wherein the first direction D3 is perpendicular to a top surface of the substrate SUB, and the second direction D1 is parallel to the top surface of the substrate SUB.
In re claim 7, Shin discloses (e.g. FIGs. 2-4 & 16-17) wherein the first signal lines CL1 are spaced apart from each other along a first direction D3, the peripheral region PER1,PER2 is arranged at the outer side of the memory region CAR along a second direction D2 (see FIGs. 3 & 16, a portion of the memory region including CL1 is spaced apart from PER1,PER2 along D2 direction), the first direction D3 is perpendicular to a top surface of the substrate SUB, and the second direction D2 is parallel to the top surface of the substrate SUB, wherein in two adjacent ones of the first signal lines CL1 along the first direction D3, one of the two first signal lines (lower CL1) closer to the substrate SUB has a length along a third direction D1 larger than a length of the other of the two first signal lines (upper CL1) along the third direction D1 (see FIG. 4B), and the third direction D1 is parallel to the top surface of the substrate SUB and intersects with the second direction D2; and
wherein the first peripheral circuits are spaced apart from each other along the third direction D1 (see FIG. 2-3 & 16, two PTR adjacent in D1 direction), and the first peripheral leads VI (of adjacent PTR, e.g. see FIG. 4C & 17A) are spaced apart from each other along the third direction D1; one ends (bottom) of the first peripheral leads VI are electrically connected to the first peripheral circuits PTR in one-to-one correspondence, and the other ends (top) are electrically connected to the first signal lines CL1 in one-to-one correspondence (¶ 69,80, each one of VI that connects to CL1 is in one-to-one correspondence).
In re claim 8, Shin discloses(e.g. FIGs. 2-4 & 16-17) wherein the second signal lines CL2 are spaced apart from each other along the third direction D1, and top surfaces of the plurality of second signal lines CL2 are flush (see FIG. 4C & 17A); and
wherein the second peripheral circuits are spaced apart from each other along the third direction D1 (see FIG. 2-3 & 16, two other PTR adjacent in D1 direction), and the second peripheral leads VI (of adjacent PTR) are spaced apart from each other along the third direction D1; one ends (bottom) of the second peripheral leads VI are electrically connected to the second peripheral circuits PTR in one-to-one correspondence, and the other ends (top) are electrically connected to the second signal lines CL2 in one-to-one correspondence (¶ 77, third peripheral circuit region, not shown, connected to CL2; as such, each one of VI that connects to CL2 is in one-to-one correspondence).
In re claim 9, Shin discloses (e.g. FIGs. 2-4 & 16-17) the first signal lines CL1 are bit lines BL (¶ 52) and the second signal lines CL2 are word lines WL (¶ 62).
In re claim 10, as best understood, Shin disclose (e.g. FIGs. 2-3 & 16) wherein the substrate SUB comprises “a plurality of the memory regions” (regions of SS1-SS4) at outer sides of the peripheral region PER1,PER2, and “one memory structure” SS1-SS4 is located above each of the memory regions;
the peripheral region PER1,PER2 comprises “a plurality of peripheral structures” PER1,PER2 and an isolation layer (ILD2 between PER1 and PER2) located between two adjacent ones of the peripheral structures PER1,PER2, the plurality of peripheral structures PER1,PER2 and “the plurality of memory structures” SS1-SS4 being electrically connected in one-to-one correspondence (e.g. memory structure SS1 and SS2 is connected to PER1, while memory structure SS3,SS4 is connected to PER2).
Response to Arguments
Applicant's arguments filed 12/26/2025 have been fully considered but they are not persuasive.
Regarding claims rejected over Shin, Applicant argues since PTRs are located at a side of CL1 along the second direction D2 and are located at a side of the CL2 along the first direction D1, the extension directions of interconnection lines ML connecting them must be different (Remark, pages 11-12).
This is not persuasive. Claim does not specify what aspect of the connecting bridges need to be parallel.
First connecting bridges connecting CL1 and PTR includes ML elongated in the D2 direction, while second connecting bridges connecting CL2 and PTR includes ML elongated in the D1 direction. The annotated drawing below shows an example of a first connecting bridge ML1 and a second connecting bridge ML2.
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The right side of the first connecting bridge ML1 faces the left side of the second connecting bridge ML2, and these facing sides are parallel to each other. Therefore, the connecting bridges are considered parallel. Furthermore, top surfaces of ML1 and ML2 are also parallel, bottom surfaces of ML1 and ML2 are also parallel, etc.
Furthermore, in a second interpretation, first signal lines and second signal lines correspond to different ones of CL1 or CL2. For examples, first signal lines correspond to some of CL1 and second signal lines correspond to other ones of CL1. As such, the connecting bridges ML connecting different ones of CL1 to a corresponding peripheral circuits PTR are elongated in the same D2 direction and are thus “parallel”.
In a third interpretation, in the embodiments shown FIGs. 19-20, the peripheral circuits PTR are arranged above the signal lines CL1,CL2 in the D3 direction. Connecting bridges THV connecting peripheral circuits PTR and first signal lines CL1 and connecting bridges THV connecting peripheral circuits PTR and second signal lines CL2 are both extending in the D3 direction. Thus, the connecting bridges THV are parallel to each other.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896