DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11, 15 and 16 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ahn et al. (2021/0391259).
As for claim 11, Ahn et al. show in Figs. 1, 2A (except AX region), 5 and related text a semiconductor structure 300, comprising:
a substrate 110, a bit line contact hole DCH being provided in the substrate;
a bit line contact structure (lower portion of) DC/142/143/144 comprising a bit line contact isolation layer 142/143/144 and a bit line contact layer (lower portion of) DC, wherein the bit line contact isolation layer at least covers a side wall of the bit line contact hole, and a remaining space of the bit line contact hole is full of the bit line contact layer; and
a bit line stack layer 330 (upper portion of DC)/332/334/336 positioned on a top surface of the bit line contact structure, wherein the bit line stack layer comprises a first conductive layer 330 (upper portion of DC)/332, a second conductive layer 334 and a dielectric layer 336 stacked in sequence from bottom to top, and a width of a top surface of the first conductive layer is smaller than a width of a bottom surface of the first conductive layer (Fig. 5; [0069]).
As for claim 15, Ahn et al. show the bit line contact isolation layer comprises:
a first isolation layer 142 at least covering the side wall of the bit line contact hole;
a second isolation layer 143 covering an exposed side surface of the first isolation layer; and
a third isolation layer 144 covering an exposed side surface of the second isolation layer (Fig. 2A).
As for claim 16, Ahn et al. show both the first isolation layer and the third isolation layer comprise a silicon nitride layer ([0040], [0049], [0050], [0102]);
the second isolation layer comprises a silicon oxide layer ([0050],[0102]); and
the bit line contact layer comprises a polysilicon layer ([0033]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 11, 15 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MEIYA LI/Primary Examiner, Art Unit 2811