DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 objected to under 37 CFR 1.75 as being a substantial duplicate of claim 1. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 10-18, 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1. Claim 1 recites the limitation "the horizontal signal lines" in the last line the claim language. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-8, 10-18 are rejected for dependence upon a 112(b) rejected claims.
Regarding claim 20. Claim 20 is rejected for the same analogous reasons as claim 1 above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5, 20 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et al (U.S. 2020/0279601).
Regarding claim 1. Kim et al discloses a semiconductor structure (FIG. 2, item 100A), comprising:
a substrate (FIG. 2, item 110) comprising:
a memory cell area (FIG. 2, item CP);
at least one stacked structure (FIG. 2, item MCA) disposed on the memory cell area (FIG. 2, item CP) of the substrate (FIG. 2, item 110),
the at least one stacked structure (FIG. 2, item MCA) comprising
a plurality of memory cell groups (FIG. 2, item MCA1 and MCA2) arranged in a first direction (FIG. 2, item D3), each of the memory cell groups (FIG. 2, item MCA1 and MCA2) comprising multiple a plurality of layers (FIG. 2, item MCAU and MCAL) of memory cells (FIG. 2, item MCAU1/2 and MCAL1/2) arranged in a second direction (FIG. 2, item D1),
wherein the first direction (FIG. 2, item D3) is parallel to a surface of the substrate (FIG. 2, item 110), and the second direction (FIG. 2, item D1) is perpendicular ([0008]) to the surface of the substrate (FIG. 2, item 110);
a plurality of horizontal signal lines (FIG. 2, item WLL2, WLU2) arranged in the second direction (FIG. 2, item D1), and each of the horizontal signal lines (FIG. 2, item WLL2, WLU2) extending along the first direction (FIG. 2, item D3) and being connected to the memory cells (FIG. 2, item MCAU1/2 and MCAL1/2) of the plurality of memory cell groups (FIG. 2, item MCA1 and MCA2); and
a plurality of leading wire posts (FIG. 2, item BL1-4) disposed on the memory cell area (FIG. 2, item CP) of the substrate (FIG. 2, item 110), wherein at least two leading wire posts (FIG. 2, items BL2,4) of the plurality of leading wire posts (FIG. 2, item BL1-4) are individually provided to penetrate (FIG. 2, items BL2,4) different memory cell groups (FIG. 2, item MCA1 and MCA2) from the second direction (FIG. 2, item D3) and are disposed on different memory cells (FIG. 2, item MCAU1/2 and MCAL1/2) to electrically connect ([0042]) to at least two (FIG. 2, item WLL2, WLU2) the horizontal signal lines (FIG. 2, item WLL2, WLU2).
Regarding claim 3. Kim et al discloses the semiconductor structure (FIG. 2) according to claim 1 above.
Kim et al further discloses each of the plurality of memory cell groups (FIG. 2, item MCA1 and MCA2) is in contact with at most one (FIG. 2, items BL2,4) of the plurality of leading wire posts (FIG. 2, items BL2,4), and bottom surfaces (FIG. 2, items BL2,4 of FIG. 2, item MCAL1/2)) the plurality of leading wire posts (FIG. 2, items BL2,4) individually disposed on one (FIG. 2, item MCAL1/2) of the memory cells (FIG. 2, item MCAU1/2 and MCAL1/2) of different ones (FIG. 2, item MCA1 and MCA2) of the plurality of memory cell groups (FIG. 2, item MCAU1/2 and MCAL1/2)
Regarding claim 5. Kim et al discloses the semiconductor structure (FIG. 2) according to claim 1 above.
Kim et al further discloses wherein a number (FIG. 2, item BL2) of the plurality of leading wire posts (FIG. 2, item BL1-4) in contact with one (FIG. 2, item MCA2) of the plurality of memory cell groups (FIG. 2, item MCA1 and MCA2) is less (FIG. 2 shows item BL1 is less than items MCAU2 and MCAL2) than a number (FIG. 2 shows item BL1 is less than items MCAU2 and MCAL2) of the plurality of memory cells (FIG. 2, item MCAU2 and MCAL2) in the one of the plurality of memory cell groups (FIG. 2, item MCA1 and MCA2).
Regarding claim 20. Kim et al discloses a semiconductor structure (FIG. 2, item 100A), comprising:
a substrate (FIG. 2, item 110) comprising:
a memory cell area (FIG. 2, item CP);
at least one stacked structure (FIG. 2, item MCA) disposed on the memory cell area (FIG. 2, item CP) of the substrate (FIG. 2, item 110),
the at least one stacked structure (FIG. 2, item MCA) comprising
a plurality of memory cell groups (FIG. 2, item MCA1 and MCA2) arranged in a first direction (FIG. 2, item D3), each of the memory cell groups (FIG. 2, item MCA1 and MCA2) comprising multiple a plurality of layers (FIG. 2, item MCAU and MCAL) of memory cells (FIG. 2, item MCAU1/2 and MCAL1/2) arranged in a second direction (FIG. 2, item D1),
wherein the first direction (FIG. 2, item D3) is parallel to a surface of the substrate (FIG. 2, item 110), and the second direction (FIG. 2, item D1) is perpendicular ([0008]) to the surface of the substrate (FIG. 2, item 110);
a plurality of horizontal signal lines (FIG. 2, item WLL2, WLU2) arranged in the second direction (FIG. 2, item D1), and each of the horizontal signal lines (FIG. 2, item WLL2, WLU2) extending along the first direction (FIG. 2, item D3) and being connected to the memory cells (FIG. 2, item MCAU1/2 and MCAL1/2) of the plurality of memory cell groups (FIG. 2, item MCA1 and MCA2); and
a plurality of leading wire posts (FIG. 2, item BL1-4) disposed on the memory cell area (FIG. 2, item CP) of the substrate (FIG. 2, item 110), wherein at least two leading wire posts (FIG. 2, items BL2,4) of the plurality of leading wire posts (FIG. 2, item BL1-4) are individually provided to penetrate (FIG. 2, items BL2,4) different memory cell groups (FIG. 2, item MCA1 and MCA2) from the second direction (FIG. 2, item D3) and are disposed on different memory cells (FIG. 2, item MCAU1/2 and MCAL1/2) to electrically connect ([0042]) to at least two (FIG. 2, item WLL2, WLU2) the horizontal signal lines (FIG. 2, item WLL2, WLU2).
Claims 1, 11, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al (U.S. 2023/0157002).
Regarding claim 1. Lee et al discloses a semiconductor structure (FIG. 2), comprising:
a substrate (FIG. 2, item SUB) comprising:
a memory cell area (FIG. 2, item CAR and CNR);
at least one stacked structure (FIG. 2, item SS1) disposed on the memory cell area (FIG. 2, item CAR and CNR) of the substrate (FIG. 2, item SUB),
the at least one stacked structure (FIG. 2, item SS1) comprising
a plurality of memory cell groups (annotated FIG. 2, a plurality of item Memory Cell Group) arranged in a first direction (FIG. 2, item D1), each of the memory cell groups (annotated FIG. 2, item MCG) comprising a plurality (FIG. 2, item L1-L4) of memory cells (annotated FIG. 2, item MC; [0024]) arranged in a second direction (FIG. 2, item D3),
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wherein the first direction (FIG. 2, item D1) is parallel ([0029]) to a surface of the substrate (FIG. 2, item SUB), and the second direction (FIG. 2, item D3) is perpendicular ([0024]) to the surface of the substrate (FIG. 2, item SUB);
a plurality of horizontal signal lines (FIG. 2, a plurality of item WL) arranged in the second direction (FIG. 2, item D3), and each of the horizontal signal lines (FIG. 2, item WL) extending along the first direction (FIG. 2, item D1) and being connected ([0026]) to the memory cells (annotated FIG. 2, item MC; [0024]) of the plurality of memory cell groups (annotated FIG. 2, plurality of item MCG); and
a plurality of leading wire posts (FIG. 2, item CNT) disposed on the memory cell area (FIG. 2, item CAR and CNR) of the substrate (FIG. 2, item SUB), wherein at least two leading wire posts (FIG. 2, items L2 and L3 of item CNT) of the plurality of leading wire posts (FIG. 2, item CNT) are individually ([0050]) provided to penetrate different ([0050]) memory cell groups (annotated FIG. 2, item MCG) from the second direction (FIG. 2, item D3) and are disposed on different ([0050]) memory cells (annotated FIG. 2, item MC; [0024]) to electrically connect ([0051]) to at least two (FIG. 2, any two items L1, L2,L3,L4 of item WL) the horizontal signal lines (FIG. 2, items L1-L4 of item WL).
Regarding claim 11. Lee et al discloses the semiconductor structure (FIG. 2) according to claim 1 above.
Lee et al further discloses wherein a numbers of memory cells (annotated FIG. 2, item MC; [0024]) of different memory cell groups (annotated FIG. 2, item MCG) the which the at least two leading wire posts (FIG. 2, items L2 and L3 of item CNT) penetrate are different from each other (FIG. 2, items L2 and L3 of item CNT are different from each other on different layers)
Regarding claim 20. Lee et al discloses a semiconductor structure (FIG. 2), comprising:
a substrate (FIG. 2, item SUB) comprising:
a memory cell area (FIG. 2, item CAR and CNR);
at least one stacked structure (FIG. 2, item SS1) disposed on the memory cell area (FIG. 2, item CAR and CNR) of the substrate (FIG. 2, item SUB),
the at least one stacked structure (FIG. 2, item SS1) comprising
a plurality of memory cell groups (annotated FIG. 2, a plurality of item Memory Cell Group) arranged in a first direction (FIG. 2, item D1), each of the memory cell groups (annotated FIG. 2, item MCG) comprising a plurality (FIG. 2, item L1-L4) of memory cells (annotated FIG. 2, item MC; [0024]) arranged in a second direction (FIG. 2, item D3),
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wherein the first direction (FIG. 2, item D1) is parallel ([0029]) to a surface of the substrate (FIG. 2, item SUB), and the second direction (FIG. 2, item D3) is perpendicular ([0024]) to the surface of the substrate (FIG. 2, item SUB);
a plurality of horizontal signal lines (FIG. 2, a plurality of item WL) arranged in the second direction (FIG. 2, item D3), and each of the horizontal signal lines (FIG. 2, item WL) extending along the first direction (FIG. 2, item D1) and being connected ([0026]) to the memory cells (annotated FIG. 2, item MC; [0024]) of the plurality of memory cell groups (annotated FIG. 2, plurality of item MCG); and
a plurality of leading wire posts (FIG. 2, item CNT) disposed on the memory cell area (FIG. 2, item CAR and CNR) of the substrate (FIG. 2, item SUB), wherein at least two leading wire posts (FIG. 2, items L2 and L3 of item CNT) of the plurality of leading wire posts (FIG. 2, item CNT) are individually ([0050]) provided to penetrate different ([0050]) memory cell groups (annotated FIG. 2, item MCG) from the second direction (FIG. 2, item D3) and are disposed on different ([0050]) memory cells (annotated FIG. 2, item MC; [0024]) to electrically connect ([0051]) to at least two (FIG. 2, any two items L1, L2,L3,L4 of item WL) the horizontal signal lines (FIG. 2, items L1-L4 of item WL).
Claims 1, 2, 4, 6-8, 10, 12, 16-18, 20 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et al (U.S. 2020/0227418).
Regarding claim 1. Kim et al discloses a semiconductor structure (FIG. 1), comprising:
a substrate (FIG. 1, item 100) comprising:
a memory cell area ([0127]);
at least one stacked structure (FIG. 1, item SS) disposed on the memory cell area ([0127]) of the substrate (FIG. 1, item 100),
the at least one stacked structure (FIG. 1, item SS) comprising
a plurality of memory cell groups (FIG. 1, plurality of item memory cell groups) arranged in a first direction (FIG. 1, item D1), each of the memory cell groups (FIG. 1, item memory cell groups) comprising multiple a plurality (FIG. 1, item L1-L5) of memory cells (FIG. 1, item SP1) arranged in a second direction (FIG. 1, item D3),
wherein the first direction (FIG. 1, item D1) is parallel ([0005]) to a surface of the substrate (FIG. 1, item 100), and the second direction (FIG. 1, item D3) is perpendicular ([0005]) to the surface of the substrate (FIG. 1, item 100);
a plurality of horizontal signal lines (FIG. 1, a plurality of item CL1) arranged in the second direction (FIG. 1, item D1), and each of the horizontal signal lines (FIG. 1, item CL1) extending along the first direction (FIG. 1, item D1) and being connected ([0027]) to the memory cells (FIG. 1, item SP1) of the plurality of memory cell groups (FIG. 1, plurality of item memory cell groups); and
a plurality of leading wire posts (FIG. 1, a plurality of item CL3) disposed on the memory cell area ([0127]) of the substrate (FIG. 1, item 100), wherein at least two ([0032]) leading wire posts (FIG. 1, items CL3) of the plurality of leading wire posts (FIG. 1, plurality of item CL3) are individually provided to penetrate ([0032]) different memory cell groups (FIG. 1, item memory cell groups) from the second direction (FIG. 1, item D3) and are disposed on different memory cells (FIG. 1, item SP1) to electrically connect ([0042]) to at least two (FIG. 1, item CL1) the horizontal signal lines (FIG. 1, item CL1).
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Regarding claim 2. Kim et al discloses the semiconductor structure (FIG. 1) according to claim 1 above.
Kim et al further discloses wherein the plurality of leading wire posts (FIG. 1, item CL3) are arranged in either a linear pattern ([0032], i.e. The third conductive lines CL3 may be spaced apart from each other in the first direction D1) or a staggered pattern along the first direction (FIG. 1, item D1).
Regarding claim 4. Kim et al discloses the semiconductor structure (FIG. 1) according to claim 1 above.
Kim et al further discloses wherein a number (FIG. 1 shows six items CL3) of the plurality of leading wire posts (FIG. 1, item CL3) is equal to or greater (FIG. 1 shows six items CL3 is greater than item L1-L5) than a number (FIG. 1, item L1-L5) of the plurality (FIG. 1, item L1-L5) of memory cells in the second direction (FIG. 1, item D3)
Regarding claim 6. Kim et al discloses the semiconductor structure (FIG. 1) according to claim 1 above.
Kim et al further discloses wherein the stacked structure further comprises a plurality of vertical signal lines (FIG. 1, item CL2) arranged in the first direction (FIG. 1, item CL1), and each of the plurality of vertical signal lines (FIG. 1, item CL2) extending along the second direction (FIG. 1, item CL2) and being connected ([0032]) to the memory cells (FIG. 1, item SP1) of each of the plurality of memory cell groups (FIG. 1, item memory cell groups)
Regarding claim 7. Kim et al discloses the semiconductor structure (FIG. 1) according to claim 6 above.
Kim et al further discloses wherein each of the memory cells (FIG. 1, item SP1) comprises a channel region ([0026]) and a source/drain doped region ([0026]) arranged (FIG. 1, item DC or BC) in a third direction (FIG. 1, item D2), the source/drain doped region (FIG. 1, item DC or BC) is arranged at two sides ([0026]) of the channel region ([0026]), and the third direction (FIG. 1, item D2) is parallel to the surface of the substrate (FIG. 1, item 100).
Regarding claim 8. Kim et al discloses all the limitations of the semiconductor structure according to claim 7 above.
Kim et al further discloses wherein each of the plurality of horizontal signal lines (FIG. 1, plurality of item CL1) is a bit line ([0027]), and each of the plurality of vertical signal lines (FIG. 2, plurality of item CL2) is a word line ([0031]),
the bit line (FIG. 1, item CL1) is connected to the source/drain doped region (FIG. 2, item SD1), and the word line (FIG. 1, item CL2) is connected ([0026]) to the channel region ([0026]); and
at least one of the plurality of leading wire posts (FIG. 1, item CL3) penetrates ([0032]) the source/drain doped region (FIG. 1, item DC) in at least one of the memory cells (FIG. 1, item SP1), wherein the source/drain doped region (FIG. 1, item DC or BC) comprise a first source/drain doped region (FIG. 1, item DC) and a second source/drain doped region (FIG. 1, item BC), the first source/drain doped region (FIG. 1, item BC) is located between the bit line (FIG. 1, item CL1; [0027]) and the channel region ([0026]), and the second source/drain doped region (FIG. 1, item DC) is located at a side of the channel region ([0026]) deviating away from the first source/drain doped region (FIG. 1, item BC); and the leading wire post (FIG. 1, item CL3) penetrates through the first source/drain doped region (FIG. 1, item DC).
Regarding claim 10. Kim et al discloses all the limitations of the semiconductor structure according to claim 7 above.
Kim et la further discloses wherein each memory cell (FIG. 1, item SP1) further comprises a bit line contact area (FIG. 1, item DC or BC), the bit line contact area (FIG. 1, item BC or DC) connecting a bit line (FIG. 1, item CL1) to the source/drain doped region ([0026]), wherein at least one of the plurality of leading wire posts (FIG. 1, item CL3) penetrates through the bit line contact area (FIG. 1, item DC) in one of the memory cells (FIG. 1, item SP1).
Regarding claim 12. Kim et al discloses all the limitations of the semiconductor structure according to claim 1 above.
Kim et la further discloses wherein two adjacent leading wire posts (FIG. 1, item CL3) of the plurality of leading wire posts (FIG. 1, item CL3) are at least spaced ([0032], i.e. The third conductive lines CL3 may be spaced apart from each other in the first direction D1) by one of the plurality of memory cell groups (FIG. 1, item memory cell groups), wherein a number of memory cells (FIG. 1, item SP1) between the two adjacent leading wire posts (FIG. 1, item CL3) is fixed ([0032]), or an area of a directly facing region between the two adjacent leading wire posts is directly proportional to a number of memory cell groups between the two adjacent leading wire posts.
Regarding claim 16. Kim et al discloses all the limitations of the semiconductor structure according to claim 1 above.
Kim et al further discloses wherein at least one of the plurality of leading wire posts (FIG. 1, item CL3) extends in the second direction (FIG. 1, item D3) and penetrates at least one memory cell (FIG. 1, item SP1) in the memory cell group (FIG. 1, item memory cell groups),
the semiconductor structure (FIG.1) further comprises a dielectric layer ([0043]-[0046]) arranged between each leading wire post (FIG. 1, item CL3) and each memory cell (FIG. 1, item SP1) which the at least two ([0032]) leading wire posts (FIG. 1, item CL3) penetrates ([0032]).
Regarding claim 17. Kim et al discloses all the limitations of the semiconductor structure according to claim 16 above.
Kim et al further discloses wherein a bottom surface of each leading wire post is in contact with each memory cell, or at least a part of a side surface ([0032]) of each leading wire post (FIG. 1, item CL3) is in contact ([0032]) with each memory cell (FIG. 1, item SP1).
Regarding claim 18. Kim et al discloses all the limitations of the semiconductor structure according to claim 1 above.
Kim et al further discloses each of the plurality of memory cell groups (FIG. 1, item memory cell groups) is in contact ([0032]) with at least two of the plurality ([0032], i.e. A pair of third conductive lines CL3) of leading wire posts (FIG. 1, item CL3).
Regarding claim 20. Kim et al discloses a semiconductor structure (FIG. 1), comprising:
a substrate (FIG. 1, item 100) comprising:
a memory cell area ([0127]);
at least one stacked structure (FIG. 1, item SS) disposed on the memory cell area ([0127]) of the substrate (FIG. 1, item 100),
the at least one stacked structure (FIG. 1, item SS) comprising
a plurality of memory cell groups (FIG. 1, plurality of item memory cell groups) arranged in a first direction (FIG. 1, item D1), each of the memory cell groups (FIG. 1, item memory cell groups) comprising multiple a plurality (FIG. 1, item L1-L5) of memory cells (FIG. 1, item SP1) arranged in a second direction (FIG. 1, item D3),
wherein the first direction (FIG. 1, item D1) is parallel ([0005]) to a surface of the substrate (FIG. 1, item 100), and the second direction (FIG. 1, item D3) is perpendicular ([0005]) to the surface of the substrate (FIG. 1, item 100);
a plurality of horizontal signal lines (FIG. 1, a plurality of item CL1) arranged in the second direction (FIG. 1, item D1), and each of the horizontal signal lines (FIG. 1, item CL1) extending along the first direction (FIG. 1, item D1) and being connected ([0027]) to the memory cells (FIG. 1, item SP1) of the plurality of memory cell groups (FIG. 1, plurality of item memory cell groups); and
a plurality of leading wire posts (FIG. 1, a plurality of item CL3) disposed on the memory cell area ([0127]) of the substrate (FIG. 1, item 100), wherein at least two ([0032]) leading wire posts (FIG. 1, items CL3) of the plurality of leading wire posts (FIG. 1, plurality of item CL3) are individually provided to penetrate ([0032]) different memory cell groups (FIG. 1, item memory cell groups) from the second direction (FIG. 1, item D3) and are disposed on different memory cells (FIG. 1, item SP1) to electrically connect ([0042]) to at least two (FIG. 1, item CL1) the horizontal signal lines (FIG. 1, item CL1).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2020/0227418) as applied to claims 6 above, and further in view of Kim et al (U.S. 2022/0108988).
Regarding claim 13. Kim et al (‘418) discloses all the limitations of the semiconductor structure according to claim 6 above.
Kim et al (‘418) fails to explicitly disclose wherein a number of stacked structures is greater than one, the plurality of horizontal signal lines of a same stacked structure comprises a first horizontal signal line to N-th horizontal signal line successively arranged in the second direction, N being a positive integer greater than 1; and two stacked structures of the stacked structures constitute a structure module, the structural module further comprises a plurality of wires, the wire connects two leading wire posts, which are in contact with different stacked structures of the stacked structures, of the plurality of leading wire posts, and a sum of sequence numbers of two horizontal signal lines electrically connected to the two leading wire posts being N+1.
However,
Kim et al (‘988) teaches wherein a number of stacked structures is greater than one (FIG. 1, item 101-1 to 101-N), the plurality of horizontal signal lines of a same stacked structure comprises a first horizontal signal line (FIG. 1, item 107-1) to N-th horizontal signal line (FIG. 1, item 107-Q) successively arranged in the second direction (FIG. 1, item D3), N being a positive integer greater than 1 ([0019]-[0022]); and two stacked structures (FIG. 1, item 101-1 to 101-N) of the stacked structures (FIG. 1, item 101-1 to 101-N) constitute a structure module (FIG. 1, item 101-1 to 101-N), the structural module further comprises a plurality of wires ([0022]), the wire connects two leading wire posts ([0022]), which are in contact with different stacked structures ([0022]) of the stacked structures ([0022]), of the plurality of leading wire posts ([0022]), and a sum of sequence numbers of two horizontal signal lines electrically ([0022]) connected to the two leading wire posts being N+1 ([0022], i.e. The digit lines 107-1, 107-2, . . . , 107-Q may conductively interconnect memory cells along horizontal columns of each sub cell array 101-, 101-2, . . . , 101-N, and the access lines 103-1, 103-2, . . . , 103-Q may conductively interconnect memory cells along vertical rows of each sub cell array 101-1, 101-2, . . . , 101-N).
Since Kim et al (‘418) and Kim et al (‘988) teach memory structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor structure as disclosed to modify Kim et al (‘418) with the teachings of wherein a number of stacked structures is greater than one, the plurality of horizontal signal lines of a same stacked structure comprises a first horizontal signal line to N-th horizontal signal line successively arranged in the second direction, N being a positive integer greater than 1; and two stacked structures of the stacked structures constitute a structure module, the structural module further comprises a plurality of wires, the wire connects two leading wire posts, which are in contact with different stacked structures of the stacked structures, of the plurality of leading wire posts, and a sum of sequence numbers of two horizontal signal lines electrically connected to the two leading wire posts being N+1 as disclosed by Kim et al (‘988). The use of conductively interconnect memory cells along horizontal columns of each sub cell array, and the access lines may conductively interconnect memory cells along vertical rows of each sub cell array in Kim et al (‘988) provides for greater interconnection density as compared to conventional structures and processes, among other advantages (Kim et al (‘988), [0016]).
Regarding claim 14. Kim et al (‘418) and Kim et al (‘988) discloses all the limitations of the semiconductor structure according to claim 13 above.
Kim et al (‘988) further discloses wherein the two leading wire posts connected by the wire are arranged to be faced directly ([0022]), and an extension direction (FIG. 1, item D2) of the wire ([0022[) is perpendicular to the first direction (FIG. 1, item D1).
Regarding claim 15. Kim et al (‘418) and Kim et al (‘988) discloses all the limitations of the semiconductor structure according to claim 13 above.
Kim et al (‘988) further discloses wherein the memory cell (FIG. 2, item 230,227) comprises a transistor (FIG. 2, item 230) and a capacitor (FIG. 2, item 227) arranged in a third direction (FIG. 2, item 230),
in a same structure module (FIG. 1, items 101-1 to 101-N), the transistor (FIG. 1,item 110) of one stacked structure (FIG.1 , item 101-1) in the structure module (FIG. 1, items 101-1 to 101-N) is arranged facing (FIG. 1) to the transistor (FIG. 1, items 110) of another stacked structure (FIG. 101-2) in the structure module (FIG. 1, items 101-1 to 101-N);
or in a same structure module, the transistor of one stacked structure in the structure module is arranged in a same direction as the transistor of another stacked structure in the structure module;
or in a same structure module, the transistor of one stacked structure in the structure module is arranged in an opposite direction to the transistor of another stacked structure in the structure module.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
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/S.E.B./ Examiner, Art Unit 2815
/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
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