DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18-24, 27-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2009/0160035 A1 (Suzuki).
Re claim 18, Suzuki teaches a semiconductor device, being a chip-scale package, comprising a semiconductor die, the semiconductor die comprising:
an inner part and a perimeter part surrounding the inner part (see annotated Fig. 6),
wherein the semiconductor die comprises, in the perimeter part (see annotated Fig. 6), at least a remainder of a sawing line or dicing street that was used for singulating the semiconductor die from other semiconductor dies on a semiconductor wafer (mesa groove 16 is formed along scribe line DL1 which leaves a wider portion of layer 10 see Figs. 4-6 [0024]), and
a semiconductor vertical device realized inside the inner part (mesa diode having terminal 15 on bottom surface and top terminal 14 thus forming a vertical current device Fig. 6);
a passivation layer (first insulation film 13) arranged in at least the inner part of the semiconductor die;
a first surface (top), and a second surface (bottom) opposite to the first surface,
wherein the semiconductor die comprises at least one first terminal (anode 14) arranged at its first surface, at least one second terminal (cathode 15) that is arranged at its second surface and that is at least partially exposed through one or more openings in the passivation layer, and
sidewalls extending between the first and second surfaces;
a conformal coating (second insulation film 17) covering the perimeter part and at least a part of the sidewalls to prevent a short-circuit from occurring between the at least one first terminal and the at least one second terminal when mounting the device on a carrier (second insulation layer 17 is an insulating material and is physically in the path between the cathode 15 on the bottom surface and the anode 14 on the top surface thus providing further short circuit prevention between anode and cathode).
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Re claim 19, Suzuki teaches wherein the conformal coating at least partially covers the inner part of the first surface, the conformal coating comprising one or more openings through which the at least one second terminal is at least partially exposed (layer 17 is cut along scribe line DL1 which exposes a side surface of cathode 15 Fig. 6).
Re claim 20, Suzuki teaches wherein the conformal coating at least partially covers the passivation layer (layer 17 covers the side surface of 13 Fig. 6).
Re claim 21, Suzuki teaches wherein the one or more openings in the conformal coating are aligned with the one or more openings in the passivation layer for the purpose of exposing the at least one second terminal (the openings 16 between adjacent portions of 13 are filled layer 17, then a further opening is formed in 17 which exposes a side surface of cathode 15 Figs. 4-6).
Re claim 22, Suzuki teaches wherein the perimeter part is not, or not fully, covered by the passivation layer (see annotated Fig. 6 above).
Re claim 23, Suzuki teaches wherein the passivation is at least one of the group consisting of silicon nitride, silicon oxide, and silicon oxynitride ([0024]).
Re claim 24, Suzuki teaches wherein the at least one second terminal is provided with a plurality of islands comprising the conformal coating (Suzuki teaches that the verical device can be a three terminal device such as a mesa IGBT, mesa BJT, mesa MOSFET etc. these devices have at least three terminals wherein the source and gate are on the same surface in such instances 14 would need to be separate conductive portions to act as gate and input terminal on one surface whereas the bottom cathode remains the output terminal ([0044-0046]).
Re claim 27, Suzuki teaches wherein the vertical device is a device chosen from the group consisting of trench MOSFETs, planar MOSFETs, PN diodes, Schottky diodes, Zener diodes, and bipolar junction transistors, and/or wherein the semiconductor die comprises a conductive semiconductor substrate, being an n-type or p-type doped semiconductor substrate (Fig. 6).
Re claim 28, Suzuki teaches wherein the device comprises a normal direction that extends perpendicular to and from the first surface to the second surface, wherein the device is configured to be arranged on a carrier, that is a printed circuit board, with its normal direction parallel to the carrier, wherein the at least one first terminal is configured to be connected to at least one first contact pad on the carrier, and wherein the at least one second terminal is configured to be connected to at least one second contact pad on the carrier (the mesa diode is formed such that cathode 15 is able to be surface mounted on a contact pad of a carrier/PCB and the anode 14 is able to be connected to another contact pad by wiring or strap bonds, as the surfaces of both the anode and cathode are exposed the device of Suzuki is configured to be connected in the manner claimed Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0160035 A1 (Suzuki) further in view of US 2023/0023295 A1 (Chen).
Re claims 29 and 30, Suzuki teaches the semiconductor device according to claim 28, however, Suzuki does not further teach incorporating the vertical mesa diode into a system comprising: a carrier, that is a printed circuit board, comprising at least one first contact pad and at least one second contact pad spaced apart from the at least one first contact pad; and wherein the semiconductor device is mounted to the carrier with its normal direction parallel to the carrier; wherein the at least one first terminal is electrically connected to the at least one first contact pad using electrically conductive attaching material; and wherein the at least one second terminal is electrically connected to the at least one second contact pad using electrically conductive attaching material (claim 29), nor wherein the electrically conductive attaching material is one or more of the group consisting of solder, conductive glue, and silver sinter material (claim 30).
However, Suzuki does teach that the semiconductor device is a vertical two terminal PN junction diode having the bottom cathode and an upper anode. It is known in the art as taught by Chen that when mounting vertical diode devices 1 to a printed circuit board 3, the bottom electrode is connected to the carrier via a conductive adhesive layer 4 and upper electrode can be connected to bond pads 7 on the carrier using wire bonds (see Fig. 1 Chen). While the diode of Chen is a vertical light emissive diode the Chen reference is relied upon to show the obviousness of how mesa vertical diodes are attached to the carrier for operation. Since Suzuki does not provide any details about how the diodes are incorporated into a larger system the ordinary skilled artisan would need to look to analogous arts regarding the mounting of vertical diodes in order to discern how to attach the vertical diode of Suzuki to a circuit board so that it may be utilized for its intended purpose in an electronic circuit.
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Allowable Subject Matter
Claims 25 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art relies upon layer 17 being the conformal layer however, Suzuki teaches that this layer is an organic insulator which is formed by spin coating or spraying techniques in order to be thick enough to add structural support to the chip package. The required resins cannot be formed by ALD and even swapping the insulation material 17 for an inorganic insulator formed by ALD would be a tedious and expensive deposition process in order to get the required thicknesses of Suzuki for mechanical support.
Response to Arguments
Applicant's arguments filed 1/21/2026 have been fully considered but they are not persuasive. Applicant argues that the prior art does not teach “at least one second terminal that is arranged at its second surface and that is at least partially exposed through one or more openings in the passivation layer. Applicant argues that the cathode 15 is on the bottom side of the device while the passivation layer 13 is on the top side of the device so the limitation is not met. This argument is not persuasive. The exact wording of the claim requires “at least one second terminal that is arranged at its second surface (bottom surface cathode 15) and that is at least partially exposed through one or more openings (the openings extend from the top surface to the bottom surface of the device) in the passivation layer.
The passivation layer 13 is deposited and then patterned in Fig. 2 to form first openings
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Then the opening is further extended through the layers 12 and 11 is Fig. 4
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Finally the opening extends completely through the entire device which results is the sidewalls of the cathode 15 to be exposed by the extended opening.
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The claim does not require the passivation layer to be on the same side of the device as the cathode. If applicant believes that this is the contribution of the instant application over the prior then this should be positively recited in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896