DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over OH SOO-YOUNG (WO 03079240 A2), hereinafter SOO-YOUNG, in view of Thanh Vuong et al. (US 20040098688 A1), and Daisuke FUKUDA (US 20120047472 A1).
Regarding claim 1
SOO-YOUNG teaches part a-d, of claim 1
A dummy metal filling method
(SOO-YOUNG, p. 1, lines 13-15 “The present invention relates generally to semiconductor processing. More specifically, systems and methods for placement of dummy metal fills while preventing disturbance of device matching and optionally limiting capacitance increase are disclosed.”)
comprising:
providing an initial layout, wherein the initial layout comprises a potential line
(SOO-YOUNG: see elements 110, 112 on fig.1; p.4, Lines 8-11 “A computer-automated method for locating dummy fills in an integrated circuit fabrication process generally comprises receiving as input layout of the integrated circuit and specification of device matching for the integrated circuit and locating the dummy fills in the integrated circuit according to dummy rules while preserving device matching.”)
determining same-layer and same-net metal wires of each metal pattern layer based on a wiring connection relationship in the initial layout, wherein the same-layer and same- net metal wires are wirings positioned on a same metal pattern layer and connected to a same potential line
(SOO-YOUNG, p. 4 lines 19-22 “To also limit capacitance increase due to the dummy fills, the method may optionally further comprise designating at least one net of the integrated circuit as a critical net, the critical nets being only a subset of all nets of the integrated circuit, identifying metal conductors corresponding to each designated critical net from the layout file”)
determining a to-be-filled region in the each metal pattern layer based on the same-layer and same-net metal wires
(SOO-YOUNG, p. 6, lines 27-29 “FIG. 7 is a flow chart illustrating a computer-automated process that determines placement of dummy metal fills to facilitate in preserving device matching and/or limiting capacitance increase due to dummy metal fills;”)
(SOO-YOUNG, p. 12 lines 20-26 “At step 140, the locations of the dummy metal fills are determined in such a way so as to preserve device matching and optionally in accordance with the blocked areas as determined in step 138. In other words, the dummy metal fill locations are symmetric along the specified axes of symmetry and/or are matched among the repeated elements and optionally are only within the permissible areas outside of the blocked areas or zones. Any suitable dummy fill method such as a rule-based or a model-based dummy filling process may be implemented in order to achieve the desired planar profile.”)
SOO-YOUNG does not teach e-h part of claim 1
wherein when an interval between two adjacent same- layer and same-net metal wires meets a preset condition, determining a region between the two adjacent same-layer and same-net metal wires as the to-be-filled region
filling same-layer metal wires into the to-be-filled region in the each metal pattern layer, and adding a connection hole, such that the same-layer metal wires are connected to the same potential line
wherein the filling the same-layer metal wires is performed in a staggered filling manner, and the same-layer metal wires using the staggered filling manner are alternately connected to different potential lines
and adding dummy metal on a layout where the filling the same-layer metal wires is completed, to output a target layout.
However, Thanh Vuong et al. (US 20040098688 A1), hereinafter Vuong discloses
filling same-layer metal wires into the to-be-filled region in the each metal pattern layer, and adding a connection hole, such that the same-layer metal wires are connected to the same potential line
(Vuong, p. 4 [0074] “At 232, the metal-fill wires are processed with respect to tie-off nets (if they exist). In conventional systems, metal-fill is left floating on the chip. In the present invention, the metal-fill can be designed to tie-off at either power or ground. This aspect of the invention is illustrated in FIG. 12.”)
and adding dummy metal on a layout where the filling the same-layer metal wires is completed, to output a target layout.
(Vuong, p. 5 [0081] “FIG. 14 shows architecture for implementing the present metal-fill mechanism according to one embodiment of the invention. In this approach, the metal-fill mechanism 1412 is integrated into the layout/place & route tool 1402.”)
(Vuong, p. 2 [0027] “FIG. 2 shows a flowchart of a metal-fill procedure according to an embodiment of the invention. Some example inputs to this procedure are: (a) the minimum and maximum fill width and length; (b) minimum, maximum and preferred density; (c) design rule spacing, window size and step size; and (d) optional list of tie-off nets to connect to. In many cases, input parameters (a), (b), and (c) are specified by the chip manufacturer. As described in more detail below, the list of tie-off nets for (d) can be provided to connect the metal-fill to ground or power nets. The output of the procedure is a list of metal-fills inserted in the design.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of SOO-YOUNG and Vuong to form the method of dummy metal filling and to tie-off the metal fill at either power or ground for the obvious reason to prevent unpredictable electrical problem and deterioration of performance or function of the semiconductor circuit device
SOO-YOUNG and Vuong do not teach e and g part of claim 1
wherein when an interval between two adjacent same- layer and same-net metal wires meets a preset condition, determining a region between the two adjacent same-layer and same-net metal wires as the to-be-filled region
wherein the filling the same-layer metal wires is performed in a staggered filling manner, and the same-layer metal wires using the staggered filling manner are alternately connected to different potential lines
However, FUKUDA; Daisuke (US 20120047472 A1), hereinafter FUKUDA discloses
when an interval between two adjacent same-layer and same-net metal wires meets a preset condition, determining a region between the two adjacent same-layer and same-net metal wires as the to-be-filled region.
(FUKUDA, p.1 [0008] “Dummy metal fill for filling dummy metal (dummy wire) is a well-known technology for maintaining a uniform wire density and a uniform peripheral wire length. An area having a low wire density is filled with dummy metal in such a manner that the dummy metal is electrically disconnected from the real wire.”)
(FUKUDA, p. 4 [0081] “As described above, the dummy-metal-layout evaluating device used in the present embodiment separates a group of dummy metal blocks that is arranged in a pattern regularly staggered with respect to the direction in which a wire object extends into meshes so that each mesh has the same dummy metal layout. The dummy-metal-layout evaluating device determines whether a dummy metal block within each dummy mesh overlaps with a wire object. The dummy-metal-layout evaluating device calculates dummy information after dummy metal blocks that are determined to be overlapped with the wire object are removed, integrates the dummy information with the wire-object information, and evaluates whether the circuit layout filled with dummy satisfies the design criteria.”)
(FUKUDA, p. 3 [0056] “FIG. 3 is a schematic diagram of the layout of wire objects and dummy metal blocks.”)
(FUKUDA, p. 1 [0032] “FIG. 12 is a third schematic diagram of an example of the operation of the dummy-metal-layout evaluating device”)
wherein the filling the same-layer metal wires is performed in a staggered filling manner, and the same-layer metal wires using the staggered filling manner are alternately connected to different potential lines
(FUKUDA, p. 3 [0058] “FIG. 4B is a schematic diagram of another pattern of the layout of dummy metal blocks. As illustrated in FIG. 4b, a staggered pattern P2 (zigzag pattern), where dummy metal is in a pattern staggered with respect to the direction in which a wire object extends, the variation in area overlapping with upper-layered metal wires is small. This pattern can suppress the variation in wire volume and improves the yield rate.”)
(FUKUDA, p. 1 [0009] “As smaller circuit layouts are developed, the amount of dummy metal data is increased and, therefore, filling with dummy metal in a regular pattern is required. Moreover, to suppress variation in the volume component of layered wire, it is preferable to arrange dummy metal in a pattern staggered with respect to the direction in which a wire object extends (in a zigzag pattern). A wire object, herein, is a metal area that is connected to another wire object and works as a part of an electric circuit.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of SOO-YOUNG and Vuong with the teaching of FUKUDA making the to be filled region between the wire objects for maintaining a uniform wire density and a uniform peripheral wire length and dummy metal is electrically disconnected from the real wire, and further to pattern the dummy metal filling in a staggered manner and completing the circuit accordingly for the obvious reasons of minimizing cross talk effects and suppressing the variation in wire volume and improve yield rate.
Regarding claim 2
wherein the determining the same-layer and same-net metal wires of the each metal pattern layer based on the wiring connection relationship in the initial layout comprises:
SOO-YOUNG, Vuong, and FUKUDA teach all aspects of the independent claim 1 as disclosed above, and further disclose
determining, based on the wiring connection relationship in the initial layout, same-net metal wires connected to the same potential line; and2025 screening the same-net metal wires at a same metal pattern layer, to obtain the same-layer and same-net metal wires.
(Soo-Young, p. 5, lines 15-18 “To also limit capacitance increase due to the dummy fills, the method may optionally further comprise designating at least one net of the integrated circuit as a critical net, the critical nets being only a subset of all nets of the integrated circuit, identifying metal conductors corresponding to each designated critical net from the layout file,”)
Regarding claim 3
wherein before the filling the same-layer metal wires into the to-be-filled region in the each metal pattern layer, and adding the connection hole, such that the same-layer metal wires are connected to the same potential line, the method further comprises
SOO-YOUNG, Vuong, and FUKUDA teach all aspects of the independent claim 1 as disclosed above, and further disclose
determining filling information of the same-layer metal wires in each to-be-filled region based on the to-be-filled region and a preset filling parameter of the same-layer metal wires, to fill the to-be-filled region in the each metal pattern layer by using the filling information of the same-layer metal wires.
(SOO-YOUNG, p. 6 lines 27-29 “FIG. 7 is a flow chart illustrating a computer-automated process that determines placement of dummy metal fills to facilitate in preserving device matching and/or limiting capacitance increase due to dummy metal fills;”)
Further, Vuong discloses as mentioned before (Vuong, p. 2 [0027] “FIG. 2 shows a flowchart of a metal-fill procedure according to an embodiment of the invention. Some example inputs to this procedure are: (a) the minimum and maximum fill width and length; (b) minimum, maximum and preferred density; (c) design rule spacing, window size and step size; and (d) optional list of tie-off nets to connect to. In many cases, input parameters (a), (b), and (c) are specified by the chip manufacturer.”)
Regarding claim 4
SOO-YOUNG, Vuong, and FUKUDA teach all aspects of the claim 3 as disclosed above, and further disclose
wherein the filling parameter of the same-layer metal wires comprises at least one of a width of the same- layer metal wire, an interval between the same-layer metal wire and the same-layer and same-net metal wire, and an interval between adjacent same-layer metal wires.
(Vuong, p. 2 [0026] “ A disclosed embodiment calculates the best offset in each local area to be filled (e.g. minimum spacing from the existing metal), and dynamically adjust shape widths and different shape lengths that best fill that area. A metal-fill window will be processed in one pass, with possibly different sizes or shapes of metal-fill in the windows. An embodiment also simultaneously optimizes across multiple metal-fill windows such that that the process will not add shapes in a window that would exceed the maximum density, while attempting to make all windows match the preferred density and meeting the minimum density.”)
Regarding claim 5
SOO-YOUNG, Vuong, and FUKUDA teach all aspects of the claim 3 as disclosed above, and further disclose
wherein the filling information of the same-layer metal wires in the each to-be-filled region comprises at least one of filling number, filling positions, and actual filling intervals of the same-layer metal wires.
(Vuong, p. 2 [0027] “FIG. 2 shows a flowchart of a metal-fill procedure according to an embodiment of the invention. Some example inputs to this procedure are: (a) the minimum and maximum fill width and length; (b) minimum, maximum and preferred density; (c) design rule spacing, window size and step size; and (d) optional list of tie-off nets to connect to. In many cases, input parameters (a), (b), and (c) are specified by the chip manufacturer.”)
Claim 6 cancelled by the applicant.
Regarding claim 7
SOO-YOUNG, Vuong, and FUKUDA teach all aspects of the independent claim 1 as disclosed above, and further disclose
wherein the potential line comprises at least one of a power wire and a ground wire with different voltage values.
(Vuong, p. 4 [0074] “In the present invention, the metal-fill can be designed to tie-off at either power or ground. This aspect of the invention is illustrated in FIG. 12.”)
Claim 9 cancelled by the applicant.
Regarding claim 12
SOO-YOUNG, Vuong, and FUKUDA teach all aspects of the independent claim 1 as disclosed above, and further disclose
An electronic device, comprising: a processor; and a memory configured to store executable instructions of the processor; wherein the processor is configured to perform the dummy metal filling method according to claim 1 by executing the executable instructions.
(Soo-Young, p. 6 “FIG. 9 illustrates an example of a computer system that can be utilized with the various embodiments of method and processing described herein; and FIG. 10 illustrates a system block diagram of the computer system of FIG. 9.”)
Regarding claim 13
SOO-YOUNG, Vuong, and FUKUDA teach all aspects of the independent claim 1 as disclosed above, and further disclose
A computer-readable storage medium storing a computer program thereon, wherein the computer program is executable by the processor, whereby the dummy metal filling method according to claim 1 is implemented.
(Soo-Young, p. 6 “FIG. 9 illustrates an example of a computer system that can be utilized with the various embodiments of method and processing described herein; and FIG. 10 illustrates a system block diagram of the computer system of FIG. 9.”).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Stephan Hoerold (US 20080120586 A1), hereinafter Hoerold in view of Daisuke FUKUDA (US 20120047472 A1), hereinafter FUKUDA
Stephan Hoerold (US 20080120586 A1), hereinafter Hoerold teaches a-c, and e part of claim 11
A dummy metal filling apparatus, comprising: an initial layout providing module configured to provide an initial layout, wherein the initial layout comprises a potential line; a same-layer and same-net determination module configured to determine same- layer and same-net metal wires of each metal pattern layer based on a wiring connection relationship in the initial layout, wherein the same-layer and same-net metal wires are wirings positioned on a same metal pattern layer and connected to a same potential line;
(Hoerold, p. 1 [004] “FIG. 1 illustrates a typical design flow of an integrated circuit device from conception through the generation of a fabrication ready design layout.”)
(Hoerold, p. 1 [0005] “Once the design is verified for accuracy through simulation, a design layout is created, as indicated at 140.”)
(Hoerold, p. 2 [0026] “FIG. 12 illustrates a computer system suitable for implementing integrated circuit design using density-based design layer filling, according to one embodiment.”)
(Hoerold, p. 3 [0033] “FIGS. 3A-3B illustrate another example of the use of a flood filler. In this example, a portion of a layout design representing one design layer (e.g., metal 1) is illustrated in FIG. 3A. As shown in FIG. 3A, this design layer includes a plurality of metal shapes 310 and several open spaces 320 in the area illustrated. These metal shapes may represent signal wires ((e.g., signal wires 360) or power lines (e.g., VSS wires 350 and VDD wires 340).”)
a filling region determination module configured to determine a to-be-filled region in the each metal pattern layer based on the same-layer and same-net metal wires of each metal pattern layer wherein when an interval between two adjacent same-layer and same-net metal wires meets a preset condition, the filling region determination module is configured to determine a region between the two adjacent same-layer and same-net metal wires as the to-be- filled region
(Hoerold, p. 4 [0040] “In some embodiments, the density-based layer filler may access a configuration file, specifying design rules and checking windows for implementation of the filler. This is shown at 415 of FIG. 4. The configuration file may include minimum density rules for one or more layers of the target process technology/manufacturing facility combination. In some embodiments, the configuration file may also include minimum spacing rules, minimum width rules, minimum layer overlap rules, maximum layer density rules and/or any other design rules that may be usable by the density-based filler or a density-based fill flow.”)
a same-layer metal filling module configured to fill same-layer metal wires into the to-be-filled region in the each metal pattern layer, and add a connection hole, such that the same-layer metal wires are connected to the same potential line
(Hoerold, p. 7 [0063] “In some embodiments, two or more metal fill shapes may be connected to each other and only one of the fill shapes may be connected at an intersection point to an existing ground wire. In some embodiments, dummy metal shapes on two or more different metal layers may be connected to each other and then one of the shapes may be connected to a ground wire on yet another metal layer. Connecting added fill shapes to each other and then to a ground wire or power grid may in some embodiments involve inserting additional metal shapes and/or vias in the design to connect the fill shapes together and then adding vias between one or more of the connected shapes to a ground wire on the next lower or next higher metal layer, at a point where they intersect.”)
and a target layout output module configured to add dummy metal on a layout where the filling the same-layer metal wires is completed, to output a target layout.
(Hoerold, p. 5 [0046] “After the density-based filler has added shapes to the design for the targeted design layers, they may be copied to the design database and instantiated in the design cell, as shown in 450.”)
Hoerold does not teach
wherein fill same-layer metal wires is performed in a staggered filling manner, and the same-layer metal wires using the staggered filling manner are alternately connected to different potential lines
However, FUKUDA discloses
wherein fill same-layer metal wires is performed in a staggered filling manner, and the same-layer metal wires using the staggered filling manner are alternately connected to different potential lines
(FUKUDA, p. 3 [0058] “FIG. 4B is a schematic diagram of another pattern of the layout of dummy metal blocks. As illustrated in FIG. 4b, a staggered pattern P2 (zigzag pattern), where dummy metal is in a pattern staggered with respect to the direction in which a wire object extends, the variation in area overlapping with upper-layered metal wires is small. This pattern can suppress the variation in wire volume and improves the yield rate.”)
(FUKUDA, p. 1 [0009] “As smaller circuit layouts are developed, the amount of dummy metal data is increased and, therefore, filling with dummy metal in a regular pattern is required. Moreover, to suppress variation in the volume component of layered wire, it is preferable to arrange dummy metal in a pattern staggered with respect to the direction in which a wire object extends (in a zigzag pattern). A wire object, herein, is a metal area that is connected to another wire object and works as a part of an electric circuit.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Hoerold, and of FUKUDA to pattern the dummy metal filling in a staggered manner and completing the circuit accordingly for the obvious reasons of minimizing cross talk effects and suppressing the variation in wire volume and improve yield rate.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over SOO-YOUNG, Vuong, and FUKUDA as applied to claim 1 above, and further in view of Alexander Tetelbaum (US 20120284679 A1), hereinafter Tetelbaum.
Regarding claim 8
The dummy metal filling method according to claim 1, wherein the adding the dummy metal on the layout where the filling the same-layer metal wires is completed, to output the target layout comprises:
SOO-YOUNG, Vuong, Leung, and FUKUDA teach the independent claim 1 as disclosed above. They do not teach
adding the dummy metal on the layout where the filling the same-layer metal wires is completed; and verifying, based on a preset design rule, the layout where the filling the dummy metal is completed, to obtain a verification result; and when the verification result indicates successful verification, outputting the target layout succeeding in verification.
However, Tetelbaum discloses
adding the dummy metal on the layout where the filling the same-layer metal wires is completed; and verifying, based on a preset design rule, the layout where the filling the dummy metal is completed, to obtain a verification result; and when the verification result indicates successful verification, outputting the target layout succeeding in verification.
(Tetelbaum, p. 2 [0022] “Step 130 includes placing a minimum number of dummy metal objects in empty tracks such that the minimum metal density requirement is met for the areas (e.g., the tiles) that were found in step 115, but were not blocked in step 125. For example, in some embodiments of step 130, a single empty routing track for a particular area is filled with a dummy metal object, and the metal density for the area is recalculated. If the minimum metal density requirement is still not met, then a second empty routing track in a particular area is filled with a second dummy metal object, and the metal density for the area is again recalculated. The step-wise addition of dummy metal objects in this fashion can be repeated iteratively until the minimum metal density requirement is met for the area.”)
(Tetelbaum, p. 1 [0002] “Many integrated circuit (IC) manufacturing processes require a minimum metal density for the metal interconnections on each layer of a multi-layer IC chip design.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of SOO-YOUNG, Vuong, Leung, and FUKUDA with the teaching of Tetelbaum to complete the filling verifying that it met the minimum density required by the manufacturing process.
Regarding claim 10
The dummy metal filling method according to claim [[9]]1 wherein the preset condition comprises
SOO-YOUNG, Vuong, Leung, and FUKUDA teach the independent claim 1 as disclosed above. They do not teach
the interval between the two adjacent same-layer and same-net metal wires being greater than or equal to a preset interval threshold.
However, Tetelbaum discloses
the interval between the two adjacent same-layer and same-net metal wires being greater than or equal to a preset interval threshold.
(Tetelbaum, p. 3 [0032] “Some preferred embodiments of step 310 include a step 330 of the unblocking of the empty routing tracks to allow the placement of the dummy metals objects in the unblocked tracks (in step 315) such that a minimum area of the dummy metal object faces an adjacent wire of a critical net of the critical timing path. Minimizing the area of the dummy metal object that faces the adjacent wire also minimizes the capacitive coupling between the wire and the dummy metal object, thereby minimizing the delay time added to the critical net. Minimizing the delay time may be advantageous in cases, e.g., where the dummy metal object is placed next to a wire in a logic path nets or a launch clock net of a critical path that is at risk of a setup timing violation. At the same time, placing larger dummy metal object into the capture clock net will improve setup slack. This follows because the dummy metal objects placed so as to minimizing the delay time may mitigate causing a signal coming from a data path more slowly than desired and thereby causing a timing violation. Thus, it is important to know if the critical path is critical to a setup violation or to a hold violation. If the critical path is a setup critical path, then the design tool can preferably minimize any increase in delay in launch clock path or logic path, and increase delay in capture clock path. If the critical path is a hold critical path, then the design tool can preferably can minimize any increase in delay in capture clock path, and, increase delay in one or both of the logic path or capture clock path.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of SOO-YOUNG, Vuong, Leung, and FUKUDA with the teaching of Tetelbaum in minimizing the area of the dummy metal object that faces the adjacent wire to minimize the capacitive coupling between the wire and the dummy metal object.
Response to Arguments
Applicant's arguments filed 01/20/2026 have been fully considered but they are not persuasive.
Following is the response to the applicant’s arguments. The arguments have been broken down to sections to be able address the arguments appropriately.
Applicant’s Argument 1: First, with respect to original claim 1, the cited references, specifically the combination of OH SOO-YOUNG and Vuong Thanhet et al., lack a technical motivation for their combination. The core objective of OH SOO-YOUNG is to protect "device matching" in analog circuits, wherein the technical crux lies in a symmetrical, floating dummy metal layout.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case,
First, the title of the publication is “… PLACEMENT OF DUMMY METAL FILLS WHILE PRESERVING DEVICE MATCHING AND/OR LIMITING CAPACITANCE INCREASE.” Objective of OH SOO-YOUNG is not merely for device matching as erroneously stated by the applicant.
Further, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to be aware of the need to connect to the metal fill to either power or ground to prevent unpredictable electrical problem and deterioration of performance or function of the semiconductor circuit device.
Applicant’s Argument 2: Connecting these dummy metals to a potential line (the teaching of Vuong, Thanhet et al.) would introduce asymmetric parasitic capacitance, directly destroying such matching.
Response: The sentence begins with mischaracterization of Vuong’s work. Then it follows with a prediction without any evidence or proof.
Applicant’s Argument 3: This is diametrically opposed to the objective of OH SOO-YOUNG, which therefore provides explicit teaching away. A person having ordinary skill in the art, seeking to achieve the objectives of OH SOO-YOUNG, would have deliberately avoided combining it with the teachings of Vuong, Thanhet et al. Accordingly, the proposed combination lacks a reasonable motivation.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case,
it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to be aware of the need to connect to the metal fill to either power or ground to prevent unpredictable electrical problem and deterioration of performance or function of the semiconductor circuit device
A person having ordinary skill in the art would understand correctly the teachings of SOO-YOUNG and Vuong and would combine teaching to tie them to a potential (power or ground).
Applicant’s Argument 4: Secondly, amended claim 1 defines a highly sophisticated layout filling method
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., highly sophisticated layout filling method) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s Argument 5: This method not only intelligently selects filling regions
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., intelligently selects filling regions) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s Argument 6: but also performs functional filling in a unique "staggered and alternately connected" manner
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., functional filling) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s Argument 7: aiming to construct an active "interleaved finger shielding structure.”
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., interleaved finger shielding structure) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s Argument 8: This constitutes a complete, complex solution wherein multiple features function synergistically to resolve advanced signal integrity issues. The four references pieced together by the Examiner to reject original claim 6 were each directed to solving distinct problems (matching, density, iteration, and patterns). Their simple aggregation cannot yield the overall technical concept and synergistic technical effect of the present invention's "staggered potential structure designed for active shielding."
In response to applicant's argument that “The four references pieced together by the Examiner to reject original claim 6 were each directed to solving distinct problems (matching, density, iteration, and patterns).”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Applicant’s Argument 9: Specifically, the newly added feature in amended claim 1 (intelligent region selection, from claim 9. is not a generalized fill of arbitrary low-density regions as seen in IFUKUDA; Daisuke. Rather, based on preset conditions, it precisely targets critical areas "between metal lines of the same-layer and same-net" requiring electrical isolation.
In response to applicant's arguments against the references individually, one cannot show non obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant’s Argument 10: The other newly added feature (construction of a shielding structure, from claim 6) creates a microscopic interleaved finger-like comb structure by utilizing "staggered filling" and "alternately connecting to different potential lines" (e.g., Vdd and GND).
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., construction of a shielding structure and microscopic interleaved finger-like comb structure) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s Argument 11: The "staggered pattern" in IFUKUDA; Daisuke is merely a geometric arrangement to improve yield, and its fill shapes are either floating or connected to a single potential; it provides no teaching to modify them into an electrical functional structure featuring alternating connections to different potentials. Similarly, the grounding in Vuong, Thanhet et al. and Tetelbaum; Alexander involves only a simple single-potential connection, which cannot form the alternating potential shielding field of the present invention
In response to applicant's arguments against the references individually, one cannot show non obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.S./Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851