Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Non-Final office is a response to the papers filed on 11/26/2025.
Claims 1-12 are pending, claims 13-20 are cancelled.
Remark
In the Office Action, claims 1-20 were restricted under 35 U.S.C. 121 by a genus- species type restriction. The restriction indicated that Species I and Species II claims respectively fall into the following two groups:
I. Group I drawn claims 1-12 which disclose a method for creating a photonic device layout.
II. Group II drawn claims 13-20 which disclose an automated place and route system comprising a product development kit (PDK) cell library including parameters for standard silicon photonic (SiPh) device parameterized cells (Pcells).
Applicant’s election without traverse of Group I (claims 1-12) in the reply filed on 11/26/2025 is acknowledged.
Claims 13-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/26/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo et al. (US 20210057365 A1).
Regarding claim 1, Kuo discloses:
A method, comprising:
creating a photonic device layout (see par [0003], When the integrated circuit includes a silicon photonic (siPH) device such as a grating coupler….);
defining a plurality of dummy layers for the device layout including a port layer, an active layer, and a device layer (see par [0028-0032], [wherein DL_1 and DL_2 are the port layers, dummy layer SIPH_LVS is a active dummy layer, and SIPH_LVS_text is dummy device layer], see par [0063-0066], first dummy layer, dummy layer text, and second dummy layer);
applying layout vs schematic (LVS) connection rules based on the device layer (see par [0028-0029, 0032], The verification may include determining a connection and routing quality of the SiPH devices D1 through D3 of the optical die 220…. [connection rules have been applied when the verification is performing]);
recognizing a port of the photonic device based on the port layer (see par [0028-0029], he second dummy layer is added to the contact pads I/O_1_CMOS and I/O_3_CMOS of the E-dies 212 and 216, and is also added to the contact pads I/O_1_SIPH and I/O_3_SIPH of the optical dies…., [wherein I/O_1 to I/O_3….. have been recognized);
extracting a parameter of the photonic device based on the active layer, the device layer, and the port layer (see par [0041-0044], The parameterized cell base BC_1 may be used to generate the dummy layer SIPH_LVS and/or dummy layer text SIPH_LVS_text …., see par [0046-0049], the parameterized cell base BC_2 may be used to add a dummy layer to a connecting device that is connected to the customized SiPH devices…., [wherein a parameter has been extracted and used for dummy layers]; and
conducting an LVS verification based on the LVS rules, including verifying port connections of the photonic device (see par [0055-0056], a LVS check is performed on the optical die to verify the stacking of the electronic die and the optical die…, see par [0066-0070], performing a layout versus schematic check of the first electronic integrated circuit including the first dummy layer, the dummy layer text and the second dummy layer….).
Regarding claim 2, Kuo discloses:
wherein the plurality of dummy layers includes three or fewer layers (see par [0028-0032], [wherein DL_1 and DL_2 are the port layers, dummy layer SIPH_LVS is a active dummy layer, and SIPH_LVS_text is dummy device layer], see par [0063-0066], first dummy layer, dummy layer text, and second dummy layer).
Regarding claim 3, Kuo discloses:
wherein the device layer includes a Silicon Photonics (SiPh) device layer (see par [0009], FIGS. 4A through 4B are views of layouts of an optical die having a SiPH dummy layer …).
Regarding claim 4, Kuo discloses:
wherein the photonics device is a parameterized cell (Pcell) (see par [0038-0041], the textual representations or the name of the SiPH devices in the layout of the optical die may be determined based on a parameterized cell base…).
Regarding claim 5, Kuo discloses:
wherein conducting the LVS verification includes verifying device parameter correctness (see par [0041-0043] and [0062-0066]).
Regarding claim 6, Kuo discloses:
wherein the photonics device includes an optical layer and an electrical layer, and wherein the method further comprises applying optical LVS rules and electrical LVS rules (see par [0022-0024], [0032], and [0056]).
Regarding claim 7, Kuo discloses:
wherein verifying port connections includes verifying optical connections and electrical connections (see par [0031-0032], the LVS check may help to ensure that the electrical connection and routing of the SiPH devices in the optical die are correct…).
Regarding claim 8, Kuo discloses:
creating a configuration database correlating the plurality of dummy layers to a schematic (see par [0030] a SIPH graphic database system (GDS) check is performed to verify the SiPH devices in the optical die (e.g., O-die 120 of FIG. 1). The SIPH GDS check may be performed based on GDS files that include a layout representation ….).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (US 20210057365 A1) in view of Gage at al. (WO 2020086181 A2).
Regarding claim 9, Kuo discloses:
Kuo discloses photonic device layout (see par [0034], a location of the dummy layer SIPH_LVS added to the terminals of the SiPH devices. In some embodiments, the verification is failed if the layout of the optical die including the SiPH devices….)
However, Kuo fails to disclose:
providing a product development kit (PDK) cell library storing a plurality of standard photonic device layouts; and automatically placing and routing the photonic device layout and the plurality of standard photonic device layouts based on the configuration database.
Thus Gage discloses:
providing a product development kit (PDK) cell library storing a plurality of standard photonic device layouts (see par [00170], industry- standard tools and techniques: here, a standard process design kit (PDK) for CNFETs as well as a library…..); and automatically placing and routing the photonic device layout and the plurality of standard photonic device layouts based on the configuration database (see par [00210], facilitate automated and compact placement and routing, standard cells are designed with the convention of having standard cell height equal to 16 metal tracks….).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to have modified a method and a system for verifying an integrated circuit stack having at least one silicon photonic device of Kuo to include an automatically placing and routing in order to minimal cost (see Gage par [00167]).
Regarding claim 10, Gage discloses:
wherein automatically placing and routing is conducted by a computer system (see par [00125-00126], The system 2700 and/or the compute device 2710 can be or encompass a personal computer, a server, a workstation…).
Regarding claim 11, Kuo and Gage disclose:
wherein automatically placing and routing (see Gage par [00210], facilitate automated and compact placement and routing, standard cells are designed with the convention of having standard cell height equal to 16 metal tracks….) includes overlapping a first port connection location of the photonic device layout and a second port connection location of one of the plurality of standard photonic device layouts on a manufacturing grid (see Kuo par [0025], the contact pads of the electronic die 110 are configured to be aligned to the corresponding contact pads of the optical die 120. Misalignment of contact pads of the electronic die 110 and the corresponding contact pads of the optical die 120 may increase a risk of a short circuit [wherein aligned of the contact pads are the overlapping]).
Regarding claim 12, Gage discloses:
fabricating an integrated circuit (IC) based on the automatic placing and routing (see par [0086-0087], This is a list of all of the standard cells in a standard cell library as disclosed herein, along with a microscopy image of each fabricated standard cell, the schematic of each cell, and a typical measured waveform from each fabricated cell…).
Conclusion
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/BRIAN NGO/ Primary Examiner, Art Unit 2851