Prosecution Insights
Last updated: April 19, 2026
Application No. 18/155,988

SEMICONDUCTOR DEVICE

Final Rejection §103
Filed
Jan 18, 2023
Examiner
ONUTA, TIBERIU DAN
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
3y 2m
To Grant
96%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
44 granted / 60 resolved
+5.3% vs TC avg
Strong +23% interview lift
Without
With
+22.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
51 currently pending
Career history
111
Total Applications
across all art units

Statute-Specific Performance

§103
65.6%
+25.6% vs TC avg
§102
22.2%
-17.8% vs TC avg
§112
11.0%
-29.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 60 resolved cases

Office Action

§103
DETAILED ACTION This Office action responds to Applicant’s amendments filed on 12/26/2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-8, 12-14, and 18-20. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-3, 6-8, and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2017/0062308) in view of Seo (US 2017/0170136) in view of Tomoya (JP 2016122727) in further view of Hong (KR 102114932). Regarding claim 1, Choi shows (see, e.g., Choi: figs. 22 and 25) most aspects of the instant invention including semiconductor device, comprising: A substrate 100/160/180/240 A wiring pattern 260 disposed in the substrate 100/160/180/240 A passivation layer 315 disposed on the substrate 100/160/180/240 The passivation layer 315 and the substrate 100/160/180/240 including a first recess 230 The first recess 230 penetrating a part of the passivation layer 315 and a part of the substrate 100/160/180/240 and extending toward the wiring pattern 260 A post 230 connected to the wiring pattern 260 The post 230 comprising a first portion and a second portion The first portion disposed within the first recess 230, the second portion disposed on the first portion and protruding from a top surface of the passivation layer 315 in a vertical direction A signal bump 370 comprising a first seed layer 350 disposed on the post, a first lower bump 372 disposed on the first seed layer, and a first upper bump 374 disposed on the first lower bump 372 Choi, however, fails (see, e.g., Choi: figs. 22 and 25) to specify a heat transfer bump being spaced apart from the signal bump 370 in a horizontal direction. Seo, in a similar device to Choi, shows (see, e.g., Seo: figs. 3 and 7) a heat transfer bump BP-T being spaced apart from the signal bump BP-P in a horizontal direction (see, e.g., Seo: par. [0035]). Seo also shows (see, e.g., Seo: figs. 3 and 7) that the heat transfer bumps BP-T dissipate heat, which is generated during operation of the semiconductor chip 10, to the outside (see, e.g., Seo: par. [0035]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the heat transfer bump of Seo in the device of Choi, to dissipate heat, which is generated during operation of the semiconductor chip, to the outside. Choi in view of Seo shows (see, e.g., Seo: figs. 3 and 7) that: The heat transfer bump BP-T is electrically insulated from the wiring pattern (see, e.g., Seo: par. [0035]) The heat transfer bump BP-T comprises a second upper bump 164 disposed on the second lower bump 162 However, Choi in view of Seo fails (see, e.g., Choi: figs. 22 and 25, and also see, e.g., Seo: figs. 3 and 7) to show a second seed layer disposed on the passivation layer. Tomoya, in a similar device to Choi in view of Seo, shows (see, e.g., Tomoya: figs. 3A-B) a second seed layer 13 disposed on the passivation layer 12/4a that is on top of the substrate 2/11. Tomoya also shows (see, e.g., Tomoya: figs. 3A-B) that the second seed layer is formed to impart conductivity to the first thermal insulating layer 4a (see, e.g., Tomoya: par. [0017]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the second seed layer of Tomoya in the device of Choi in view of Seo, to impart conductivity to the first thermal insulating layer in contact with the seed layer. Choi in view of Seo in view of Tomoya (see, e.g., Tomoya: figs. 3A-B) shows that the second lower bump 6 is disposed on the second seed layer 13. Choi in view of Seo in view of Tomoya (see, e.g., Tomoya: figs. 2O, and figs. 3A-B) shows that a width of the second portion in a horizontal direction is greater than a width of the first portion in the horizontal direction, and the width of the first portion in the horizontal direction decreases toward the wiring pattern. However, Choi in view of Seo in view of Tomoya fails (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7, and also see, e.g., Tomoya: figs. 3A-B) to show that a width of the heat transfer bump BP-T in the horizontal direction is greater than a width of the signal bump BP-P in the horizontal direction (see, e.g., Seo: figs. 3 and 7). Hong, in a similar device to Choi in view of Seo in view of Tomoya, shows (see, e.g., Hong: figs. 2 and 3) that a width W1 of the heat transfer bump 172-1 in the horizontal direction is greater than a width W2 of the signal bump 162-1 in the horizontal direction. Hong also shows (see, e.g., Hong: figs. 2 and 3) that when width W1 is larger than the width W2, heat generated in the light emitting structure 130 (is taken by thermal bump portions 172-1) can be more easily discharged to the sub-mount 180 though the heat bump portions (see, e.g., Hong: par. [0080]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a width of the heat transfer bump that is greater than a width of the signal bump in the horizontal direction of Hong in the device of Choi in view of Seo in view of Tomoya, to eliminate the heat generated in the light emitting structure by easily discharging it to the sub-mount. However, the differences in the width of the heat transfer bump and of the signal bump in the horizontal direction will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Accordingly, since the applicant has not established the criticality (see next paragraph below) of the mentioned widths, and Hong has identified such widths as result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to use these width values in the device of Choi in view of Seo in view of Tomoya. CRITICALITY The specification contains no disclosure of either the critical nature of the claimed width values or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Regarding claim 2, Choi in view of Seo in view of Tomoya in view of Hong shows (see, e.g., Seo: figs. 3 and 7) that a first height of the signal bump BP-P from the top surface of the passivation layer 150 to a topmost point of the first upper bump 164 is same as a second height of the heat transfer bump BP-T from the top surface of the passivation layer 150 to a topmost point of the second upper bump 164 (see, e.g., Seo: par. [0061]). Regarding claim 3, Choi in view of Seo in view of Tomoya in view of Hong shows (see, e.g., Choi: figs. 22 and 25, and also see, e.g., Tomoya: figs. 3A-B) that the second seed layer 13 (see, e.g., Tomoya: figs. 3A-B) is lower than a portion of the first seed layer 350 that is disposed on a top surface of the post 230 (see, e.g., Choi: figs. 22 and 25) (the second seed layer 13 from the Tomoya reference passes all the way through the passivation layer 12/4a, while the first seed layer on the top surface of the post 230 from the Choi reference is higher; thus, the second seed layer 13 is lower than first seed layer on the top surface of the post 230). Regarding claim 6, Choi in view of Seo in view of Tomoya in view of Hong shows see, e.g., Choi: figs. 22 and 25, and also see, e.g., Tomoya: figs. 3A-B) that an entire bottom surface of the second seed layer 13 is in contact with the passivation layer 12/4a. Regarding claim 7, Choi in view of Seo in view of Tomoya in view of Hong shows (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7) that the substrate 300 comprises a first region PR in which the signal bump BP-P is disposed and a second region CR which surround the first region PR and has the heat transfer bump BP-T in the second region (see, e.g., Seo: figs. 16 and 17). Regarding claim 8, Choi in view of Seo in view of Tomoya in view of Hong shows (see, e.g., Choi: figs. 22 and 25, and also see, e.g., Tomoya: figs. 3A-B) an entirety of the second seed layer 13 is higher than the top surface of the substrate 2/11. Regarding claim 12, Choi in view of Seo in view of Tomoya in view of Hong shows (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7) that the width of the heat transfer bump BP-T in the horizontal direction is greater than a width of the second portion of the post in the horizontal direction 230 (the Seo reference shows that heat transfer bump BP-T in the horizontal direction is identical to any signal bump BP-P, thus, by reference combination, it is identical to the signal bumps from the Choi reference, where width of the heat transfer bump BP-T in the horizontal direction is greater than a width of the second portion of the post in the horizontal direction 230). However, the differences in the width of the heat transfer bump and of the second portion of the post in the horizontal direction will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Accordingly, since the applicant has not established the criticality (see next paragraph 21) of the mentioned widths, and Seo has identified such widths as result-effective variables subject to optimization (see, e.g., Seo: par. [0043]), it would have been obvious to one of ordinary skill in the art to use these width values in the device of Choi in view of Seo in view of Tomoya in view of Hong. Regarding claim 13, Choi shows (see, e.g., Choi: figs. 22 and 25) most aspects of the instant invention including semiconductor device, comprising: A substrate 100/160/180/240 A wiring pattern 260 disposed in the substrate 100/160/180/240 A passivation layer 315 disposed on the substrate 100/160/180/240 The passivation layer 315 and the substrate 100/160/180/240 including a first recess 230 The first recess 230 penetrating a part of the passivation layer 315 and a part of the substrate 100/160/180/240 and extending toward the wiring pattern 260 A post 230 connected to the wiring pattern 260 The post 230 comprising a first portion and a second portion The first portion disposed within the first recess 230, the second portion disposed on the first portion and protruding from a top surface of the passivation layer 315 in a vertical direction A signal bump 370 comprising a first seed layer 350 disposed on the post, a first lower bump 372 disposed on the first seed layer, and a first upper bump 374 disposed on the first lower bump 372 Choi, however, fails (see, e.g., Choi: figs. 22 and 25) to specify a heat transfer bump being spaced apart from the signal bump 370 in a horizontal direction. Seo, in a similar device to Choi, shows (see, e.g., Seo: figs. 3 and 7) a heat transfer bump BP-T being spaced apart from the signal bump BP-P in a horizontal direction (see, e.g., Seo: par. [0035]). Seo also shows (see, e.g., Seo: figs. 3 and 7) that the heat transfer bumps BP-T dissipate heat, which is generated during operation of the semiconductor chip 10, to the outside (see, e.g., Seo: par. [0035]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the heat transfer bump of Seo in the device of Choi, to dissipate heat, which is generated during operation of the semiconductor chip, to the outside. Choi in view of Seo shows (see, e.g., Seo: figs. 3 and 7) that: The heat transfer bump BP-T is electrically insulated from the wiring pattern (see, e.g., Seo: par. [0035]) The heat transfer bump BP-T comprises a second upper bump 164 disposed on the second lower bump 162 A first height of the signal bump BP-P from the top surface of the passivation layer 150 to a topmost point of the first upper bump 164 is same as a second height of the heat transfer bump BP-T from the top surface of the passivation layer 150 to a topmost point of the second upper bump 164 (see, e.g., Seo: par. [0061]). However, Choi in view of Seo fails (see, e.g., Choi: figs. 22 and 25, and also see, e.g., Seo: figs. 3 and 7) to show a second seed layer disposed on the passivation layer. Tomoya, in a similar device to Choi in view of Seo, shows (see, e.g., Tomoya: figs. 3A-B) a second seed layer 13 disposed on the passivation layer 12/4a that is on top of the substrate 2/11. Tomoya also shows (see, e.g., Tomoya: figs. 3A-B) that the second seed layer is formed to impart conductivity to the first thermal insulating layer 4a (see, e.g., Tomoya: par. [0017]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the second seed layer of Tomoya in the device of Choi in view of Seo, to impart conductivity to the first thermal insulating layer in contact with the seed layer. Choi in view of Seo in view of Tomoya (see, e.g., Tomoya: figs. 3A-B) shows that the second lower bump 6 is disposed on the second seed layer 13. Choi in view of Seo in view of Tomoya (see, e.g., Tomoya: figs. 2O, and figs. 3A-B) also shows that a width of the second portion in a horizontal direction is greater than a width of the first portion in the horizontal direction, and the width of the first portion in the horizontal direction decreases toward the wiring pattern. However, Choi in view of Seo in view of Tomoya fails (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7, and also see, e.g., Tomoya: figs. 3A-B) to show that a width of the heat transfer bump BP-T in the horizontal direction is greater than a width of the signal bump BP-P in the horizontal direction (see, e.g., Seo: figs. 3 and 7). Hong, in a similar device to Choi in view of Seo in view of Tomoya, shows (see, e.g., Hong: figs. 2 and 3) that a width W1 of the heat transfer bump 172-1 in the horizontal direction is greater than a width W2 of the signal bump 162-1 in the horizontal direction. Hong also shows (see, e.g., Hong: figs. 2 and 3) that when width W1 is larger than the width W2, heat generated in the light emitting structure 130 (is taken by thermal bump portions 172-1) can be more easily discharged to the sub-mount 180 though the heat bump portions (see, e.g., Hong: par. [0080]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a width of the heat transfer bump that is greater than a width of the signal bump in the horizontal direction of Hong in the device of Choi in view of Seo in view of Tomoya, to eliminate the heat generated in the light emitting structure by easily discharging it to the sub-mount. However, the differences in the width of the heat transfer bump and of the signal bump in the horizontal direction will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Accordingly, since the applicant has not established the criticality (see next paragraph 21) of the mentioned widths, and Hong has identified such widths as result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to use these width values in the device of Choi in view of Seo in view of Tomoya. Regarding claim 14, Choi in view of Seo in view of Tomoya in view of Hong shows (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7, and also see, e.g., Tomoya: figs. 3A-B) that: A signal bump 370 comprising a first seed layer 350 disposed on the post, a first lower bump 372 disposed on the first seed layer, and a first upper bump 374 disposed on the first lower bump 372 (see, e.g., Choi: figs. 22 and 25) The heat transfer bump BP-T comprises a second upper bump 164 disposed on the second lower bump 162 (see, e.g., Seo: figs. 3 and 7) The heat transfer bump 6 comprises a second seed layer 13 disposed on the passivation layer 12/4a 13 (see, e.g., Tomoya: figs. 3A-B) The second lower bump 6 is disposed on the second seed layer 13 (see, e.g., Tomoya: figs. 3A-B) The second seed layer 13 (see, e.g., Tomoya: figs. 3A-B) is lower than a portion of the first seed layer 350 that is disposed on a top surface of the post 230 (see, e.g., Choi: figs. 22 and 25) (the second seed layer 13 from the Tomoya reference passes all the way through the passivation layer 12/4a, while the first seed layer on the top surface of the post 230 from the Choi reference is higher; thus, the second seed layer 13 is lower than first seed layer on the top surface of the post 230). Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Seo in view of Tomoya in view of Hong in further view of Sakamoto (US 2016/0066423). Regarding claim 4, Choi in view of Seo in view of Tomoya in view of Hong shows (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7) most aspects of the instant invention including a post 230, a first lower bump 372, and the first seed layer 350 (see, e.g., Choi: figs. 22 and 25). Choi in view of Seo in view of Tomoya in view of Hong also shows (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7) that the post 220 (made of copper (Cu); see, e.g., Choi: par. [0120]) and the first lower bump 162 (made of copper (Cu); see, e.g., Seo: par: [0059]) include the same material. However, Choi in view of Seo in view of Tomoya in view of Hong fails (see, e.g., Choi: figs. 22 and 25) to show that the first seed layer 350 includes a material different from that of the post 220 and that of the first lower bump 162. Choi in view of Seo in view of Tomoya in view of Hong shows (see, e.g., Choi: figs. 22 and 25) that the first seed layer 350 includes the same material (copper (Cu)) as that of the post 220 and that of the first lower bump 162 (see, e.g., Choi: par: [0142]). Sakamoto, in a similar device to Choi in view of Seo in view of Tomoya in view of Hong, teaches (see, e.g., Sakamoto: fig. 5A) a first seed layer 33 that is made from titanium (Ti) (see, e.g., Sakamoto: par. [0034]). Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the first seed layer of titanium (Ti) of Sakamoto or the first seed layer of copper (Cu) of Choi in view of Seo in view of Tomoya in view of Hong because these were recognized in the semiconductor art for their use as interconnect layers between posts and solder bumps, as taught by Sakamoto and by Choi in view of Seo in view of Tomoya in view of Hong, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007). Thus, Choi in view of Seo in view of Tomoya in view of Hong in view of Sakamoto teaches that the first seed layer 33 (see, e.g., Sakamoto: fig. 5A) includes a material different from that of the post 220 and that of the first lower bump 162 (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Seo in view of Tomoya in view of Hong in view of Sakamoto in further view of Lee (US 2019/0131269). Regarding claim 5, Choi in view of Seo in view of Tomoya in view of Hong in view of Sakamoto shows (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7) most aspects of the instant invention including a post 230, a first lower bump 372, and the first seed layer 350 (see, e.g., Choi: figs. 22 and 25). Choi in view of Seo in view of Tomoya in view of Hong in view of Sakamoto shows (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7) that the first lower bump 372 includes nickel (Ni) and that the first see layer 350 includes copper (Cu). However, Choi in view of Seo in view of Tomoya in view of Hong in view of Sakamoto fails (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7) to show that the post 230 includes nickel (Ni). Choi in view of Seo in view of Tomoya in view of Hong in view of Sakamoto shows that post 230 includes copper (Cu) (see, e.g., Choi: par. [0120]). Lee, in a similar device to Choi in view of Seo in view of Tomoya in view of Hong in view of Sakamoto, teaches (see, e.g., Lee: fig. 1G) a post 106 that is made from nickel (Ni) (see, e.g., Lee: par. [0018]). Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the post of nickel (Ni) of Lee or the post of copper (Cu) of Choi in view of Seo in view of Tomoya in view of Hong in view of Sakamoto because these were recognized in the semiconductor art for their use as interconnect post between below solder bumps, as taught by Sakamoto and by Choi in view of Seo in view of Tomoya in view of Hong, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007). Thus, Choi in view of Seo in view of Tomoya in view of Hong in view of Sakamoto in view of Lee teaches that the post 106 (see, e.g., Lee: fig. 1G) and the first lower bump 162 (see, e.g., Choi: figs. 22 and 25) both include nickel (Ni). Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2017/0062308) in view of Seo (US 2017/0170136) in view of Tomoya (JP 2016122727) in further view of Sakamoto (US 2016/0066423). Regarding claim 18, Choi shows (see, e.g., Choi: figs. 22 and 25) most aspects of the instant invention including semiconductor device, comprising: A substrate 100/160/180/240 A wiring pattern 260 disposed in the substrate 100/160/180/240 A passivation layer 315 disposed on the substrate 100/160/180/240 The passivation layer 315 and the substrate 100/160/180/240 including a first recess 230 The first recess 230 penetrating a part of the passivation layer 315 and a part of the substrate 100/160/180/240 and extending toward the wiring pattern 260 A post 230 connected to the wiring pattern 260 The post 230 comprising a first portion and a second portion The first portion disposed within the first recess 230, the second portion disposed on the first portion and protruding from a top surface of the passivation layer 315 in a vertical direction A signal bump 370 comprising a first seed layer 350 disposed on the post, a first lower bump 372 disposed on the first seed layer, and a first upper bump 374 disposed on the first lower bump 372 Choi, however, fails (see, e.g., Choi: figs. 22 and 25) to specify a heat transfer bump being spaced apart from the signal bump 370 in a horizontal direction. Seo, in a similar device to Choi, shows (see, e.g., Seo: figs. 3 and 7) a heat transfer bump BP-T being spaced apart from the signal bump BP-P in a horizontal direction (see, e.g., Seo: par. [0035]). Seo also shows (see, e.g., Seo: figs. 3 and 7) that the heat transfer bumps BP-T dissipate heat, which is generated during operation of the semiconductor chip 10, to the outside (see, e.g., Seo: par. [0035]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the heat transfer bump of Seo in the device of Choi, to dissipate heat, which is generated during operation of the semiconductor chip, to the outside. Choi in view of Seo shows (see, e.g., Seo: figs. 3 and 7) that: The heat transfer bump BP-T is electrically insulated from the wiring pattern (see, e.g., Seo: par. [0035]) The heat transfer bump BP-T comprises a second upper bump 164 disposed on the second lower bump 162 However, Choi in view of Seo fails (see, e.g., Choi: figs. 22 and 25, and also see, e.g., Seo: figs. 3 and 7) to show a second seed layer disposed on the passivation layer. Tomoya, in a similar device to Choi in view of Seo, shows (see, e.g., Tomoya: figs. 3A-B) a second seed layer 13 disposed on the passivation layer 12/4a that is on top of the substrate 2/11. Tomoya also shows (see, e.g., Tomoya: figs. 3A-B) that the second seed layer is formed to impart conductivity to the first thermal insulating layer 4a (see, e.g., Tomoya: par. [0017]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the second seed layer of Tomoya in the device of Choi in view of Seo, to impart conductivity to the first thermal insulating layer in contact with the seed layer. Choi in view of Seo in view of Tomoya shows (see, e.g., Tomoya: figs. 3A-B) that the second lower bump 6 is disposed on the second seed layer 13. Choi in view of Seo in view of Tomoya shows (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7) that the width of the heat transfer bump BP-T in the horizontal direction is greater than a width of the second portion of the post in the horizontal direction 230 (the Seo reference shows that heat transfer bump BP-T in the horizontal direction is identical to any signal bump BP-P, thus, by reference combination, it is identical to the signal bumps from the Choi reference, where width of the heat transfer bump BP-T in the horizontal direction is greater than a width of the second portion of the post in the horizontal direction 230). Choi in view of Seo in view of Tomoya shows (see, e.g., Choi: figs. 22 and 25, and also see, e.g., Tomoya: figs. 3A-B) that the second seed layer 13 (see, e.g., Tomoya: figs. 3A-B) is lower than a portion of the first seed layer 350 that is disposed on a top surface of the post 230 (see, e.g., Choi: figs. 22 and 25) (the second seed layer 13 from the Tomoya reference passes all the way through the passivation layer 12/4a, while the first seed layer on the top surface of the post 230 from the Choi reference is higher; thus, the second seed layer 13 is lower than first seed layer on the top surface of the post 230). Choi in view of Seo in view of Tomoya (see, e.g., Tomoya: figs. 2O, and figs. 3A-B) shows that a width of the second portion in a horizontal direction is greater than a width of the first portion in the horizontal direction, and the width of the first portion in the horizontal direction decreases toward the wiring pattern. However, Choi in view of Seo in view of Tomoya fails (see, e.g., Choi: figs. 22 and 25) to show that the first seed layer 350 includes a material different from that of the post 220 and that of the first lower bump 162. Choi in view of Seo in view of Tomoya in view of Hong shows (see, e.g., Choi: figs. 22 and 25) that the first seed layer 350 includes the same material (copper (Cu)) as that of the post 220 and that of the first lower bump 162 (see, e.g., Choi: par: [0142]). Sakamoto, in a similar device to Choi in view of Seo in view of Tomoya, teaches (see, e.g., Sakamoto: fig. 5A) a first seed layer 33 that is made from titanium (Ti) (see, e.g., Sakamoto: par. [0034]). Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the first seed layer of titanium (Ti) of Sakamoto or the first seed layer of copper (Cu) of Choi in view of Seo in view of Tomoya because these were recognized in the semiconductor art for their use as interconnect layers between posts and solder bumps, as taught by Sakamoto and by Choi in view of Seo in view of Tomoya, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007). Thus, Choi in view of Seo in view of Tomoya in view of Sakamoto teaches that the first seed layer 33 (see, e.g., Sakamoto: fig. 5A) includes a material different from that of the post 220 and that of the first lower bump 162 (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7). Regarding claim 20, Choi in view of Seo in view of Tomoya in view of Sakamoto shows (see, e.g., Seo: figs. 3 and 7) that a first height of the signal bump BP-P from the top surface of the passivation layer 150 to a topmost point of the first upper bump 164 is same as a second height of the heat transfer bump BP-T from the top surface of the passivation layer 150 to a topmost point of the second upper bump 164 (see, e.g., Seo: par. [0061]). Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Seo in view of Tomoya in view of Sakamoto in further view of Hong (KR 102114932). Regarding claim 19, Choi in view of Seo in view of Tomoya in view of Sakamoto shows (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7, and also see, e.g., Tomoya: figs. 3A-B) the heat transfer bump BP-T and the signal bump BP-P (see, e.g., Seo: figs. 3 and 7). However, Choi in view of Seo in view of Tomoya in view of Sakamoto fails (see, e.g., Choi: figs. 22 and 25, and see, e.g., Seo: figs. 3 and 7, and also see, e.g., Tomoya: figs. 3A-B) to show that a width of the heat transfer bump BP-T in the horizontal direction is greater than a width of the signal bump BP-P in the horizontal direction (see, e.g., Seo: figs. 3 and 7). Hong, in a similar device to Choi in view of Seo in view of Tomoya in view of Sakamoto, shows (see, e.g., Hong: figs. 2 and 3) that a width W1 of the heat transfer bump 172-1 in the horizontal direction is greater than a width W2 of the signal bump 162-1 in the horizontal direction. Hong also shows (see, e.g., Hong: figs. 2 and 3) that when width W1 is larger than the width W2, heat generated in the light emitting structure 130 (is taken by thermal bump portions 172-1) can be more easily discharged to the sub-mount 180 though the heat bump portions (see, e.g., Hong: par. [0080]). It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a width of the heat transfer bump that is greater than a width of the signal bump in the horizontal direction of Hong in the device of Choi in view of Seo in view of Tomoya in view of Sakamoto, to eliminate the heat generated in the light emitting structure by easily discharging it to the sub-mount. However, the differences in the width of the heat transfer bump and of the signal bump in the horizontal direction will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Accordingly, since the applicant has not established the criticality (see next paragraph below) of the mentioned widths, and Hong has identified such widths as result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to use these width values in the device of Choi in view of Seo in view of Tomoya in view of Sakamoto. Response to Arguments Applicants’ arguments have been considered but are moot in view of the new grounds of rejection. Examiner has read and considered Applicants’ arguments, and finds them to be unpersuasive. Applicant’s arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitation. Examiner believes that the Kikuchi in view of Deen discloses the amended limitation. The applicability of Kikuchi reference and Deen reference to the amended limitation is indicated in the claim rejections above. The applicants argue: Choi in view of Seo in view of Tomoya fails to anticipate or render obvious the amended limitation of "… a width of the second portion in a horizontal direction is greater than a width of the first portion in the horizontal direction, and the width of the first portion in the horizontal direction decreases toward the wiring pattern", as recited in claims 1, 13, and 18. The examiner responds: In view of the new grounds of rejection, Choi in view of Seo in view of Tomoya (see, e.g., Tomoya: figs. 2O, and figs. 3A-B) clearly shows that a width of the second portion in a horizontal direction is greater than a width of the first portion in the horizontal direction, and the width of the first portion in the horizontal direction decreases toward the wiring pattern. Conclusion This action is made final. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /TIBERIU DAN ONUTA/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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Prosecution Timeline

Jan 18, 2023
Application Filed
Oct 01, 2025
Non-Final Rejection — §103
Oct 28, 2025
Interview Requested
Nov 04, 2025
Examiner Interview Summary
Nov 04, 2025
Applicant Interview (Telephonic)
Dec 26, 2025
Response Filed
Feb 25, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
96%
With Interview (+22.9%)
3y 2m
Median Time to Grant
Moderate
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