DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 8-9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto et al. (US 5672414) in view of Kitajima et al. (US 2013/0313309 A1).
Re Claim 1, Okamoto show and disclose
A high frequency module comprising:
a mounting substrate (85, fig. 9) having a first main surface (top) and a second main surface (bottom), the first main surface and the second main surface facing each other (see 112 rejection above);
a circuit component (7, fig. 9) mounted on the first main surface of the mounting substrate;
a resin layer (filled resin, fig. 9) disposed on the first main surface of the mounting substrate and covering at least a part of an outer peripheral surface of the circuit component (fig. 9); and
a shield layer (71A, fig. 9) covering at least a part of the resin layer and a main surface of the circuit component farther from the mounting substrate (fig. 9),
wherein a gap is arranged at least one of a position between the circuit component and the resin layer, a position between the circuit component and the shield layer (fig. 9), a position inside the resin layer, and a position inside the shield layer.
But, Okamoto does not explicitly teach wherein a gap is arranged at a position between the circuit component and the resin layer.
However, Kitajima et al. teaches wherein a gap (7) is arranged at a position between the circuit component (5) and the resin layer (6, see paragraph [0108]).
Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide wherein a gap is arranged at a position between the circuit component and the resin layer in the device of Okamoto based on the teaching of Kitajima et al. in order to provide stress relief and prevents cracking or peeling caused by temperature changes.
Re Claim 2, Okamoto show and disclose
The high frequency module according to Claim 1, wherein the circuit component includes a substrate (4, fig. 9), and wherein the gap is arranged at at least one of a position between the substrate of the circuit component and the resin layer and a position between the substrate of the circuit component and the shield layer (fig. 9).
Re Claim 8, Okamoto show and disclose
The high frequency module according to Claim 1, wherein the gap (gap in 74A, fig. 9) is arranged along a thickness direction of the shield layer inside the shield layer (fig. 9), and overlaps with an interface between the circuit component and the resin layer in the thickness direction of the shield layer (fig. 9).
Re Claim 9, Okamoto show and disclose
The high frequency module according to Claim 1, wherein a thickness of a part of the shield layer provided on the main surface of the circuit component is set to a first thickness (thickness of 71A in area with top component 7, fig. 9), wherein a thickness of a part of the shield layer provided on a main surface of the resin layer farther from the mounting substrate is set to a second thickness (thickness of 71A with gap in 74A, fig. 9), and wherein the first thickness is more than the second thickness (fig. 9).
Re Claims 17, Okamoto show and disclose
The high frequency module according to Claim 2, wherein the gap (gap in center of layer 74A, fig. 9) is arranged along a thickness direction of the shield layer inside the shield layer (fig. 9), and does not overlap with an interface between the circuit component and the resin layer in the thickness direction of the shield layer (fig. 9).
Re Claim 10, Okamoto show and disclose
The high frequency module according to Claim 1,
Okamoto disclosed claimed invention except for the high frequency module is used in a communication apparatus module, and a signal processing circuit connected to the high frequency module and performs signal processing on a high frequency signal, since Okamoto disclosed the high frequency module, and the high frequency module is capable to be used in a communication apparatus module, and connect to a signal processing circuit to perform signal processing on a high frequency; therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to use the high frequency module in a communication, in order to make a complete working system for the electronic device; and since this limitation is a intended-use limitation (be used in a communication apparatus module, and to perform signal processing on a high frequency); and since it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 UAPQ2d 1647 (1987).
Claims 5, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto et al., in view of Kitajima et al. (US 2013/0313309 A1) as applied to claim 1 above, and further in view of Shiga (US5723904).
Re Claims 5 and 14, Okamoto show and disclose
The high frequency module according to Claims 1 and 2, respectively,
Okamoto does not disclose
wherein the main surface of the circuit component includes a plurality of ground marks.
Shiga teaches a device wherein
wherein the main surface of the circuit component includes a plurality of ground marks (the ground lines are located at the upper surface of the IC chip, [col. 3, line 53]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to add ground lines on main surface of the circuit component as taught by Shiga, in order to make ground connections easily for the electronic device.
Re Claim 20, Okamoto show and disclose
The high frequency module according to Claim 5, wherein the gap (gap in center of layer 74A, fig. 9) is arranged along a thickness direction of the shield layer inside the shield layer (fig. 9), and does not overlap with an interface between the circuit component and the resin layer in the thickness direction of the shield layer (fig. 9).
Response to Arguments
5. Applicant's arguments with respect to claims 1-2, 5, 8-10, 14, 17 and 20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDARGIE M AYCHILLHUM whose telephone number is (571)270-1607. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDARGIE M AYCHILLHUM/ Primary Examiner, Art Unit 2847
Prosecution Insights