DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 9/12/2025. Claims 1-20 are pending in this application. Claims 1-3, 6, 11, and 13 are amended. Claims 14-20 remain withdrawn.
Claims 1-13 are presented in this Office Action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over by Colinge et al. (US 2019/0103496; hereinafter ‘Colinge’) in view of Chen (US 2018/0247584).
Regarding claim 1, Colinge teaches a semiconductor device (200, FIG. 6, [0071-0072]) comprising:
a two-dimensional (2D) material layer (the lower portion of multilayer sheet 210, as 210 is described as being formed by CVD/ALD/epitaxial processes, and thus reasonably interpreted as a multilayer 2D composite in which the lower monolayer set corresponds to the 2D material layer, [0064-0065]; hereinafter ‘2D210’) including a 2D semiconductor material (210 including graphene, phosphorene, TMDs) having a polycrystalline structure (annealing increases the domain size and reduces defects),
the 2D material layer (2D210) including a sheet member (a portion of 2D210 extending laterally along the upper surface of 206, wherein the portion corresponds to the lower monolayer set positioned along the lateral region, FIG. 5; hereinafter ‘2D210S’) and at least one protrusion (a portion of 2D210 rising along the adjacent 208, wherein the portion corresponds to the same lower monolayer set positioned along the vertical region of the fin gate structure; hereinafter ‘2D210P’), the sheet member (2D210S) extending along one plane (x-direction) and the at least one protrusion (2D210P) extending in one direction perpendicular to the one plane (y-direction);
a source electrode (216S) and a drain electrode (216D) spaced apart from each other on the 2D material layer (shown in FIG. 6);
a gate insulating layer (212) and a gate electrode (214) on the 2D material layer (2D210) between the source electrode (216S) and the drain electrode (216D); and
graphene layers (the upper portion of the same multilayer sheet 210 positioned above 2D210, the upper monolayer set within 210; hereinafter ‘G210’) on both sides of the gate insulating layer (212), the graphene layers (G210) covering a part of the sheet member (the upper surface of 2D210S).
Colinge does not teach the semiconductor device comprising: the graphene layers covering an upper surface and side surfaces of the at least one protrusion.
Chen teaches a semiconductor device (FIG. 2, [0018]) comprising: the graphene layers (8 and 12, [0021-0023]) covering an upper surface and side surfaces of the at least one protrusion (the upper surface and the side surfaces of 5 and 10 are covered by 8 and 12, respectively).
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Colinge to obtain and achieve the semiconductor device comprising: the graphene layers covering an upper surface and side surfaces of the at least one protrusion as claimed, because covering the protrusion-type conductive portions with graphene enhances device performance by increasing the effective contact area, improving both thermal and electrical conduction, and stabilizing the interface [0021, 0025].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination with Colinge due to above reason.
Regarding claim 2, Colinge in view of Chen teaches the semiconductor device of claim 1, wherein the graphene layers are on the part of the sheet member and an upper portion of the at least one protrusion through a horizontal junction along the one plane and a vertical junction in the one direction perpendicular to the one plane (Colinge: G210 is formed as multilayer graphene, and covers the upper portion of 2D210S and the upper portion of 2D210P through horizontal and vertical junctions, FIG. 6, [0064-0065])
Regarding claim 3, Colinge in view of Chen teaches the semiconductor device of claim 1, wherein
the 2D material layer comprises a first region and second regions (Colinge: 2D210 comprises a first region and the left/right side of second regions, see the annotated FIG. 6; hereinafter ‘FR’, ‘LSR’, and ‘RSR’),
the first region corresponds to the gate electrode (FR under 214), and
the second regions correspond to the source electrode and the drain electrode (LSR under 216S and RSR under 216D),
the at least one protrusion is in the second regions (2D210P is in LSR and RSR), and
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the graphene layers are in the second regions between the source electrode and the 2D material layer and between the drain electrode and the 2D material layer (G210 in LSR between 216S and 2D210 in RSR and G210 in RSR between 216D and 2D210 in LSR).
Regarding claim 4, Colinge in view of Chen teaches the semiconductor device of claim 3, wherein a thickness of the sheet member in the first region and a thickness of the sheet member in the second regions are equal to each other (Colinge: 2D210S is a single continuous layer having uniform thickness across FR, LSR, and RSR, as it is formed by CVD/epitaxial/ALD, [0064-0065])
Regarding claim 8, Colinge in view of Chen teaches the semiconductor device of claim 1, wherein the 2D semiconductor material comprises a material having a bandgap greater than or equal to about 0.5 eV and less than or equal to about 3.0 eV (Colinge: 2D210 comprises MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, HfS2, HfSe2, MoS2, [0038]).
Although, Colinge does not explicitly teach that the bandgap range of the 2D material layer, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Colinge to include the semiconductor device wherein the 2D semiconductor material comprises a material having a bandgap greater than or equal to about 0.5 eV and less than or equal to about 3.0 eV as claimed, because MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, HfS2, HfSe2, MoS2 are well known in the art to have a bandgap between 0.5 eV and 3.0 eV. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 9, Colinge in view of Chen teaches the semiconductor device of claim 1, wherein the 2D semiconductor material comprises transition metal dichalcogenide (Colinge: TMD) or black phosphorus (2D210 comprises TMD or black phosphorus, [0038]).
Regarding claim 13, Colinge in view of Chen teaches an electronic device (high-performance low-power device, [0041]) comprising: a semiconductor device (200, FIG. 6, [0071-0072]), comprising:
a two-dimensional (2D) material layer (the lower portion of multilayer sheet 210, as 210 is described as being formed by CVD/ALD/epitaxial processes, and thus reasonably interpreted as a multilayer 2D composite in which the lower monolayer set corresponds to the 2D material layer, [0064-0065]; hereinafter ‘2D210’) including a 2D semiconductor material (210 including graphene, phosphorene, TMDs) having a polycrystalline structure (annealing increases the domain size and reduces defects),
the 2D material layer (2D210) including a sheet member (a portion of 2D210 extending laterally along the upper surface of 206, wherein the portion corresponds to the lower monolayer set positioned along the lateral region, FIG. 5; hereinafter ‘2D210S’) and at least one protrusion (a portion of 2D210 rising along the adjacent 208, wherein the portion corresponds to the same lower monolayer set positioned along the vertical region of the fin gate structure; hereinafter ‘2D210P’), the sheet member (2D210S) extending along one plane (x-direction) and the at least one protrusion (2D210P) extending in one direction perpendicular to the one plane (y-direction);
a source electrode (216S) and a drain electrode (216D) spaced apart from each other on the 2D material layer (shown in FIG. 6);
a gate insulating layer (212) and a gate electrode (214) on the 2D material layer (2D210) between the source electrode (216S) and the drain electrode (216D); and
graphene layers (the upper portion of the same multilayer sheet 210 positioned above 2D210, the upper monolayer set within 210; hereinafter ‘G210’) on both sides of the gate insulating layer (212), the graphene layers (G210) covering a part of the sheet member (the upper surface of 2D210S).
Colinge does not teach the electronic device comprising: the graphene layers covering an upper surface and side surfaces of the at least one protrusion.
Chen teaches an electronic device (FIG. 2, [0018]) comprising: the graphene layers (8 and 12, [0021-0023]) covering an upper surface and side surfaces of the at least one protrusion (the upper surface and the side surfaces of 5 and 10 are covered by 8 and 12, respectively).
As taught by Chen, one of ordinary skill in the art would utilize and modify the above teaching into Colinge to obtain and achieve the electronic device comprising: the graphene layers covering an upper surface and side surfaces of the at least one protrusion as claimed, because covering the protrusion-type conductive portions with graphene enhances device performance by increasing the effective contact area, improving both thermal and electrical conduction, and stabilizing the interface [0021, 0025].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination with Colinge due to above reason.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Colinge (US 2019/0103496) in view of Chen (US 2018/0247584), and further in view of Ahn (KR 2012/0136118).
Regarding claim 5, Colinge in view of Chen teaches the semiconductor device of claim 3, but does not teach the semiconductor device wherein a thickness of the sheet member in the second regions exceeds a thickness of the sheet member in the first region.
Ahn teaches a semiconductor device (FIG. 5, [0020]) wherein a thickness of the sheet member in the second regions exceeds a thickness of the sheet member in the first region (the thickness of 110 under 141 and 142 is greater than that under 151, [0029, 0004])
As taught by Ahn, one of ordinary skill in the art would utilize and modify the above teaching into Colinge in view of Chen to obtain and achieve the semiconductor device wherein a thickness of the sheet member in the second regions exceeds a thickness of the sheet member in the first region as claimed, because the thinner channel region ensures semiconducting behavior for switching, while the thicker source/drain regions provide metallic characteristics to reduce contact resistance [0025-0026].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ahn in combination with Colinge in view of Chen due to above reason.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Colinge (US 2019/0103496) in view of Chen (US 2018/0247584), and further in view of Lee et al. (US 2020/0388680; hereinafter ‘Lee’).
Regarding claim 6, Colinge in view of Chen teaches the semiconductor device of claim 1, wherein
the 2D material layer comprises a first region and second regions (Colinge: 2D210 comprises a first region and the left/right side of second regions, see the annotated FIG. 6; hereinafter ‘FR’, ‘LMSR’, and ‘RMSR’),
the first region corresponds to the gate electrode (FR corresponds to 214), and
the second regions correspond to a region between the source electrode and the gate electrode (LMSR correspond to the region between 216S and 214) and a region between the drain electrode and the gate electrode (RMSR correspond to the region between 216D and 214),
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the at least one protrusion is in the second regions (2D210P is in LMSR and RMSR).
Although, Colinge does not explicitly teach the semiconductor device further comprising: spacers, wherein the graphene layers are between the 2D material layer and the spacers in the second regions, and the spacers are between the source electrode and the gate electrode and between the drain electrode and the gate electrode in the second regions.
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Colinge, however, recognizes that the semiconductor device further comprising: spacers (1208, FIG. 12A-12B, [0089]), wherein the graphene layers (the outer portion of 810 is the graphene, since 810 is a multilayer graphene formed by CVD, epitaxial growth, ALD, CVD, PEVCD, MBE, [0080], see the annotated FIG. 9A and 9B; hereinafter referred to as ‘G810’) are between the 2D material layer and the spacers in the second regions (G810 are between 2D810 and 1208, see the annotate FIG. 13A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Colinge to include the semiconductor device further comprising: spacers, wherein the graphene layers are between the 2D material layer and the spacers in the second region as claimed, because an additional insulating layer provides as extra insulation, covering both lateral and top surfaces, thereby improving device reliability and field control. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Colinge in view of Chen does not teach the semiconductor device further comprising: the spacers are between the source electrode and the gate electrode and between the drain electrode and the gate electrode in the second regions.
Lee teaches a semiconductor device (100, FIG. 5, [0061]) further comprising: the spacers (110, [0055]) are between the source electrode and the gate electrode and between the drain electrode and the gate electrode in the second regions (the left side 110 between 106 and 109 and the right side 110 between 107 and 109 in the region between 109 and 106/107, [0055]).
As taught by Lee, one of ordinary skill in the art would utilize and modify the above teaching into Colinge in view of Chen to obtain and achieve the semiconductor device further comprising: the spacers are between the source electrode and the gate electrode and between the drain electrode and the gate electrode in the second regions as claimed, because it functions as an additional insulating structure surrounding the gate stack, preventing electrical shorting and metal diffusion from the source/drain electrodes, and thereby enhancing overall device robustness.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lee in combination with Colinge in view of Chen due to above reason.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Colinge (US 2019/0103496) in view of Chen (US 2018/0247584) and Lee (US 2020/0388680), and further in view of Byun et al. (US 2014/0158989; hereinafter ‘Byun’).
Regarding claim 7, Colinge in view of Chen and Lee teaches the semiconductor device of claim 6, but does not teach the semiconductor device wherein the graphene layers extend under the source electrode and the drain electrode.
Byun teaches a semiconductor device (400’, FIG. 13B, [0137]) wherein the graphene layers extend under the source electrode and the drain electrode (431 and 432 extend under451 and 452, [0126-0127]).
As taught by Byun, one of ordinary skill in the art would utilize and modify the above teaching into Colinge in view of Chen and Lee to obtain and achieve the semiconductor device wherein the graphene layers extend under the source electrode and the drain electrode as claimed, because the graphene layers are intended to provide a continuous path and to ensure sufficient overlap with the source/drain electrodes to form low resistance ohmic contacts [0076].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Byun in combination with Colinge in view of Chen and Lee due to above reason.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Colinge (US 2019/0103496) in view of Chen (US 2018/0247584), and further in view of Jung et al. (US 2020/0039827; hereinafter ‘Jung’).
Regarding claim 10, Colinge in view of Chen teaches the semiconductor device of claim 1, wherein the graphene layers comprise graphene (Colinge: G210 comprise graphene, [0064]).
Colinge in view of Chen does not teach the semiconductor device, wherein the graphene has a crystal size of about 0.5 nm or more and about 500 nm or less.
Jung teaches a semiconductor device (S, FIG. 1, [0037, 0069]), wherein the graphene has a crystal size of about 0.5 nm or more and about 500 nm or less (40 includes crystals of a size in a rage of about 0.5 nm to about 70 nm, [0015]).
As taught by Jung, one of ordinary skill in the art would utilize and modify the above teaching into Colinge in view of Chen to obtain and achieve the semiconductor device, wherein the graphene has a crystal size of about 0.5 nm or more and about 500 nm or less as claimed, because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Jung in combination with Colinge in view of Chen due to above reason.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Colinge (US 2019/0103496) in view of Chen (US 2018/0247584), and further in view of Song et al. (US 2019/0161351; hereinafter ‘Song’).
Regarding claim 11, Colinge in view of Chen teaches the semiconductor device of claim 1, wherein the graphene layers comprise graphene (Colinge: G210 comprise graphene, [0064]).
Colinge in view of Chen does not teach the semiconductor device, wherein the graphene has a ratio of carbons having a sp2 combination structure with respect to all carbons of about 50% or more and about 99% or less.
Song teaches a semiconductor device (770, FIG. 7C, [0154]), wherein the graphene has a ratio of carbons having a sp2 combination structure with respect to all carbons of about 50% or more and about 99% or less (750a and 750b has a ratio of carbons having a sp2 combination structure to total carbon within a range of about 50% to about 99%, [0006]).
As taught by Song, one of ordinary skill in the art would utilize and modify the above teaching into Colinge in view of Chen to obtain and achieve the semiconductor device, wherein the graphene has a ratio of carbons having a sp2 combination structure with respect to all carbons of about 50% or more and about 99% or less as claimed, because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Song in combination with Colinge in view of Chen due to above reason.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Colinge (US 2019/0103496) in view of Chen (US 2018/0247584), and further in view of Son et al. (US 2015/0093648; hereinafter ‘Son’).
Regarding claim 12, Colinge in view of Chen teaches the semiconductor device of claim 1, wherein, in a mixing region where the 2D material layer and the graphene layers coexist in the one direction (Colinge: a mixing region between 2D210 and G210 coexist along the stacking direction, since interfacial regions between 2D210 and G210 naturally occur and intermingle during layer growth and stacking, [0065]).
Colinge in view of Chen does not teach the semiconductor device, wherein a content of graphene in the graphene layers is about 20 vol % or more and about 80 vol % or less.
Son teaches a semiconductor device ([0154]), wherein a content of graphene in the graphene layers is about 20 vol % or more and about 80 vol % or less (a contents of graphene in the composite is about 0.001 part to about 90 part by weight, [0098]).
Although, Son does not explicitly teach the graphene content in the range of 20 to 80 vol.%. it is a matter of routine calculation in the field to convert between wt.% and vol.% when material densities are known. The density of graphene (~2.2g/cm3) and silicon-based materials (~2.3g/ cm3) are closely matched, a 20 to 80 vol.% graphene content would inherently correspond to approximately 20 to 80 wt.%.
As taught by Son, one of ordinary skill in the art would utilize and modify the above teaching into Colinge in view of Chen to obtain and achieve the semiconductor device, wherein a content of graphene in the graphene layers is about 20 vol % or more and about 80 vol % or less as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Son in combination with Colinge in view of Chen due to above reason.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 12/4/25
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