DETAILED ACTION
This action is responsive to the following communication: the response filed 4/15/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 6-16 pending, 1-5 and 17-20 withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6, 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2017/0110177 “Lee”).
Regarding claim 6, Lee discloses a memory device comprising:
a memory bank (480a; fig. 4) including a plurality of memory blocks (“a memory bank including a plurality of memory blocks” para 0009) that includes a plurality of memory cells (“each bank having a plurality of memory cells arranged in rows and columns” para 0027); and
a control logic (410; fig. 4) configured to control a data input/output operation (para 0069) for the plurality of memory cells,
wherein the control logic (410) is configured to:
measure a refresh count (a counting in which a refresh operation is performed; fig. 6) that is calculated based on a first count (count value(s) CNTa-CNTh as counted by counter block 140; fig. 5) and a second count (burst count value as counted by burst counter BRSC 510; fig. 7); and
perform a refresh operation (i.e. performed during t1-t3 according to self-refresh entry command SRE; fig. 6) for a memory block (any selected memory block) from among the plurality of memory blocks, based on the refresh count (i.e. based on the counting),
wherein the first count (i.e. count value(s) CNTa-CNTh) is determined based on an access history (the count value is determined according to an access history indicating when a refresh operation is completed and an interval of the refresh operation; fig. 6 para 0076) of the memory block,
wherein the second count (i.e. the burst count) is determined based on a characteristic (a time point when mode signal MOD is activated for refresh; para 0099) of the plurality of memory cells, and is not determined based on the access history of the memory cells (i.e. the burst count is increased at the time point when MOD is activated, and not based on refresh completion or any respective intervals of the refresh operation),
wherein the characteristic (i.e. time point of MOD activation) of the plurality of memory cells is independent (i.e. independent event or occurrence) from the access history (i.e. completion and interval of the refresh operation) of the memory block (i.e. the time point in which MOD is activated is not dependent on the completion and respective intervals of the refresh operation).
Regarding claim 15, Lee discloses the memory device, wherein the memory block includes a group of memory rows identified by a sense amplifiers (485; fig. 4 para 0060-0061).
Regarding claim 16, Lee discloses the memory device, wherein the memory block includes a group of memory rows identified by a plurality of sense amplifiers (“the sense amplifier unit 485 may include a plurality of bank sense amplifiers 485a˜485h respectively coupled to the bank arrays 480a˜480h” para 0061).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2017/0110177 “Lee”) in view of Haehn et al. (US 2007/0157056 ‒hereinafter Haehn).
Regarding claim 7, Lee discloses the memory device, the first count (i.e. count value(s) CNTa-CNTh), the second count (i.e. burst count value), and leakage current of the plurality of memory cells (para 0006).
Lee does not expressly disclose a dynamic leakage current and a static leakage current.
Haehn discloses a dynamic leakage current and a static leakage current (measuring a parameter comprising a dynamic leakage current and a static leakage current; claim 3).
Since Lee and Haehn are both from the same field of endeavor (i.e. measuring operating parameters), and the purpose disclosed by Haehn would have been recognized as pertinent to Jung. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to modify Jung as taught by Haehn for the purpose of improving operational parameters including measuring a dynamic leakage current and a static leakage current (para 0038-0039 of Haehn), which is common and well known in the art to secure integrity of data storage in an integrated circuit.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2017/0110177 “Lee”) in view of Jung et al. (US 2013/0304982 ‒hereinafter Jung).
Regarding claim 8, Lee does not expressly disclose the memory device, wherein the control logic is configured to apply different weights to the first count and the second count.
Jung discloses the memory device, wherein the control logic is configured to apply different weights to the first count and the second count (the access history is more significant, i.e. considered to have more weight, in measuring the refresh count than the second count based on the refresh characteristic; fig. 3, 7, further para 0117-0018).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is modifiable as taught by Jung for the purpose of facilitating data accessing schemes by preventing data loss by managing refreshing operations (para 0063 of Jung), which is common and well known in the art to secure integrity of data storage.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2017/0110177 “Lee”) in view of Suwa et al. (US 2003/0214344 ‒hereinafter Suwa).
Regarding claim 9, Lee discloses the memory device, wherein the control logic includes:
a block decoder (decoder 460 functions to decode an address to select the memory block of the memory bank; fig. 4) configured to output a block signal (any control signal, including address for selecting the memory block; para 0064) for selecting the memory block based on an active request (CMD; fig. 4) and a row address (Addr; fig. 4) received from a controller (200; fig. 3);
a count manager (100; fig. 5) configured to output a count signal (RDONh-RDONa; fig. 5) for the memory block, based on the active request (i.e. Command); the block signal (i.e. the control signal);
a refresh counter (counter block 140 functions to store a count value corresponding to refresh; fig. 5) configured to store the refresh count (the counting for performing refresh) corresponding to the memory block and increasing by one depending on the count signal (para 0077); and
a refresh manager (160; fig. 5) configured to output a refresh signal (para 0079-0081) based on the refresh count (the counting for performing refresh) such that the refresh operation is performed for the memory block (fig. 6).
Lee does not expressly disclose an oscillator configured to generate an oscillation signal pulsing with a specified period, and output a signal based on the oscillation signal.
Suwa discloses a block decoder (data line decoder functions to decode signals to designate a block; para 0212-0213) configured to output a block signal (BS/ZBS; fig. 19) for selecting the memory block (i.e. upper/lower block; para 0213); an oscillator (31a; fig. 11, 12) configured to generate an oscillation signal (PHY; fig. 12) pulsing (i.e. of the waveform; para 0183) with a specified period (i.e. oscillation cycle), and output a signal (para 0173) based on the oscillation signal (PHY).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is modifiable as taught by Suwa for the purpose of facilitating data accessing schemes by enabling changes in a refresh cycle without changing circuit configuration, which facilitates memory chip assembly having large storage capacity (para 0229 of Suwa).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2017/0110177 ‒hereinafter Lee) in view of Suwa et al. (US 2003/0214344 ‒hereinafter Suwa), and further in view of Jung et al. (US 2013/0304982 ‒hereinafter Jung).
Regarding claim 13, Lee as modified does not expressly disclose the memory device, wherein the refresh manager is configured to: receive count status information corresponding to the memory block from the refresh counter; and output the refresh signal for the memory block when the refresh count reaches a refresh reference value.
Jung discloses receive count status information (i.e. from comparator 222; fig. 2) corresponding to the memory block from the refresh counter (223; fig. 2) (para 0081); and output the refresh signal (i.e. via refresh command generator 254; fig. 2 para 0091) for the memory block when the refresh count reaches a refresh reference value (i.e. a threshold S43; fig. 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Jung for the purpose of facilitating data accessing schemes by preventing data loss by managing refreshing operations (para 0063 of Jung), which is common and well known in the art to secure integrity of data storage.
Regarding claim 14, Jung discloses the memory device, wherein the refresh manager is configured to send a reset signal for initializing the refresh count (para 0097) to the refresh counter (223; fig. 2) in which the refresh count reaches a refresh reference value (i.e. a threshold S43; fig. 5).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Lee is further modifiable as taught by Jung for the purpose of facilitating data accessing schemes by preventing data loss by managing refreshing operations (para 0063 of Jung), which is common and well known in the art to secure integrity of data storage.
Allowable Subject Matter
Claim(s) 10-12 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 10, the prior art fails to teach or suggest the claimed limitations, namely an AND gate configured to output a block count signal by performing an AND operation on the active request and the block signal; and an OR gate configured to output the count signal by performing an OR operation on the block count signal and the oscillation signal.
With respect to dependent claim 11, the prior art fails to teach or suggest the claimed limitations, namely an AND gate configured to output a block count signal by performing an AND operation on the active request and the block signal; a frequency divider configured to receive the block count signal and configured to output a weighted block count signal by changing a frequency of the block count signal based on a specified weight; and an OR gate configured to output the count signal by performing an OR operation on the weighted block count signal and the oscillation signal.
With respect to dependent claim 12, the prior art fails to teach or suggest the claimed limitations, namely an AND gate configured to output a block count signal by performing an AND operation on the active request and the block signal; a D-flip-flop configured to output a weighted oscillation signal by decreasing a frequency of the oscillation signal; and an OR gate configured to output the count signal by performing an OR operation on the block count signal and the weighted oscillation signal.
The allowable claims are supported in at least fig. 4-6 of the instant application.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/UYEN SMET/
Primary Examiner, Art Unit 2824
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