DETAILED ACTION
Claims 1-20 are presented for examination
This office action is in response to submission of application on 18-JANURARY-2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 16-APRIL-2026 in response to the non-final office action mailed 23-OCTOBER-2025 has been entered. Claims 1-20 remain pending in the application.
With regards to the 103 rejections, the applicant’s amendments to the claims have not overcome the rejections to claims 1-20 as the former prior art sufficiently teaches the newly added limitations of the amended claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the partial sum" in line 9. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 11-13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over AYDONAT (E.P. Pub. No. EP 3153996 A2) in view of HUANG (U.S. Pub. No. US 20180173571 A1) in view of SONG (U.S. Pub. No. US 20180173571 A1)
Regarding claim 1, AYDONAT teaches the claim invention including:
An accelerator circuit for use in a convolutional layer of a convolutional neural network, comprising a plurality of sub processing-element (PE) arrays, wherein each of the plurality of sub PE arrays comprises a plurality of processing elements, ([0043] Figure 9 is a block diagram of an exemplary CNN accelerator 900 that may be used to implement a CNN according to an embodiment of the present invention. The CNN accelerator 900 allows for efficient computation of forward propagation of convolution and other layers.
[0044] The CNN accelerator 900 accepts an input image (feature map) and may apply multiple convolution and other layers in succession.
[0045] Input image pixels are transmitted into the processing element (PE) arrays 901-904 which may perform independent dot-product operations in a convolution procedure. PE array 901 represents a first PE array and PE array 904 represents an nth PE array, where n can be scaled to any number.) wherein the processing elements in each of the plurality sub PE arrays implement a standard convolutional layer during a first configuration applied to the accelerator circuit, ([0009] According to an embodiment of the present invention, a CNN accelerator implemented on a target includes a sequencer unit that coordinates a first data flow between components on the target during a first configuration and that coordinates a second data flow between components on the target during a second configuration. The CNN accelerator also includes a plurality of processing elements that implement a standard convolutional layer during the first configuration) a first accumulator; (The accumulator unit 1030 accumulates dot product results as partial sums until an entire computation is completed. The accumulator unit 1030 may be implemented using a logic array block. )
While AYDONAT does teach an accelerator circuit that implements PE arrays, it does not explicitly teach:
and implement a depth-wise convolutional layer during a second configuration applied to the accelerator circuit.
However, in analogous art that similarly implements a CNN, HUANG teaches:
and implement a depth-wise convolutional layer during a second configuration applied to the accelerator circuit. ([0140] In some cases, the same configurations can be adapted for a depthwise convolution layer. Alternatively, a variation of configuration may be used for the depthwise convolution layer. )
It would have been obvious to a person skilled in the art before the effective filing date of the
invention to have combined with HUANG‘s depth-wise CNN and, with AYDONAT‘s CNN accelerator circuit, with a reasonable expectation of success, a depth-wise CNN, as in HUANG, where the CNN is implemented by an accelerator circuit, as found in AYDONAT. A person of ordinary skill would have been motivated to lower power consumption (HUANG [0003]).
AYDONAT further teaches:
… the first partial sum generated by each sub PE array… ([0131] The 128 multipliers may be configured to perform multiplication in parallel and each of the plurality of accumulators 1103 may sum the outputs of four multipliers and accumulate the partial sum results for one or more cycles. Then the accumulated partial results may further be summed and accumulated by one or more accumulators to yield a final output of a convolution layer.)
While AYDONAT, as modified by HUANG, does teach generating activation data based on a configuration and routing the data to PE arrays, it does not explicitly teach:
a demultiplexer, configured to output the first partial sum generated by each sub PE array to the first accumulator to calculate an accumulation result in response to a control signal being in a low logic state, and to output a concatenated partial sum obtained from the first partial sum generated by each sub PE array in response to the control signal being in a high logic state;
However, in analogous art that similarly teaches using accelerator circuits, SONG teaches:
a demultiplexer, configured to output the first partial sum generated by each sub PE array to the first accumulator to calculate an accumulation result in response to a control signal being in a low logic state, ([0061] The first demultiplexer DEMUX0 of the data output selection circuit 220 may transmit the first multiplication result data DWV1.1 to the first accumulator ACC0 through the first output line 261 of the first demultiplexer DEMUX0 in response to the flag signal FLAG having a logic “low(L)” level. ) and to output a concatenated partial sum obtained from the first partial sum generated by each sub PE array in response to the control signal being in a high logic state; ([0030] In contrast, the flag signal FLAG having a logic “high” level may be transmitted to the data selection output circuit 123 to perform the EWM arithmetic operation. In such a case, the data selection output circuit 123 may output the replica constant data DC<127:0>, which are inputted to the first input terminal IN1, through the output terminal OUT of the data selection output circuit 123. In an embodiment, the data selection output circuit 123 may be realized using a 2-to-1 multiplexer.)
It would have been obvious to a person skilled in the art before the effective filing date of the
invention to have combined with SONG‘s demultiplexer and multiplexer and, with AYDONAT‘s, as modified by HUANG, CNN accelerator circuit and PE arrays, with a reasonable expectation of success, a demultiplexer and multiplexer, as in song, which is applied to a CNN accelerator circuit and PE array data, as found in AYDONAT, as modified by HUANG. A person of ordinary skill would have been motivated to increase data processing speed (SONG [0004]).
Regarding claim 19, it comprises of limitations similar to those of claim 1 and is therefore rejected for similar rationale.
Regarding claim 2, HUANG further teaches:
The accelerator circuit of Claim 1, further comprising: a memory, configured to store weights for the standard convolutional layer or the depth-wise convolutional layer in response to the first configuration or the second configuration being applied; ([0093] At step 407, the input data, various CNN model parameters and associated data may be transmitted from the main memory to a random-access-memory (RAM) on the chip…. The system can also choose to have eight slices for storing the CNN weights, each having approximately 150B, and four slices for storing the CNN biases.) an activation circuit, configured to generate activation data for each sub PE array according to a first partial sum generated by each sub PE array; ([0050] In some embodiments, a convolution layer and/or fully-connected layer may be followed by an activation layer, such as a rectified linear unit (ReLU). The ReLU layer may apply an elementwise activation function, such as the max(0,x) thresholding at zero. [0131] The 128 multipliers may be configured to perform multiplication in parallel and each of the plurality of accumulators 1103 may sum the outputs of four multipliers and accumulate the partial sum results for one or more cycles. Then the accumulated partial results may further be summed and accumulated by one or more accumulators to yield a final output of a convolution layer.)
AYDONAT further teaches:
a router, configured to distribute the activation data to each sub PE array; (The device 1700 may include routing resources such as LAB local interconnect lines, row interconnect lines ("H-type wires"), and column interconnect lines ("V-type wires") (not shown) to route signals between components on the target device. )
SONG further teaches:
and a multiplexer, configured to receive the accumulation result and the concatenated partial sum, and to respectively output the accumulation result and the concatenated partial sum to the activation circuit in response to the control signal being in the low logic state and the high logic state. ([0038] In each of the demultiplexers DEMUX0˜DEMUX7, selection of the output line through which the multiplication result data are outputted may be determined by the flag signal FLAG that is inputted to the data output selection circuit 220. For example, when the flag signal FLAG having a logic “low” level is inputted to the data output selection circuit 220, the demultiplexers DEFAUX0˜DEMUX7 may output the first to eighth multiplication result data DM_0˜DM_7, which are outputted from the multiplication circuit 210, through the first output lines 261 of the demultiplexers DEMUX0˜DEMUX7. In contrast, when the flag signal FLAG having a logic “high” level is inputted to the data output selection circuit 220, the demultiplexers DEMUX0˜DEMUX7 may output the first to eighth multiplication result data DM_0˜DM_7, which are outputted from the multiplication circuit 210, through the second output lines 262 of the demultiplexers DEMUX0˜DENIUX7.)
SONG further teaches:
The accelerator circuit of Claim 2, wherein in response to the first configuration being applied, the control signal is switched to the low logic state, wherein in response to the second configuration being applied, the control signal is switched to the high logic state. ([0070] When the MAC command MAC_CMD is transmitted to the command decoder 510, the command decoder 510 may decode the MAC command MAC_CMD to generate various MAC control signals (e.g., a MAC read control signal MAC_RD, the first latch control signal LATCH1 having a logic “high(H)” level, the second latch control signal LATCH2 having a logic “high(H)” level, the third latch control signal LATCH3 having a logic “low(L)” level, the fourth latch control signal LATCH4 having a logic “low(L)” level, the flag signal FLAG having a logic “low(L)” level, and the MAC result data output control signal MAC_RD_RST) which are described with reference to FIG. 7. The MAC read control signal MAC_RD may be transmitted to the first memory bank 521 and the second memory bank 522. The first memory bank 521 and the second memory bank 522 may output the weight data DW and the vector data DV in response to the MAC read control signal MAC_RD, respectively. If the MAC arithmetic operation of the MAC circuit 10 terminates, the MAC result data output control signal MAC_RD_RST for controlling an output operation of the MAC result data may be transmitted from the command decoder 510 to the MAC circuit 10. The MAC arithmetic operation performed by the MAC circuit 10 based on the MAC control signals may be the same as the MAC arithmetic operation described with reference to FIG. 7.
[0071] When the EWM command EWM_CMD is transmitted to the command decoder 510, the command decoder 510 may decode the EWM command EWM_CMD to generate various EWM control signals (e.g., an EWM read control signal EWM_RD, the first latch control signal LATCH1 having a logic “low(L)” level, the second latch control signal LATCH2 having a logic “low(L)” level, the third latch control signal LATCH3 having a logic “high(H)” level, the fourth latch control signal LATCH4 having a logic “high(H)” level, the flag signal FLAG having a logic “high(H)” level, and the EWM result data output control signal EWM_RD_RST) which are described with reference to FIG. 8. In similar fashion as illustrated in FIG. 12, the EWM read control signal EWM_RD may be transmitted to the first memory bank 521 and the global buffer 530. The first memory bank 521 and the global buffer 530 may output the weight data DW and the constant data DC in response to the EWM read control signal EWM_RD, respectively. If the EWM arithmetic operation of the MAC circuit 10 terminates, the EWM result data output control signal EWM_RD_RST for controlling an output operation of the EWM result data may be transmitted from the command decoder 510 to the MAC circuit 10. The EWM arithmetic operation performed by the MAC circuit 10 based on the EWM control signals may be the same as the EWM arithmetic operation described with reference to FIG. 8.)
HUANG further teaches:
The accelerator circuit of Claim 2, wherein the activation circuit further comprises functions of pooling, batch normalization, quantization, or a combination thereof. ([0053] The computing architecture may be a pre-trained convolutional neural network. A CNN model may comprise one or more convolution layers. A CNN model may comprise from one to several hundred convolution layers. A CNN model may comprise one or more pooling layers. In some cases, the pooling layer may immediately follow a convolution layer. In some embodiments, ReLU activation operations are combined with convolution operations such that convolution results are processed by activation functions immediately.)
Regarding claims 12-13, they comprise of limitations similar to those of claims 2-4 and are therefore rejected for similar rationale.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over AYDONAT (E.P. Pub. No. EP 3153996 A2), HUANG (U.S. Pub. No. US 20180173571 A1), SONG (U.S. Pub. No. US 20180173571 A1) in further view of DALLY (U.S. Pub. No. US 20180046900 A1)
While AYDONAT, as modified by HUANG and SONG, does teach claim 2, which claim 5 is dependent upon, it does not explicitly teach:
The accelerator circuit of Claim 2, wherein the processing elements in each sub PE array are arranged in a two-dimensional systolic array, and each sub PE array further comprises: an activation buffer, configured to store the distributed input activate data; a weight buffer, configured to store the weight for the standard convolutional layer or the depth-wise convolutional layer; and a second accumulator, configured to accumulate output partial sums from a bottom row of the processing elements of each sub PE array to generate the first partial sum of each sub PE array.
However, in analogous art that similarly implements a accelerator circuit, DALLY teaches:
The accelerator circuit of Claim 2, wherein the processing elements in each sub PE array are arranged in a two-dimensional systolic array, and each sub PE array further comprises: an activation buffer, configured to store the distributed input activate data; a weight buffer, configured to store the weight for the standard convolutional layer or the depth-wise convolutional layer; ([0060] The PTIS-dense dataflow relies on input buffers, weight buffer 230 and input activations buffer 235, for storing weights and input activations, respectively. An accumulator buffer 250 stores the partial sums of the output activations.) and a second accumulator, configured to accumulate output partial sums from a bottom row of the processing elements of each sub PE array to generate the first partial sum of each sub PE array. ([0076] To accommodate the accumulation of sparse partial sums, the monolithic K.sub.c×W.sub.t×H.sub.t accumulation buffer 250 used in the PTIS-dense dataflow is modified to be a distributed array of smaller accumulation buffers accessed via a scatter network which can be implemented as a crossbar switch, such as the F×I arbitrated crossbar 335. The F×I arbitrated crossbar 335 routes F×I products to an array of A accumulator units based on the output positions associated with each product. The positions may be translated to form an address. A particular product is transmitted to the one accumulator unit in the accumulator array 340 that is configured to compute the output activation for the position associated with the product. Taken together, a scatter accumulator array comprising the F×I arbitrated crossbar 335 and accumulator array 340 is associated with a K.sub.c×W.sub.t×H.sub.t address range. The address space is distributed across the A accumulator units and each accumulator unit includes a bank of addressable storage and an adder to accumulate a partial sum (when processing of a tile is complete, the partial sum is an output activation) for the output position.)
It would have been obvious to a person skilled in the art before the effective filing date of the
invention to have combined with DALLY‘s weight buffer and calculation and, with AYDONAT‘s, as modified by HUANG and SONG, CNN accelerator circuit and PE arrays, with a reasonable expectation of success, a weight buffer and calculation, as in DALLY, which is applied to a CNN accelerator circuit and PE array data, as found in AYDONAT, as modified by HUANG and SONG. A person of ordinary skill would have been motivated to lower energy consumption (DALLY [0005]).
Regarding claim 14, it comprises of limitations similar to those of claim 5 and is therefore rejected for similar rationale.
Claims 6, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over AYDONAT (E.P. Pub. No. EP 3153996 A2), HUANG (U.S. Pub. No. US 20180173571 A1), SONG (U.S. Pub. No. US 20180173571 A1) in further view of YOON (U.S. Pub. No. US 20230015148 A1)
While AYDONAT, as modified by HUANG and SONG, does teach claim 3 which claim 6 is dependent upon, it does not explicitly teach:
The accelerator circuit of Claim 3, wherein the weights for the standard convolutional layer is preloaded into the processing elements in each sub PE array in response to the first configuration being applied,
However, in analogous art that similarly applied an accelerator, YOON teaches:
The accelerator circuit of Claim 3, wherein the weights for the standard convolutional layer is preloaded into the processing elements in each sub PE array in response to the first configuration being applied, and the activation data for the depth-wise convolutional layer is preloaded into the processing elements in each sub PE array in response to the second configuration being applied. ([0007] The first flip/flop may be configured to latch a first number and to output the first number and a multiple number based on the first number. The second flip/flop may be configured to load a second number and to output the second number. [0053] The flip/flops 610 and 612 may preload and latch scalar values in the matrix A. In particular, the flip/flop 610 may be used for preloading a scalar value, a, of the matrix A and may pass this value to the flip/flop 612. The flip/flop 612 may be used for loading and latching the scalar value, a, and reusing this value several times in computations until it is reloaded. Flip/flops 614 and 616 may preload and latch hard multiple(s) of the scalar values in matrix A. In particular, the flip/flop 614 may be used for preloading pre-computed hard multiple(s) of the scalar value, a, of the matrix A and may pass these values to the flip/flop 616. (as seen here, YOON teaches the preloading of data into a data structure based on a configuration. One skilled in the art could use the method of preloading data as taught by YOON to preload the activations and weights of the other arts into the PE arrays.))
It would have been obvious to a person skilled in the art before the effective filing date of the
invention to have combined with YOON‘s preloading of data based on configuration and, with AYDONAT‘s, as modified by HUANG, and SONG, activation data, weights, and PE array, with a reasonable expectation of success, preloading data, as in YOON, where the data is weights and activation data being directed to a PE array, as found in AYDONAT, as modified by HUANG, and SONG. A person of ordinary skill would have been motivated to improve efficiency. (YOON [0001]).
Regarding claims 15 and 20, they comprise of limitations similar to those of claim 6 and are therefore rejected for similar rationale.
Claims 7-8, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over AYDONAT (E.P. Pub. No. EP 3153996 A2), HUANG (U.S. Pub. No. US 20180173571 A1), SONG (U.S. Pub. No. US 20180173571 A1), YOON (U.S. Pub. No. US 20230015148 A1), in further view of DALLY (U.S. Pub. No. US 20180046900 A1 )
Regarding claim 7, YOON further teaches:
The accelerator circuit of Claim 6, wherein, for each sub PE array during the first configuration, when a specific row of the processing elements is not the bottom row, ([0054] An intermediate result, which may be the partial sum output by the adder 630 in a MAC unit that is not in the bottom row of the systolic array)
While AYDONAT, as modified by HUANG, SONG, and YOON, does teach data that is not from the bottom row, it does not explicitly teach:
each processing element of the specific row receives an output partial sum from each processing element in a previous row of the processing elements, performs a multiply-accumulate operation by multiplying the activation data with the preloaded weight to generate a multiplication product adds the multiplication product to the received output partial sum from each processing element in the previous row to generate the output partial sum of each processing element in the specific row, and transmits the output partial sum to each processing element in a next row.
However, in analogous art that similarly implements accelerator circuits, DALLY teaches:
each processing element of the specific row receives an output partial sum from each processing element in a previous row of the processing elements, ([0048] The layer sequencer 215 reads the weights and outputs weight vectors to be multiplied by the PEs 210. In one embodiment, the weights are in compact form and are read from off-chip DRAM only once and stored within the SCNN accelerator 200. In one embodiment, the layer sequencer 215 broadcasts a weight vector to each PE 210 and sequences through multiple activation vectors before broadcasting another weight vector. In one embodiment, the layer sequencer 215 broadcasts an input activation vector to each PE 210 and sequences through multiple weight vectors before broadcasting another input activation vector. Products generated by the multipliers within each PE 210 are accumulated to produce intermediate values (e.g., partial sums) that become the output activations after one or more iterations. When the output activations for a neural network layer have been computed and stored in an output activation buffer, the layer sequencer 215 may proceed to process a next layer by applying the output activations as input activations.) performs a multiply-accumulate operation by multiplying the activation data with the preloaded weight to generate a multiplication product, ([0066] To exploit the parallelism of many multipliers within a PE 220, a vector of F filter-weights may be fetched from the weight buffer 230 and a vector of I inputs may be fetched from the input activations buffer 235.) adds the multiplication product to the received output partial sum from each processing element in the previous row to generate the output partial sum of each processing element in the specific row, ([0093] The F*I arbitrated crossbar 335 transmits the products to the associated accumulator in the accumulator array 340 based on the product positions. The low bits of the linearized accumulator address are used by the F*I arbitrated crossbar 335 to route each product to an accumulator unit in the accumulator array 340 and the product is added to a partial sum by the adder within the accumulator array 340 that is selected by the high bits of the address.) and transmits the output partial sum to each processing element in a next row. ([0048] When the output activations for a neural network layer have been computed and stored in an output activation buffer, the layer sequencer 215 may proceed to process a next layer by applying the output activations as input activations.)
It would have been obvious to a person skilled in the art before the effective filing date of the
invention to have combined with DALLY‘s weight buffer and calculation and, with AYDONAT‘s, as modified by HUANG, SONG, and YOON, CNN accelerator circuit and PE arrays, with a reasonable expectation of success, a weight buffer and calculation, as in DALLY, which is applied to a CNN accelerator circuit and PE array data, as found in AYDONAT, as modified by HUANG, SONG, and YOON. A person of ordinary skill would have been motivated to lower energy consumption (DALLY [0005]).
Regarding claim 8, YOON further teaches:
The accelerator circuit of Claim 6, wherein, for each sub PE array during the second configuration, when a specific row of the processing elements is not the bottom row, ([0054] An intermediate result, which may be the partial sum output by the adder 630 in a MAC unit that is not in the bottom row of the systolic array)
DALLY further teaches:
each processing element of the specific row receives an output partial sum from each processing element in a previous row of the processing elements, performs a multiply-accumulate operation by multiplying the weight with the preloaded activation data to generate a multiplication product, ([0048] The layer sequencer 215 reads the weights and outputs weight vectors to be multiplied by the PEs 210. In one embodiment, the weights are in compact form and are read from off-chip DRAM only once and stored within the SCNN accelerator 200. In one embodiment, the layer sequencer 215 broadcasts a weight vector to each PE 210 and sequences through multiple activation vectors before broadcasting another weight vector. In one embodiment, the layer sequencer 215 broadcasts an input activation vector to each PE 210 and sequences through multiple weight vectors before broadcasting another input activation vector. Products generated by the multipliers within each PE 210 are accumulated to produce intermediate values (e.g., partial sums) that become the output activations after one or more iterations. When the output activations for a neural network layer have been computed and stored in an output activation buffer, the layer sequencer 215 may proceed to process a next layer by applying the output activations as input activations.) adds the multiplication product to the received output partial sum from each processing element in the previous row to generate the output partial sum of each processing element in the specific row, ([0093] The F*I arbitrated crossbar 335 transmits the products to the associated accumulator in the accumulator array 340 based on the product positions. The low bits of the linearized accumulator address are used by the F*I arbitrated crossbar 335 to route each product to an accumulator unit in the accumulator array 340 and the product is added to a partial sum by the adder within the accumulator array 340 that is selected by the high bits of the address.) and transmits the output partial sum to each processing element in a next row. ([0048] When the output activations for a neural network layer have been computed and stored in an output activation buffer, the layer sequencer 215 may proceed to process a next layer by applying the output activations as input activations.)
Regarding claims 16-17, they comprise of limitations similar to those of claims 7-8 and are therefore rejected for similar rationale.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over AYDONAT (E.P. Pub. No. EP 3153996 A2) in further view of HU (U.S. Pub. No. US 20230161556 A1) in further view of HUANG (U.S. Pub. No. US 20180173571 A1)
Regarding claim 11, AYDONAT substantially teaches the claimed invention, including:
A semiconductor device, comprising a plurality of sub processing-element (PE) arrays, wherein each sub PE array comprises a plurality of processing elements ([0043] Figure 9 is a block diagram of an exemplary CNN accelerator 900 that may be used to implement a CNN according to an embodiment of the present invention. The CNN accelerator 900 allows for efficient computation of forward propagation of convolution and other layers. [0045] Input image pixels are transmitted into the processing element (PE) arrays 901-904 which may perform independent dot-product operations in a convolution procedure. PE array 901 represents a first PE array and PE array 904 represents an nth PE array, where n can be scaled to any number.) and a weight buffer, ( [0017] The coefficients 321-323 apply weights which formulate a filter for the convolution layer. [0067] At 1302, coefficient data is stored on an on-chip buffer. (weights are coefficients, as seen here, the coefficients must be weights to apply weights to the CNN))
While AYDONAT does teach PE arrays and a weight buffer, it does not explicitly teach:
wherein the processing elements in each sub PE array are implemented on a first die plane, and the weight buffer in each sub PE array is implemented on a second die plane that is on top of the first die plane,
However, in analogous art that similarly handles weight data and PE arrays, HU teaches:
wherein the processing elements in each sub PE array are implemented on a first die plane, and the weight buffer in each sub PE array is implemented on a second die plane that is on top of the first die plane, ([0068] The memory die 615 includes a plurality of memory planes (MP) 620, a plurality of page buffers (PB) 625 and an accumulation circuit 630. In FIG. 6, the memory die 615 includes four memory planes 620 and four page buffers 625, but the application is not limited by this. The memory plane 620 includes a plurality of memory cells (not shown). The weight data is stored in the memory cells.
[0069] In each memory die 615, the accumulation circuit 630 is shared by the memory planes 620 and thus the accumulation circuit 630 sequentially performs the accumulation operations of the memory planes 620. Further, each memory die 615 may independently execute the above digital MAC operations and the digital Hamming distance operations.)
It would have been obvious to a person skilled in the art before the effective filing date of the
invention to have combined with HU‘s die planes and, with AYDONAT‘s CNN accelerator circuit and PE arrays and buffer, with a reasonable expectation of success, performing calculations on a die plane, as in HU, which is applied to a CNN accelerator circuit and PE array data, as found in AYDONAT. A person of ordinary skill would have been motivated to improve performance (HU [0023]).
AYDONAT further teaches:
and wherein the processing elements in each of the plurality sub PE arrays implement a standard convolutional layer during a first configuration applied to the semiconductor device, (([0009] According to an embodiment of the present invention, a CNN accelerator implemented on a target includes a sequencer unit that coordinates a first data flow between components on the target during a first configuration and that coordinates a second data flow between components on the target during a second configuration. The CNN accelerator also includes a plurality of processing elements that implement a standard convolutional layer during the first configuration))
While AYDONAT does teach an accelerator circuit that implements PE arrays, it does not explicitly teach:
and implement a depth-wise convolutional layer during a second configuration applied to the accelerator circuit.
However, in analogous art that similarly implements a CNN, HUANG teaches:
and implement a depth-wise convolutional layer during a second configuration applied to the accelerator circuit. ([0140] In some cases, the same configurations can be adapted for a depthwise convolution layer. Alternatively, a variation of configuration may be used for the depthwise convolution layer. )
It would have been obvious to a person skilled in the art before the effective filing date of the
invention to have combined with HUANG‘s depth-wise CNN and, with AYDONAT‘s, as modified by HU, CNN accelerator circuit, with a reasonable expectation of success, a depth-wise CNN, as in HUANG, where the CNN is implemented by an accelerator circuit, as found in AYDONAT, as modified by HU. A person of ordinary skill would have been motivated to lower power consumption (HUANG [0003]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over AYDONAT (E.P. Pub. No. EP 3153996 A2), HUANG (U.S. Pub. No. US 20180173571 A1), HU (U.S. Pub. No. US 20230161556 A1) in further view of DONO (U.S. Pub. No. US 20180025789 A1)
While AYDONAT, as modified by HUANG and HU, does teach claim 11, which claim 18 is dependent upon, it does not explicitly teach:
The semiconductor device of Claim 11, wherein the weight buffer communicates with the processing elements in each sub PE array through a local TSV (through-silicon via) array of each sub PE array.
However, in analogous art that similarly uses arrays, DONO teaches:
The semiconductor device of Claim 11, wherein the weight buffer communicates with the processing elements in each sub PE array through a local TSV (through-silicon via) array of each sub PE array. ([0051] FIG. 12A is a schematic diagram of a multiplexer MUXA, in accordance with an embodiment of the present disclosure. For example, the multiplexer MUXA 121 may receive an input signal A at a node A and an input signal B at a node B and may provide either the input signal A or the input signal B as an output signal O at a node O responsive to a select signal SEL at a node SEL representing either “0” or “1”. In the remapping circuit 13 of FIG. 11, the plurality of multiplexers MUXA 121 may be arranged in a manner that a plurality of multiplexers MUXA 121a receive an adjacent pairs of the internal signals Int_Rise[0:9] signals and Int_Fall [0:9] signals via buffers and provide Tsv_Rise[0:9] signals and Tsv_Fall [0:9] signals to the TSV array sub region 14 via buffers responsive to the Lane_Shift_Enable[0:9] signals. Furthermore, a plurality of multiplexers MUXA 121b receive an adjacent pairs of Tsv_Rise[0:9] signals and Tsv_Fall [0:9] signals from the TSV array sub region 14 via buffers and provide the internal signals Int_Rise[0:9] signals and Int_Fall [0:9] signals via buffers responsive to the Lane_Shift_Enable[0:9] signals.)
It would have been obvious to a person skilled in the art before the effective filing date of the
invention to have combined with DONO‘s TSV and, with AYDONAT‘s, as modified by HUANG and HU, semiconducter and PE arrays and buffer, with a reasonable expectation of success, transporting data through a TSV, as in DONO, which is applied to a semiconducter and PE array data, as found in AYDONAT, as modified by HUANG and HU. A person of ordinary skill would have been motivated to improve chip performance (DONO [0001]).
Allowable Subject Matter
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments filed 16-JANURARY-2026 have been fully considered, but they are found to be non-persuasive
With regards to the applicant’s remarks regarding the 103 rejection in the non-final action, the applicant argues that the prior art does not teach the newly amended claims 1. The examiner acknowledges this argument and has adjusted the mappings of claim 1 to reflect the changes made to claim 1. Applicant argues:
First, based on paragraph [0024] of Song, the MAC circuit 10 may receive the weight data DW<127:0> and constant data DC<15:0> from the memory region. Accordingly, the constant data DC<15:0> is not a partial sum generated a sub PE within sub PE arrays.
With regards to this argument, it is true that SONG, by itself, does not teach the partial sum generation. However, SONG is combined with prior art AYDONAT. AYDONAT does teach the partial sum generation. One of ordinary skill in the art would be able to use the partial sums generated by AYDONAT in place of the data shown in SONG. As such, SONG has no further burden to reteach the generated partial sums.
Second, based on paragraph [0030] of Song, it can be understood that the replica constant data DC<127:0> generated by the bit copy block 122 is comprised of a plurality of copied constant data DC<15:0>. This indicates that the bit copy block 122 duplicates the constant data DC<15:0> (e.g., 16 bits) 8 times to generate the replica constant data DC<127:0> (e.g., 128 bits). In other words, the replica constant data DC<127:0> in Song is not a concatenated partial sum obtained from the partial sum generated by each sub PE array when the flag signal FLAG having a logic “high” level.
With regards to this argument, again it must be remembered that SONG has no further burden to reteach the generated partial sums. SONG teaches concatenating the data into the constant data. One of ordinary skill in the art can replace the data with the partial sums as taught by AYDONAT.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SKIELER A KOWALIK whose telephone number is (571)272-1850. The examiner can normally be reached 8-5.
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/SKIELER ALEXANDER KOWALIK/Examiner, Art Unit 2142 /Mariela Reyes/Supervisory Patent Examiner, Art Unit 2142
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