Prosecution Insights
Last updated: October 27, 2026
Application No. 18/156,414

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Jan 19, 2023
Priority
Oct 12, 2022 — provisional 63/415,288
Examiner
PIZARRO CRESPO, MARCOS D
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
3 (Non-Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
381 granted / 572 resolved
-1.4% vs TC avg
Moderate +14% lift
Without
With
+14.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
31 currently pending
Career history
601
Total Applications
across all art units

Statute-Specific Performance

§103
54.8%
+14.8% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
17.7%
-22.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§102 §103
Attorney’s Docket Number: 122750-US-PA Filing Date: 1/19/2023 Claimed Priority Date: 10/12/2022 (US 63/415,288) Inventors: Chang et al. Examiner: Marcos D. Pizarro DETAILED ACTION This Office action responds to the amendment filed on 5/22/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Continued Examination Under 37 CFR 1.114 A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after the final rejection in paper no. 7, mailed on 2/24/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/22/2026 has been entered. Amendment Status The RCE submission filed on 5/22/2026, as an amendment in reply to the Office action in paper no. 7, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1, 2, 5-12, 14, 15 and 21-28. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the spacing pattern of claim 9 must be shown or the feature canceled from the claim. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baello (US 10,593,640). Regarding claim 1, Baello (see, e.g., figs. 4 and 11) shows all aspects of the instant invention including a semiconductor package comprising: A first semiconductor substrate 403 comprising a first pad region and a plurality of first pads 405 within the first pad region A plurality of conductive bumps 413 on the first pads A second semiconductor substrate 409 bonded to the first substrate and comprising a plurality of second pads bonded to the bumps A spacing pattern 411 integrally formed on the first substrate and in contact with the second substrate wherein: The spacing pattern comprises a plurality of discrete spacers 1131 disposed at a plurality of corners of the first pad region The spacers collectively define a peripheral boundary of the first pad region enclosing the first pads Regarding claim 25, Baello (see, e.g., fig. 4) shows that the pitch between two adjacent spacers 411 is greater than the pitch between two adjacent first pads 405. Claims 21, 23, 24, 1, 2, 6 and 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Molina (US 2023/0106976). Regarding claim 21, Molina (see, e.g., figs. 1G, 1I and 2G) shows all aspects of the instant invention including a semiconductor package 300 comprising: A first semiconductor device 170 comprising a plurality of first pads 106 A second semiconductor device 260 over the first device and comprising a plurality of second pad 261 A plurality of conductive bumps 119/144 bonded between the first and second pads A spacing pattern 126 protruding from a topmost layer of the first device and defining a boundary of the pad region wherein the first pads are disposed within the pad region. Regarding claim 23, Molina (see, e.g., fig. 2G) shows that a top surface of the spacing pattern 126 is not coplanar with the top surface of the topmost layer of the first device 170. Regarding claim 1, Molina (see, e.g., figs. 1G and 2G) shows all aspects of the instant invention including a semiconductor package comprising: A first semiconductor substrate 105 comprising a first pad region and plurality of first pads 106 within the first pad region A plurality of bumps 119/144 disposed on the first pads A second semiconductor substrate 260 bonded to the first substrate and comprising a plurality of second pads 261 bonded to the bumps, and A spacing pattern 126 integrally formed on the first substrate and in contact with the second substrate Wherein: The spacing pattern comprises a plurality of discrete spacers at a plurality of corners of the first pad region The spacers collectively define a peripheral boundary of the first pad region enclosing the first pads Regarding claims 2, and 24, Molina (see, e.g., fig. 1I) shows that the bumps comprise a metal pillar 119 and a solder cap 144 over the pillar, wherein a height of the spacing pattern 126 is substantially greater than the height of the pillar. Regarding claim 6, Molina (see, e.g., ¶0029/l.2) teaches that the melting temperature of the material of the spacing pattern 126 is substantially equal to or greater than 200°C. Regarding claim 7, Molina (see, e.g., ¶0029/l.2) teaches that the material of the spacing pattern comprises Cu, Ni, Au, Co, PI or BCB. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 5 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Molina in view of Kim (US 2023/0119548). Regarding claims 5 and 22, Molina (see, e.g., fig. 2G) teaches a semiconductor package including first 105 and second 260 semiconductor devices. Molina further shows the supporting structure 126 formed between the first and second devices, the first device including a passivation layer 112 formed thereon, and the supporting structure contacting the passivation layer of the first device. However, Molina does not explicitly disclose that the second device 260 includes a second passivation layer such that the supporting structure contacts both passivation layers. Like Molina, Kim (see, e.g., fig. 7) teaches a semiconductor package 1000A that include first 100A and second 100B devices. Kim, however, shows both the first and second devices including passivation layers IL1/IL2. Kim expressly teaches that the passivation layers provide a bonding surface for bonding and coupling to an external device, e.g., a semiconductor chip, a substrate, or the like” (see, e.g., Kim: ¶0039/ll.15-19). Kim thus teaches the use of passivation layers as bonding interfaces for coupling semiconductor devices and associated structures. It would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention to modify the semiconductor package of Molina to include a passivation layer formed on the second device, as taught by Kim, such that the supporting structure contacts both the first and second passivation layers. Kim provides an express teaching that passivation layers serve as bonding surfaces for coupling semiconductor devices and related structures. The proposed modification merely applies a known technique, using a passivation layer as a bonding interface, to a known device, Molina’s second semiconductor device, to yield predictable results, a suitable bonding surface between the semiconductor devices. Providing analogous bonding interfaces on both devices would have been an obvious design choice to improve bonding reliability, interface uniformity, and manufacturing consistency within the semiconductor packaging art. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Molina in view of Lin (US 2021/0074661). Regarding claim 8, Molina (see, e.g., fig. 1G) shows the substrate further comprising a second pad region and a plurality of second pads in the second pad region, wherein the first pads have a first pitch, and the second pads have a second pitch. Molina, however, shows that the pads in the first and second regions have the same pitch. Lin teaches that pad pitches may be varied between different regions to effectively use the device to meet different electrical connection requirements, such as signal input/output and power supply/grounding. Lin further teaches that providing different pitches may result in improved signal integrity and power integrity. See, e.g., Lin: par.0032. It would have been obvious at the time of filing the invention to a PHOSITA to modify the package of Molina such that the pad pitch in the first region is different from the pad pitch in the second region, as taught by Lin. The motivation to do so would have been to meet different electrical connection requirements and improve signal integrity and power integrity. Allowable Subject Matter Claims 9, 10, 12, 14, 15 and 26 are allowed. Claims 27 and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments The applicant argues: The prior art of record fails to show a plurality of spacers at the corners of the pad region, the spacers collectively defining the peripheral boundary of the pad region. The examiner responds: The prior art of record shows these features of the amended claims. See, e.g., fig. 1G, where Molina shows a plurality of spacers 126 at the corners of the pad region, the spacers collectively defining the peripheral boundary of the pad region. Conclusion Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Marcos D. Pizarro/Primary Examiner, Art Unit 2814 MDP/mdp September 28, 2026
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Prosecution Timeline

Show 1 earlier event
Sep 24, 2025
Non-Final Rejection mailed — §102, §103
Dec 24, 2025
Response Filed
Feb 24, 2026
Final Rejection mailed — §102, §103
Apr 28, 2026
Applicant Interview (Telephonic)
Apr 28, 2026
Examiner Interview Summary
May 22, 2026
Request for Continued Examination
May 29, 2026
Response after Non-Final Action
Oct 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
81%
With Interview (+14.5%)
3y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

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