Prosecution Insights
Last updated: October 02, 2026
Application No. 18/156,449

INTEGRATED POWER MODULE PACKAGE OPENING WITH EXPOSED COMPONENT

Final Rejection §102§103
Filed
Jan 19, 2023
Examiner
NGUYEN, KHIEM D
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
3 (Final)
86%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1928 granted / 2248 resolved
+17.8% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
60 currently pending
Career history
2283
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
46.4%
+6.4% vs TC avg
§102
28.8%
-11.2% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2248 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Remarks The amendment filed on May 11th, 2026 has been acknowledged. By this amendment, claims 1-3, 8-11, 15, 17-19, 21, 25, 28, and 30 have been amended. Accordingly, claims 1-30 are pending in the present application in which claims 1, 4, 10, 12, 15, 21, 25, 28, and 30 are in independent form. Applicant’s amendment to claims 15 has obviated the 112(b) issue in the previous office action. Claim Objections Claims 1, 10, 17, 18, 20, 28, and 29 are objected to because of the following informalities: In claim 1, lines 6-7, “the electronic component” should be --the electronic components--. In claim 10, line 6, “coupled to circuit” should be --coupled to the circuit-- since “a circuit” has been defined in claim 10, line 4. In re claim 17, lines 1-2, “attaching the electronic component” should be --attaching the electronic components--. In claim 18, lines 1-2, “attaching the electronic component” should be --attaching the electronic components--. In claim 20, line 1, “attaching the electronic component” should be --attaching the electronic components--. In claim 28, line 4, “two or more electronic component” should be --two or more electronic components--. In claim 29, line 2, “the electronic component” should be --the electronic components--. Appropriate correction is required. New Grounds of Rejection Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 15, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Manack et al. (U.S. Pub. 2022/0059423). In re claim 15, Manack discloses a method of fabricating an electronic device 501, the method comprising attaching a semiconductor die 508 to a substrate or a die attach pad 502 (see paragraph [0037] and fig. 5A); performing an electrical connection process that couples the semiconductor die 508 to a circuit 510 (see paragraph [0037] and fig. 5A); forming a package structure 512 that encloses the semiconductor die 508 and having an opening 514 that exposes metal terminals 516 attached to the substrate or the die attach pad 502 (see paragraph [0038] and fig. 5A); and attaching electronic components (550,552,554) through the opening 514 to the metal terminals 516 (see paragraphs [0037], [0038] and fig. 5A). PNG media_image1.png 302 754 media_image1.png Greyscale In re claim 19, as applied to claim 15 above, Manack discloses wherein attaching the electronic components (550,552,554) includes soldering terminals of the electronic components (550,552,554) to the metal terminals 516 to couple the electronic components (550,552,554) to the circuit 510 (see paragraphs [0035], [0038] and fig. 5A). In re claim 20, as applied to claim 19 above, Manack discloses wherein attaching the electronic component (550,552,554) includes dispensing solder paste on the metal terminals 516; attaching terminals of the electronic components (550,552,554) on respective ones of the solder paste; and reflowing the solder paste to couple the electronic components (550,552,554) to the circuit 510 (see paragraph [0038] and fig. 5A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3, 8-11, and 28-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manack et al. (U.S. Pub. 2022/0059423) in view of Jow (U.S. Pub. 2008/0067641). In re claim 1, Manack discloses an electronic device 501, comprising a semiconductor die 508 attached to a die attach pad 502 and coupled to a circuit 510 of the electronic device 501 (see paragraph [0037] and fig. 5A); two or more electronic components (550,552,554) coupled to the circuit 510 (see paragraph [0037] and fig. 5A); and a package structure 512 that encloses the semiconductor die 508, the package structure 512 having an opening 514 that exposes a top and at least partial side portions of the electronic component (550,552,554) (see paragraph [0038] and fig. 5A). Manack discloses that the semiconductor die is attached to the die attach pad but is silent to wherein the semiconductor die is attached to a substrate. However, Jow discloses in a same field of endeavor, an electronic device 10, including, inter-alia, a semiconductor die (30,40) attached to a die attach pad 26 (see paragraph [0018] and fig. 2) or to a substrate 15 (see paragraph [0021] and fig. 3). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Jow into the electronic device of Manack in order to enable the semiconductor die to be attached to a substrate in Manack to be formed because Jow provides evidence that it is well-known in the art to attach the semiconductor die to either a die attach pad or to a substrate in order to obtain a package structure. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 2, as applied to claim 1 above, Manack in combination with Jow discloses wherein the electronic device further comprising a conductive lead 504 that is coupled to the circuit 510 and extends outward from the package structure 512; and metal terminals 516 attached to the substrate, the electronic components (550,552,554) being coupled to respective ones of the metal terminals 516 (see paragraphs [0037], [0038] and fig. 5A of Manack). In re claim 3, as applied to claim 2 above, Manack in combination with Jow discloses wherein one of the metal terminals 516 is coupled to the conductive lead 504; and the electronic component (550,552,554) is soldered to one of the metal terminals 516 (see paragraphs [0035], [0038] and fig. 5A of Manack). In re claim 8, as applied to claim 1 above, Manack in combination with Jow discloses wherein the electronic components (550,552,554) are passive circuit components (see paragraph [0040] and fig. 5A of Manack). In re claim 9, as applied to claim 8 above, Manack in combination with Jow discloses wherein each of the electronic components has terminals soldered to respective metal terminals 516 of the electronic device (see paragraph [0038] and fig. 5A of Manack). In re claim 10, Manack discloses a system, comprising a circuit board 150; and an electronic device 100 attached to the circuit board 150 (see paragraph [0030] and fig. 1D), the electronic device comprising a semiconductor die 508 attached to a die attach pad 502 and coupled to a circuit 510 of the electronic device (see paragraph [0037] and fig. 5A); two or more electronic components (550,552,554) coupled to circuit 510 (see paragraph [0037] and fig. 5A); a package structure 512 that encloses the semiconductor die 508, the package structure 512 having an opening 514 that exposes a top and at least partial side portions of the electronic components (550,552,554) (see paragraph [0038] and fig. 5A); and a conductive lead 504 that is coupled to the circuit 510 and extends outward from the package structure 512 (see paragraph [0038] and fig. 5A), the conductive lead coupled to the circuit board 150 (see paragraph [0030] and fig. 1B). Manack discloses that the semiconductor die is attached to the die attach pad but is silent to wherein the semiconductor die is attached to a substrate. However, Jow discloses in a same field of endeavor, an electronic device 10, including, inter-alia, a semiconductor die (30,40) attached to a die attach pad 26 (see paragraph [0018] and fig. 2) or to a substrate 15 (see paragraph [0021] and fig. 3). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Jow into the electronic device of Manack in order to enable the semiconductor die to be attached to a substrate in Manack to be formed because Jow provides evidence that it is well-known in the art to attach the semiconductor die to either a die pad or to a substrate in order to obtain a package structure. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 11, as applied to claim 10 above, Manack in combination with Jow discloses wherein the electronic device further comprises a conductive lead 504 that is coupled to the circuit 510 and extends outward from the package structure 512; and a metal terminal 516 attached to the substrate, one of the electronic components (550,552,554) being coupled to the metal terminal 516 (see paragraphs [0037], [0038] and fig. 5A of Manack). In re claim 28, Manack discloses an electronic device 501, comprising a semiconductor die 508 attached to a die attach pad 502 and coupled to a circuit 510 of the electronic device 501 (see paragraph [0037] and fig. 5A); two or more electronic component (550,552,554) coupled to the circuit 510 (see paragraph [0037] and fig. 5A); and a package structure 512 that encloses the semiconductor die 508, the package structure 512 having a tapered opening 514 that exposes a portion of the electronic components (550,552,554) (see paragraph [0038] and fig. 5A). Manack discloses that the semiconductor die is attached to the die attach pad but is silent to wherein the semiconductor die is attached to a substrate. However, Jow discloses in a same field of endeavor, an electronic device 10, including, inter-alia, a semiconductor die (30,40) attached to a die attach pad 26 (see paragraph [0018] and fig. 2) or to a substrate 15 (see paragraph [0021] and fig. 3). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Jow into the electronic device of Manack in order to enable the semiconductor die to be attached to a substrate in Manack to be formed because Jow provides evidence that it is well-known in the art to attach the semiconductor die to either a die pad or to a substrate in order to obtain a package structure. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 29, as applied to claim 28 above, Manack in combination with Jow discloses wherein no portion of the package structure 512 contacts the electronic component (see paragraph [0038] and fig. 5A of Manack). In re claim 30, Manack discloses an electronic device 501, comprising a semiconductor die 508 attached to a die attach pad 502 and coupled to a circuit 510 of the electronic device 501 (see paragraph [0037] and fig. 5A); two or more electronic components (550,552,554) coupled to the circuit 510; and a package structure 512 that encloses the semiconductor die 508, the package structure 512 having an opening 514 that exposes a portion of the electronic components (550,552,554), wherein no portion of the package structure 512 contacts the electronic components (550,552,554) (see paragraph [0038] and fig. 5A). Manack discloses that the semiconductor die is attached to the die pad but is silent to wherein the semiconductor die is attached to a substrate. However, Jow discloses in a same field of endeavor, an electronic device 10, including, inter-alia, a semiconductor die (30,40) attached to a die pad 26 (see paragraph [0018] and fig. 2) or to a substrate 15 (see paragraph [0021] and fig. 3). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Jow into the electronic device of Manack in order to enable the semiconductor die to be attached to a substrate in Manack to be formed because Jow provides evidence that it is well-known in the art to attach the semiconductor die to either a die pad or to a substrate in order to obtain a package structure. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manack et al. (U.S. Pub. 2022/0059423), as applied to claim 15 above, and further in view of Jow (U.S. Pub. 2008/0067641). In re claim 16, as applied to claim 15 above, Manack is silent to wherein forming the package structure includes performing a molding process with a mold feature engaging a surface of the metal terminal to create the opening of the package structure. However, Jow discloses in a same field of endeavor, a method of fabricating an electronic device, including, inter-alia, the step of forming the package structure 50 includes performing a molding process with a mold feature (a upper mold 92 and a lower mold 94) engaging a surface of the metal terminal to create the opening 60 of the package structure 50 (see paragraphs [0027], [0028], [0029] and fig. 5B of Jow). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Jow into the electronic device of Manack in order to enable the step of forming the package structure includes performing a molding process with a mold feature engaging a surface of the metal terminal to create the opening of the package structure in Manack to be performed in order to provide passive component in the opening (see Abstract of Jow). In re claim 17, as applied to claim 16 above, Manack in combination with Jow discloses wherein attaching the electronic component (550,552,554) includes soldering terminals of the electronic components (550,552,554) to respective ones of the metal terminals 516 to couple the electronic component (550,552,554) to the circuit 510 (see paragraph [0037] and fig. 5A of Manack). In re claim 18, as applied to claim 16 above, Manack in combination with Jow discloses wherein attaching the electronic component (550,552,554) includes dispensing solder paste on the metal terminals 516; attaching terminals of the electronic components (550,552,554) on respective ones of the solder paste; and reflowing the solder paste to couple the electronic components (550,552,554) to the circuit 510 (see paragraph [0038] and fig. 5A of Manack). Allowable Subject Matter Claims 4-7, 12-14, and 21-27 are allowed over prior art of record. Reasons For Allowance The following is an examiner’s statement of reasons for allowance: It is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of independent claims 4, 12, 21, and 25 as a whole taken alone or in combination, in particular, prior art of record does not teach “a second semiconductor die attached to the substrate and having a second transistor with a drain coupled to the second metal terminal and a source coupled to the switching mode, the first conductive lead is coupled to the first metal terminal to form a reference node of the circuit, the second conductive lead is coupled to the switching mode of the circuit, and the third conductive lead is coupled to the second metal terminal to form an input node of the circuit", as recited in independent claim 4, “the electronic device includes a second semiconductor die, first, second, and third conductive leads, and first and second metal terminals, the semiconductor die is a first semiconductor die attached to the substrate and having a first transistor with drain coupled to a switching node of the circuit and a source coupled to the first metal terminal, the second semiconductor die is attached to the substrate and has a second transistor with drain coupled to the second metal terminal and a source coupled to the switching mode, the first conductive lead is coupled to the first metal terminal to form a reference node of the circuit, the second conductive lead is coupled to the switching node of the circuit, and the third conductive lead is coupled to the second metal terminal to form an input node of the circuit”, as recited in independent claim 12, “the second semiconductor die is attached to the substrate and has a second transistor with a drain coupled to the second metal terminal and a source coupled to the switching node; the first conductive lead is coupled to the first metal terminal to form a reference node of the circuit; the second conductive lead is coupled to the switching node of the circuit; and the third conductive lead is coupled to the second metal terminal to form an input node of the circuit”, as recited in independent claim 21, and “the second semiconductor die is attached to the substrate and has a second transistor with a drain coupled to the second metal terminal and a source coupled to the switching node; the first conductive lead is coupled to the first metal terminal to form a reference node of the circuit; the second conductive lead is coupled to the switching node of the circuit; and the third conductive lead is coupled to the second metal terminal to form an input node of the circuit”, as recited in independent claim 25. Claims 5-7, 13, 14, 22-24, 26, and 27 also allowed as being directly or indirectly dependent of the allowed independent base claims. Response to Applicant’s Amendment and Arguments Applicant’s arguments with respect to claim(s) 1-3, 8-11, 15-20, and 28-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Jan 19, 2023
Application Filed
Jun 16, 2025
Non-Final Rejection mailed — §102, §103
Nov 17, 2025
Response Filed
Feb 17, 2026
Non-Final Rejection mailed — §102, §103
May 11, 2026
Response Filed
Aug 07, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
86%
Grant Probability
98%
With Interview (+12.5%)
2y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 2248 resolved cases by this examiner. Grant probability derived from career allowance rate.

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